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minitest: litex: litesata: fix Makefile and build process 

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2021-01-22 13:40:35 +01:00
parent 8210db1aa5
commit f5dfb69d19
4 changed files with 22 additions and 22 deletions
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1
minitests/litex/nexys_video_sata/.gitignore vendored
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@ -4,3 +4,4 @@ src
# Build data
build*
sata.*
*.ok

16
minitests/litex/nexys_video_sata/Makefile vendored
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@ -13,14 +13,20 @@ YOSYS = $(XRAY_DIR)/third_party/yosys/yosys
PART = xc7a200tsbg484-1
PROJECT_NAME = sata
all: $(PROJECT_NAME).fasm
clean:
@find . -name "build-par.*" | xargs rm -rf
@find . -name "build-syn.*" | xargs rm -rf
@rm -rf build*
@rm -f *.edif
@rm -f *.bit
@rm -f *.bin
@rm -f *.log
@rm -f *.dcp
@rm -f *.fasm
clean_litex:
@rm -rf ${VIRTUAL_ENV}/src
@rm -f litex-install.ok
help:
@echo "Usage: make all [SYNTH=<vivado/yosys>]"
@ -35,15 +41,15 @@ litex-install.ok:
touch litex-install.ok
build/build.ok: litex-install.ok
./src/litex-boards/litex_boards/targets/nexys_video.py --with-sata --integrated-rom-size 0x10000
${VIRTUAL_ENV}/src/litex-boards/litex_boards/targets/nexys_video.py --with-sata --integrated-rom-size 0x10000
touch build/build.ok
VERILOG_FILES = ./build/nexys_video/gateware/nexys_video.v \
./src/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v
${VIRTUAL_ENV}/src/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v
ifeq ($(SYNTH), yosys)
$(PROJECT_NAME).edif: $(YOSYS) build/build.ok
$(YOSYS) -p "read_verilog $(VERILOG_FILES); techmap -map retarget.v; synth_xilinx -flatten -nosrl; write_edif -pvector bra -attrprop $@" -l $@.log
$(YOSYS) -p "read_verilog $(VERILOG_FILES); techmap -map retarget.v; synth_xilinx -flatten -nosrl -nodsp; write_edif -pvector bra -attrprop $@" -l $@.log
else ifeq ($(SYNTH), vivado)
$(PROJECT_NAME).edif: build/build.ok tcl/syn.tcl

25
minitests/litex/nexys_video_sata/requirements.txt vendored
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@ -1,21 +1,14 @@
# Litex
-e git+https://github.com/enjoy-digital/litex#egg=litex
-e git+https://github.com/enjoy-digital/litedram#egg=litedram
-e git+https://github.com/enjoy-digital/liteeth#egg=liteeth
-e git+https://github.com/enjoy-digital/liteiclink#egg=liteiclink
-e git+https://github.com/enjoy-digital/litejesd204b#egg=litejesd204b
-e git+https://github.com/enjoy-digital/litepcie#egg=litepcie
-e git+https://github.com/enjoy-digital/litesata#egg=litesata
-e git+https://github.com/enjoy-digital/litescope#egg=litescope
-e git+https://github.com/enjoy-digital/litesdcard#egg=litesdcard
-e git+https://github.com/enjoy-digital/litevideo#egg=litevideo
-e git+https://github.com/litex-hub/litehyperbus#egg=litehyperbus
-e git+https://github.com/litex-hub/litespi#egg=litespi
-e git+https://github.com/litex-hub/litex-boards#egg=litex_boards
-e git+https://github.com/enjoy-digital/litex@e8cfe3b6ea4d8fbea0080d5cae4302169fc804cb#egg=litex
-e git+https://github.com/enjoy-digital/litedram@ab2423e3dd06783d80fef7aeb43b7c5513c1f2f0#egg=litedram
-e git+https://github.com/enjoy-digital/liteeth@7448170390ddf4b7c353ae10932377255581c25a#egg=liteeth
-e git+https://github.com/enjoy-digital/liteiclink@0980a7cf4ffcb0b69a84fa0343a66180408b2a91#egg=liteiclink
-e git+https://github.com/enjoy-digital/litesata@fae9f8d5b7b6d4c6a0a93b496bd15db5201d14f7#egg=litesata
-e git+https://github.com/litex-hub/litex-boards@bee71da7746c6fda0d4e1942452510e11f06c14a#egg=litex_boards
# Migen and nMigen
-e git+https://github.com/m-labs/migen#egg=migen
-e git+https://github.com/nmigen/nmigen#egg=nmigen
-e git+https://github.com/m-labs/migen@40b1092a05ec7659c42c8087b0c229dcfb5d9ca1#egg=migen
-e git+https://github.com/nmigen/nmigen@490fca57457b16421f7b3f2c7812bb229b17744a#egg=nmigen
-e git+https://github.com/litex-hub/pythondata-cpu-vexriscv#egg=pythondata_cpu_vexriscv
-e git+https://github.com/litex-hub/pythondata-cpu-vexriscv@16c5dded21ca50b73a2bdafab10eeef2ca816818#egg=pythondata_cpu_vexriscv

2
minitests/litex/nexys_video_sata/tcl/syn.tcl vendored
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@ -7,7 +7,7 @@
# SPDX-License-Identifier: ISC
create_project -force -name $env(PROJECT_NAME) -part $env(XRAY_PART)
read_verilog ../build/nexys_video/gateware/nexys_video.v ../src/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v
read_verilog ../build/nexys_video/gateware/nexys_video.v $env(VIRTUAL_ENV)/src/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v
synth_design -top nexys_video -max_dsp 0