mirror of https://github.com/openXC7/prjxray.git
minitests: Add min litex with DDR test
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
This commit is contained in:
Tomasz Michalak
parent
332f020dda
commit
18acada713
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@ -0,0 +1,99 @@
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#!/usr/bin/env python3
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# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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from migen import *
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from litex.boards.platforms import arty
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT41K128M16
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from litedram.phy import s7ddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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# # #
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pll_clkin = Signal()
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self.specials += Instance(
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"BUFG", i_I=platform.request("clk100"), o_O=pll_clkin)
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(~platform.request("cpu_reset"))
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pll.register_clkin(pll_clkin, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4 * sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# BaseSoC ------------------------------------------------------------------------------------------
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class MinSoC(SoCSDRAM):
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def __init__(
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self, sys_clk_freq=int(50e6), integrated_rom_size=0x8000,
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**kwargs):
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platform = arty.Platform()
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(
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self,
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platform,
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clk_freq=sys_clk_freq,
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integrated_rom_size=integrated_rom_size,
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integrated_sram_size=0x8000,
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cpu_variant="lite",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
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platform.request("ddram"),
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memtype="DDR3",
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nphases=4,
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sys_clk_freq=sys_clk_freq)
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self.add_csr("ddrphy")
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sdram_module = MT41K128M16(sys_clk_freq, "1:4")
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self.register_sdram(
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self.ddrphy,
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geom_settings=sdram_module.geom_settings,
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timing_settings=sdram_module.timing_settings)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Arty")
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builder_args(parser)
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soc_sdram_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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cls = MinSoC
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soc = cls(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args))
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if __name__ == "__main__":
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main()
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@ -0,0 +1,33 @@
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PART = xc7a35tcsg324-1
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BIT2FASM_ARGS = --part "$(XRAY_DIR)/database/artix7/$(PART)" --verbose
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SOURCES = ../verilog/mem.init ../verilog/mem_1.init ../verilog/top.v ../verilog/VexRiscv_Lite.v
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all: top.fasm top.bits segprint.log
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clean:
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@rm -f *.bit
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@rm -f *.bin
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@rm -f *.bits
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@rm -f *.fasm
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@rm -f *.log
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@rm -rf build
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.PHONY: all clean
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top.bit: $(VIVADO) $(SOURCES) top.xdc top.tcl
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mkdir -p build
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cd build && $(XRAY_VIVADO) -mode batch -source ../top.tcl -nojournal -tempDir build -log vivado.log -verbose
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cp build/*.bit ./
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top.fasm: top.bit
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PYTHONPATH="$(XRAY_DIR):$(XRAY_DIR)/utils:$(XRAY_DIR)/third_party/fasm" \
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PATH="$(XRAY_DIR)/build/tools:$(PATH)" \
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$(XRAY_BIT2FASM) $(BIT2FASM_ARGS) \
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top.bit >top.fasm \
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|| (rm -f top.fasm && exit 1)
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top.bits: top.bit
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$(XRAY_BITREAD) -part_file $(XRAY_DIR)/database/artix7/$(PART).yaml -o top.bits -z -y top.bit
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segprint.log: top.bits
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$(XRAY_SEGPRINT) -z -D -b top.bits > segprint.log
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@ -0,0 +1,27 @@
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create_project -force -name top -part xc7a35ticsg324-1L
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add_files {../../verilog/top.v}
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add_files {../../verilog/VexRiscv_Lite.v}
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read_xdc ../top.xdc
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synth_design -top top -part xc7a35ticsg324-1L
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report_timing_summary -file top_timing_synth.rpt
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report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
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report_utilization -file top_utilization_synth.rpt
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opt_design
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place_design
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report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
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report_utilization -file top_utilization_place.rpt
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report_io -file top_io.rpt
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report_control_sets -verbose -file top_control_sets.rpt
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report_clock_utilization -file top_clock_utilization.rpt
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route_design
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phys_opt_design
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report_timing_summary -no_header -no_detailed_paths
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write_checkpoint -force top_route.dcp
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report_route_status -file top_route_status.rpt
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report_drc -file top_drc.rpt
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report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
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report_power -file top_power.rpt
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
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write_bitstream -force top.bit
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write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
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quit
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@ -0,0 +1,230 @@
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## serial:0.tx
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set_property LOC D10 [get_ports serial_tx]
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set_property IOSTANDARD LVCMOS33 [get_ports serial_tx]
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## serial:0.rx
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set_property LOC A9 [get_ports serial_rx]
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set_property IOSTANDARD LVCMOS33 [get_ports serial_rx]
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## clk100:0
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set_property LOC E3 [get_ports clk100]
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set_property IOSTANDARD LVCMOS33 [get_ports clk100]
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## cpu_reset:0
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set_property LOC C2 [get_ports cpu_reset]
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set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
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## ddram:0.a
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set_property LOC R2 [get_ports ddram_a[0]]
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set_property SLEW FAST [get_ports ddram_a[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[0]]
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## ddram:0.a
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set_property LOC M6 [get_ports ddram_a[1]]
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set_property SLEW FAST [get_ports ddram_a[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[1]]
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## ddram:0.a
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set_property LOC N4 [get_ports ddram_a[2]]
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set_property SLEW FAST [get_ports ddram_a[2]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[2]]
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## ddram:0.a
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set_property LOC T1 [get_ports ddram_a[3]]
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set_property SLEW FAST [get_ports ddram_a[3]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[3]]
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## ddram:0.a
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set_property LOC N6 [get_ports ddram_a[4]]
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set_property SLEW FAST [get_ports ddram_a[4]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[4]]
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## ddram:0.a
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set_property LOC R7 [get_ports ddram_a[5]]
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set_property SLEW FAST [get_ports ddram_a[5]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[5]]
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## ddram:0.a
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set_property LOC V6 [get_ports ddram_a[6]]
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set_property SLEW FAST [get_ports ddram_a[6]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[6]]
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## ddram:0.a
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set_property LOC U7 [get_ports ddram_a[7]]
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set_property SLEW FAST [get_ports ddram_a[7]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[7]]
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## ddram:0.a
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set_property LOC R8 [get_ports ddram_a[8]]
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set_property SLEW FAST [get_ports ddram_a[8]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[8]]
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## ddram:0.a
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set_property LOC V7 [get_ports ddram_a[9]]
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set_property SLEW FAST [get_ports ddram_a[9]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[9]]
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## ddram:0.a
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set_property LOC R6 [get_ports ddram_a[10]]
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set_property SLEW FAST [get_ports ddram_a[10]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[10]]
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## ddram:0.a
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set_property LOC U6 [get_ports ddram_a[11]]
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set_property SLEW FAST [get_ports ddram_a[11]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[11]]
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## ddram:0.a
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set_property LOC T6 [get_ports ddram_a[12]]
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set_property SLEW FAST [get_ports ddram_a[12]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[12]]
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## ddram:0.a
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set_property LOC T8 [get_ports ddram_a[13]]
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set_property SLEW FAST [get_ports ddram_a[13]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[13]]
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## ddram:0.ba
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set_property LOC R1 [get_ports ddram_ba[0]]
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set_property SLEW FAST [get_ports ddram_ba[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_ba[0]]
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## ddram:0.ba
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set_property LOC P4 [get_ports ddram_ba[1]]
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set_property SLEW FAST [get_ports ddram_ba[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_ba[1]]
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## ddram:0.ba
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set_property LOC P2 [get_ports ddram_ba[2]]
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set_property SLEW FAST [get_ports ddram_ba[2]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_ba[2]]
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## ddram:0.ras_n
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set_property LOC P3 [get_ports ddram_ras_n]
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set_property SLEW FAST [get_ports ddram_ras_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n]
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## ddram:0.cas_n
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set_property LOC M4 [get_ports ddram_cas_n]
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set_property SLEW FAST [get_ports ddram_cas_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n]
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## ddram:0.we_n
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set_property LOC P5 [get_ports ddram_we_n]
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set_property SLEW FAST [get_ports ddram_we_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_we_n]
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## ddram:0.cs_n
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set_property LOC U8 [get_ports ddram_cs_n]
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set_property SLEW FAST [get_ports ddram_cs_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n]
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## ddram:0.dm
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set_property LOC L1 [get_ports ddram_dm[0]]
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set_property SLEW FAST [get_ports ddram_dm[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dm[0]]
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## ddram:0.dm
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set_property LOC U1 [get_ports ddram_dm[1]]
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set_property SLEW FAST [get_ports ddram_dm[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dm[1]]
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## ddram:0.dq
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set_property LOC K5 [get_ports ddram_dq[0]]
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set_property SLEW FAST [get_ports ddram_dq[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[0]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]]
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## ddram:0.dq
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set_property LOC L3 [get_ports ddram_dq[1]]
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set_property SLEW FAST [get_ports ddram_dq[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[1]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]]
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## ddram:0.dq
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set_property LOC K3 [get_ports ddram_dq[2]]
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set_property SLEW FAST [get_ports ddram_dq[2]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[2]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]]
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## ddram:0.dq
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set_property LOC L6 [get_ports ddram_dq[3]]
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set_property SLEW FAST [get_ports ddram_dq[3]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[3]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]]
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## ddram:0.dq
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set_property LOC M3 [get_ports ddram_dq[4]]
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set_property SLEW FAST [get_ports ddram_dq[4]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[4]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]]
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## ddram:0.dq
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set_property LOC M1 [get_ports ddram_dq[5]]
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set_property SLEW FAST [get_ports ddram_dq[5]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[5]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]]
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## ddram:0.dq
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set_property LOC L4 [get_ports ddram_dq[6]]
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set_property SLEW FAST [get_ports ddram_dq[6]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[6]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]]
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## ddram:0.dq
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set_property LOC M2 [get_ports ddram_dq[7]]
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set_property SLEW FAST [get_ports ddram_dq[7]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[7]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]]
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## ddram:0.dq
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set_property LOC V4 [get_ports ddram_dq[8]]
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set_property SLEW FAST [get_ports ddram_dq[8]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[8]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]]
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## ddram:0.dq
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set_property LOC T5 [get_ports ddram_dq[9]]
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set_property SLEW FAST [get_ports ddram_dq[9]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[9]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]]
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## ddram:0.dq
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set_property LOC U4 [get_ports ddram_dq[10]]
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set_property SLEW FAST [get_ports ddram_dq[10]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[10]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]]
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## ddram:0.dq
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set_property LOC V5 [get_ports ddram_dq[11]]
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set_property SLEW FAST [get_ports ddram_dq[11]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[11]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]]
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## ddram:0.dq
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set_property LOC V1 [get_ports ddram_dq[12]]
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set_property SLEW FAST [get_ports ddram_dq[12]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[12]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]]
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## ddram:0.dq
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set_property LOC T3 [get_ports ddram_dq[13]]
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set_property SLEW FAST [get_ports ddram_dq[13]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[13]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]]
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## ddram:0.dq
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set_property LOC U3 [get_ports ddram_dq[14]]
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set_property SLEW FAST [get_ports ddram_dq[14]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[14]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]]
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## ddram:0.dq
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set_property LOC R3 [get_ports ddram_dq[15]]
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set_property SLEW FAST [get_ports ddram_dq[15]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[15]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]]
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## ddram:0.dqs_p
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set_property LOC N2 [get_ports ddram_dqs_p[0]]
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set_property SLEW FAST [get_ports ddram_dqs_p[0]]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[0]]
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## ddram:0.dqs_p
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set_property LOC U2 [get_ports ddram_dqs_p[1]]
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set_property SLEW FAST [get_ports ddram_dqs_p[1]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[1]]
|
||||
## ddram:0.dqs_n
|
||||
set_property LOC N1 [get_ports ddram_dqs_n[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_n[0]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[0]]
|
||||
## ddram:0.dqs_n
|
||||
set_property LOC V2 [get_ports ddram_dqs_n[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_n[1]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[1]]
|
||||
## ddram:0.clk_p
|
||||
set_property LOC U9 [get_ports ddram_clk_p]
|
||||
set_property SLEW FAST [get_ports ddram_clk_p]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p]
|
||||
## ddram:0.clk_n
|
||||
set_property LOC V9 [get_ports ddram_clk_n]
|
||||
set_property SLEW FAST [get_ports ddram_clk_n]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n]
|
||||
## ddram:0.cke
|
||||
set_property LOC N5 [get_ports ddram_cke]
|
||||
set_property SLEW FAST [get_ports ddram_cke]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_cke]
|
||||
## ddram:0.odt
|
||||
set_property LOC R5 [get_ports ddram_odt]
|
||||
set_property SLEW FAST [get_ports ddram_odt]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_odt]
|
||||
## ddram:0.reset_n
|
||||
set_property LOC K6 [get_ports ddram_reset_n]
|
||||
set_property SLEW FAST [get_ports ddram_reset_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n]
|
||||
|
||||
set_property INTERNAL_VREF 0.675 [get_iobanks 34]
|
||||
|
||||
create_clock -name clk100 -period 10.0 [get_nets clk100]
|
||||
|
||||
set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}]
|
||||
|
||||
set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
|
||||
|
||||
set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]]
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
export XRAY_PART = xc7a35tcsg324-1
|
||||
export XRAY_PART_YAML = $(XRAY_DATABASE_DIR)/$(XRAY_DATABASE)/$(XRAY_PART).yaml
|
||||
YOSYS = $(XRAY_DIR)/third_party/yosys/yosys
|
||||
SOURCES = ../verilog/mem.init ../verilog/mem_1.init ../verilog/top.v ../verilog/VexRiscv_Lite.v
|
||||
PORT ?= /dev/ttyUSB1
|
||||
|
||||
all: top.f2b.bit
|
||||
|
||||
clean:
|
||||
@rm -f *.edif
|
||||
@rm -f *.bit
|
||||
@rm -f *.bin
|
||||
@rm -f *.bits
|
||||
@rm -f *.fasm
|
||||
@rm -f *.frames
|
||||
@rm -f *.log
|
||||
@rm -rf build
|
||||
|
||||
.PHONY: all clean
|
||||
|
||||
$(YOSYS):
|
||||
cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc)
|
||||
|
||||
top.edif: $(YOSYS) synth.ys $(SOURCES)
|
||||
$(YOSYS) -s synth.ys -l yosys.log
|
||||
|
||||
top.bit: $(VIVADO) top.edif top.xdc top.tcl
|
||||
mkdir -p build
|
||||
cd build && $(XRAY_VIVADO) -mode batch -source ../top.tcl -nojournal -tempDir build -log vivado.log -verbose
|
||||
python3 $(XRAY_DIR)/minitests/timing/clean_json5.py < build/iobuf_report.json5 > build/iobuf_report.json
|
||||
cp build/*.bit ./
|
||||
|
||||
top.fasm: top.bit
|
||||
$(XRAY_BIT2FASM) --verbose $< > $@ \
|
||||
|| (rm -f top.fasm && exit 1)
|
||||
|
||||
top.bits: top.bit
|
||||
$(XRAY_BITREAD) -part_file $(XRAY_PART_YAML) -o top.bits -z -y top.bit
|
||||
|
||||
segprint.log: top.bits
|
||||
$(XRAY_SEGPRINT) -z -D -b top.bits > segprint.log
|
||||
|
||||
top.frames: top.fasm
|
||||
$(XRAY_FASM2FRAMES) $< $@
|
||||
|
||||
top.f2b.bit: top.frames
|
||||
$(XRAY_DIR)/build/tools/xc7frames2bit --output_file $@ --part_name $(XRAY_PART) --part_file $(XRAY_PART_YAML) --frm_file $<
|
||||
|
||||
program: top.f2b.bit
|
||||
xc3sprog -c nexys4 top.f2b.bit
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
../verilog/mem.init
|
||||
|
|
@ -0,0 +1 @@
|
|||
../verilog/mem_1.init
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
""" Generates a missing feature/bit report for LiteX design.
|
||||
|
||||
This script is fairly fragile, because it depends on the specific observation
|
||||
that all of the remaining bits appear to either belong to HCLK_IOI or IOI3
|
||||
tiles. A more general version of this script could be created, but that was
|
||||
not the point of this script.
|
||||
|
||||
"""
|
||||
from fasm import parse_fasm_filename
|
||||
|
||||
|
||||
def main():
|
||||
fasm_file = 'top.fasm'
|
||||
fasm_model = list(parse_fasm_filename(fasm_file))
|
||||
|
||||
unknown_bits = {
|
||||
'HCLK_IOI': {},
|
||||
'IOI3': {},
|
||||
}
|
||||
|
||||
total_unknown = 0
|
||||
for l in fasm_model:
|
||||
if l.annotations is None:
|
||||
continue
|
||||
|
||||
annotations = {}
|
||||
for annotation in l.annotations:
|
||||
annotations[annotation.name] = annotation.value
|
||||
|
||||
if 'unknown_bit' not in annotations:
|
||||
continue
|
||||
|
||||
total_unknown += 1
|
||||
|
||||
frame, word, bit = annotations['unknown_bit'].split('_')
|
||||
|
||||
frame = int(frame, 16)
|
||||
word = int(word)
|
||||
bit = int(bit)
|
||||
|
||||
frame_offset = frame % 0x80
|
||||
base_frame = frame - frame_offset
|
||||
|
||||
# All remaining LiteX bits appear to be in this one IO bank, so limit
|
||||
# the tool this this one IO bank.
|
||||
assert base_frame == 0x00401580, hex(frame)
|
||||
|
||||
SIZE = 4
|
||||
INITIAL_OFFSET = -2
|
||||
|
||||
if word == 50:
|
||||
group = 'HCLK_IOI'
|
||||
offset = 45
|
||||
elif word < 50:
|
||||
group = 'IOI3'
|
||||
offset = ((word - INITIAL_OFFSET) // SIZE) * SIZE + INITIAL_OFFSET
|
||||
else:
|
||||
group = 'IOI3'
|
||||
word -= 1
|
||||
offset = ((word - INITIAL_OFFSET) // SIZE) * SIZE + INITIAL_OFFSET
|
||||
offset += 1
|
||||
word += 1
|
||||
|
||||
bit = '{}_{:02d}'.format(
|
||||
frame_offset,
|
||||
(word - offset) * 32 + bit,
|
||||
)
|
||||
|
||||
if bit not in unknown_bits[group]:
|
||||
unknown_bits[group][bit] = 0
|
||||
unknown_bits[group][bit] += 1
|
||||
|
||||
print('Total unknown bits: {}'.format(total_unknown))
|
||||
for group in unknown_bits:
|
||||
print('Group {} (count = {}):'.format(group, len(unknown_bits[group])))
|
||||
for bit in sorted(unknown_bits[group]):
|
||||
print(' {} (count = {})'.format(bit, unknown_bits[group][bit]))
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
read_verilog ../verilog/top.v
|
||||
read_verilog ../verilog/VexRiscv_Lite.v
|
||||
synth_xilinx -edif top.edif
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
proc write_iobuf_report {filename} {
|
||||
set fp [open $filename w]
|
||||
puts $fp "{ \"tiles\": \["
|
||||
foreach port [get_ports] {
|
||||
set net [get_nets -of $port]
|
||||
if { $net == "" } {
|
||||
continue
|
||||
}
|
||||
|
||||
set cell [get_cells -of $net]
|
||||
set site [get_sites -of $cell]
|
||||
set tile [get_tiles -of $site]
|
||||
|
||||
puts $fp "{"
|
||||
puts $fp "\"port\": \"$port\","
|
||||
puts $fp "\"pad_wire\": \"$net\","
|
||||
puts $fp "\"cell\": \"$cell\","
|
||||
puts $fp "\"site\": \"$site\","
|
||||
puts $fp "\"tile\": \"$tile\","
|
||||
puts $fp "\"type\": \"[get_property REF_NAME $cell]\","
|
||||
puts $fp "\"IOSTANDARD\": \"\\\"[get_property IOSTANDARD $cell]\\\"\","
|
||||
puts $fp "\"PULLTYPE\": \"\\\"[get_property PULLTYPE $cell]\\\"\","
|
||||
puts $fp "\"DRIVE\": \"[get_property DRIVE $cell]\","
|
||||
puts $fp "\"SLEW\": \"\\\"[get_property SLEW $cell]\\\"\","
|
||||
puts $fp "},"
|
||||
}
|
||||
puts $fp "\]}"
|
||||
close $fp
|
||||
}
|
||||
|
||||
create_project -force -name top -part xc7a35ticsg324-1L
|
||||
read_xdc ../top.xdc
|
||||
read_edif ../top.edif
|
||||
link_design -top top -part xc7a35ticsg324-1L
|
||||
report_timing_summary -file top_timing_synth.rpt
|
||||
report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
|
||||
report_utilization -file top_utilization_synth.rpt
|
||||
opt_design
|
||||
place_design
|
||||
report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
|
||||
report_utilization -file top_utilization_place.rpt
|
||||
report_io -file top_io.rpt
|
||||
report_control_sets -verbose -file top_control_sets.rpt
|
||||
report_clock_utilization -file top_clock_utilization.rpt
|
||||
route_design
|
||||
phys_opt_design
|
||||
report_timing_summary -no_header -no_detailed_paths
|
||||
write_checkpoint -force top_route.dcp
|
||||
report_route_status -file top_route_status.rpt
|
||||
report_drc -file top_drc.rpt
|
||||
report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
|
||||
report_power -file top_power.rpt
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
write_bitstream -force top.bit
|
||||
write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
|
||||
|
||||
write_iobuf_report iobuf_report.json5
|
||||
|
||||
|
||||
quit
|
||||
|
|
@ -0,0 +1,230 @@
|
|||
## serial:0.tx
|
||||
set_property LOC D10 [get_ports serial_tx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports serial_tx]
|
||||
## serial:0.rx
|
||||
set_property LOC A9 [get_ports serial_rx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports serial_rx]
|
||||
## clk100:0
|
||||
set_property LOC E3 [get_ports clk100]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports clk100]
|
||||
## cpu_reset:0
|
||||
set_property LOC C2 [get_ports cpu_reset]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
|
||||
## ddram:0.a
|
||||
set_property LOC R2 [get_ports ddram_a[0]]
|
||||
set_property SLEW FAST [get_ports ddram_a[0]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[0]]
|
||||
## ddram:0.a
|
||||
set_property LOC M6 [get_ports ddram_a[1]]
|
||||
set_property SLEW FAST [get_ports ddram_a[1]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[1]]
|
||||
## ddram:0.a
|
||||
set_property LOC N4 [get_ports ddram_a[2]]
|
||||
set_property SLEW FAST [get_ports ddram_a[2]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[2]]
|
||||
## ddram:0.a
|
||||
set_property LOC T1 [get_ports ddram_a[3]]
|
||||
set_property SLEW FAST [get_ports ddram_a[3]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[3]]
|
||||
## ddram:0.a
|
||||
set_property LOC N6 [get_ports ddram_a[4]]
|
||||
set_property SLEW FAST [get_ports ddram_a[4]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[4]]
|
||||
## ddram:0.a
|
||||
set_property LOC R7 [get_ports ddram_a[5]]
|
||||
set_property SLEW FAST [get_ports ddram_a[5]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[5]]
|
||||
## ddram:0.a
|
||||
set_property LOC V6 [get_ports ddram_a[6]]
|
||||
set_property SLEW FAST [get_ports ddram_a[6]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[6]]
|
||||
## ddram:0.a
|
||||
set_property LOC U7 [get_ports ddram_a[7]]
|
||||
set_property SLEW FAST [get_ports ddram_a[7]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[7]]
|
||||
## ddram:0.a
|
||||
set_property LOC R8 [get_ports ddram_a[8]]
|
||||
set_property SLEW FAST [get_ports ddram_a[8]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[8]]
|
||||
## ddram:0.a
|
||||
set_property LOC V7 [get_ports ddram_a[9]]
|
||||
set_property SLEW FAST [get_ports ddram_a[9]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[9]]
|
||||
## ddram:0.a
|
||||
set_property LOC R6 [get_ports ddram_a[10]]
|
||||
set_property SLEW FAST [get_ports ddram_a[10]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[10]]
|
||||
## ddram:0.a
|
||||
set_property LOC U6 [get_ports ddram_a[11]]
|
||||
set_property SLEW FAST [get_ports ddram_a[11]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[11]]
|
||||
## ddram:0.a
|
||||
set_property LOC T6 [get_ports ddram_a[12]]
|
||||
set_property SLEW FAST [get_ports ddram_a[12]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[12]]
|
||||
## ddram:0.a
|
||||
set_property LOC T8 [get_ports ddram_a[13]]
|
||||
set_property SLEW FAST [get_ports ddram_a[13]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[13]]
|
||||
## ddram:0.ba
|
||||
set_property LOC R1 [get_ports ddram_ba[0]]
|
||||
set_property SLEW FAST [get_ports ddram_ba[0]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[0]]
|
||||
## ddram:0.ba
|
||||
set_property LOC P4 [get_ports ddram_ba[1]]
|
||||
set_property SLEW FAST [get_ports ddram_ba[1]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[1]]
|
||||
## ddram:0.ba
|
||||
set_property LOC P2 [get_ports ddram_ba[2]]
|
||||
set_property SLEW FAST [get_ports ddram_ba[2]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[2]]
|
||||
## ddram:0.ras_n
|
||||
set_property LOC P3 [get_ports ddram_ras_n]
|
||||
set_property SLEW FAST [get_ports ddram_ras_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n]
|
||||
## ddram:0.cas_n
|
||||
set_property LOC M4 [get_ports ddram_cas_n]
|
||||
set_property SLEW FAST [get_ports ddram_cas_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n]
|
||||
## ddram:0.we_n
|
||||
set_property LOC P5 [get_ports ddram_we_n]
|
||||
set_property SLEW FAST [get_ports ddram_we_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_we_n]
|
||||
## ddram:0.cs_n
|
||||
set_property LOC U8 [get_ports ddram_cs_n]
|
||||
set_property SLEW FAST [get_ports ddram_cs_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n]
|
||||
## ddram:0.dm
|
||||
set_property LOC L1 [get_ports ddram_dm[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dm[0]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dm[0]]
|
||||
## ddram:0.dm
|
||||
set_property LOC U1 [get_ports ddram_dm[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dm[1]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dm[1]]
|
||||
## ddram:0.dq
|
||||
set_property LOC K5 [get_ports ddram_dq[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[0]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[0]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]]
|
||||
## ddram:0.dq
|
||||
set_property LOC L3 [get_ports ddram_dq[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[1]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[1]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]]
|
||||
## ddram:0.dq
|
||||
set_property LOC K3 [get_ports ddram_dq[2]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[2]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[2]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]]
|
||||
## ddram:0.dq
|
||||
set_property LOC L6 [get_ports ddram_dq[3]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[3]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[3]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]]
|
||||
## ddram:0.dq
|
||||
set_property LOC M3 [get_ports ddram_dq[4]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[4]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[4]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]]
|
||||
## ddram:0.dq
|
||||
set_property LOC M1 [get_ports ddram_dq[5]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[5]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[5]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]]
|
||||
## ddram:0.dq
|
||||
set_property LOC L4 [get_ports ddram_dq[6]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[6]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[6]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]]
|
||||
## ddram:0.dq
|
||||
set_property LOC M2 [get_ports ddram_dq[7]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[7]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[7]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]]
|
||||
## ddram:0.dq
|
||||
set_property LOC V4 [get_ports ddram_dq[8]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[8]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[8]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]]
|
||||
## ddram:0.dq
|
||||
set_property LOC T5 [get_ports ddram_dq[9]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[9]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[9]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]]
|
||||
## ddram:0.dq
|
||||
set_property LOC U4 [get_ports ddram_dq[10]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[10]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[10]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]]
|
||||
## ddram:0.dq
|
||||
set_property LOC V5 [get_ports ddram_dq[11]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[11]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[11]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]]
|
||||
## ddram:0.dq
|
||||
set_property LOC V1 [get_ports ddram_dq[12]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[12]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[12]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]]
|
||||
## ddram:0.dq
|
||||
set_property LOC T3 [get_ports ddram_dq[13]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[13]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[13]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]]
|
||||
## ddram:0.dq
|
||||
set_property LOC U3 [get_ports ddram_dq[14]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[14]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[14]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]]
|
||||
## ddram:0.dq
|
||||
set_property LOC R3 [get_ports ddram_dq[15]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[15]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[15]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]]
|
||||
## ddram:0.dqs_p
|
||||
set_property LOC N2 [get_ports ddram_dqs_p[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_p[0]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[0]]
|
||||
## ddram:0.dqs_p
|
||||
set_property LOC U2 [get_ports ddram_dqs_p[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_p[1]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[1]]
|
||||
## ddram:0.dqs_n
|
||||
set_property LOC N1 [get_ports ddram_dqs_n[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_n[0]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[0]]
|
||||
## ddram:0.dqs_n
|
||||
set_property LOC V2 [get_ports ddram_dqs_n[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_n[1]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[1]]
|
||||
## ddram:0.clk_p
|
||||
set_property LOC U9 [get_ports ddram_clk_p]
|
||||
set_property SLEW FAST [get_ports ddram_clk_p]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p]
|
||||
## ddram:0.clk_n
|
||||
set_property LOC V9 [get_ports ddram_clk_n]
|
||||
set_property SLEW FAST [get_ports ddram_clk_n]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n]
|
||||
## ddram:0.cke
|
||||
set_property LOC N5 [get_ports ddram_cke]
|
||||
set_property SLEW FAST [get_ports ddram_cke]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_cke]
|
||||
## ddram:0.odt
|
||||
set_property LOC R5 [get_ports ddram_odt]
|
||||
set_property SLEW FAST [get_ports ddram_odt]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_odt]
|
||||
## ddram:0.reset_n
|
||||
set_property LOC K6 [get_ports ddram_reset_n]
|
||||
set_property SLEW FAST [get_ports ddram_reset_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n]
|
||||
|
||||
set_property INTERNAL_VREF 0.675 [get_iobanks 34]
|
||||
|
||||
create_clock -name clk100 -period 10.0 [get_nets clk100]
|
||||
|
||||
set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}]
|
||||
|
||||
set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
|
||||
|
||||
set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
Loading…
Reference in New Issue