mirror of https://github.com/openXC7/prjxray.git
uart_ddr: improve sdram test script
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi
parent
51158fd0b8
commit
fb5a88a6b8
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@ -2,41 +2,22 @@
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import sys
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import time
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import argparse
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from litex import RemoteClient
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from sdram_init import *
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wb = RemoteClient(debug=False)
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wb.open()
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# # #
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# get identifier
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fpga_id = ""
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for i in range(256):
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c = chr(wb.read(wb.bases.identifier_mem + 4 * i) & 0xff)
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fpga_id += c
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if c == "\0":
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break
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print(fpga_id)
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# software control
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wb.regs.sdram_dfii_control.write(0)
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# sdram initialization
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for i, (comment, a, ba, cmd, delay) in enumerate(init_sequence):
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print(comment)
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wb.regs.sdram_dfii_pi0_address.write(a)
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wb.regs.sdram_dfii_pi0_baddress.write(ba)
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if i < 2:
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wb.regs.sdram_dfii_control.write(cmd)
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else:
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wb.regs.sdram_dfii_pi0_command.write(cmd)
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wb.regs.sdram_dfii_pi0_command_issue.write(1)
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# hardware control
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wb.regs.sdram_dfii_control.write(dfii_control_sel)
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def identify_fpga(wb):
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""" Gets the FPGA identifier and prints it on terminal."""
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fpga_id = ""
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for i in range(256):
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c = chr(wb.read(wb.bases.identifier_mem + 4 * i) & 0xff)
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fpga_id += c
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if c == "\0":
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break
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print(fpga_id)
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def seed_to_data(seed, random=True):
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@ -46,12 +27,12 @@ def seed_to_data(seed, random=True):
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return seed
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def write_pattern(length):
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def write_pattern(wb, length):
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for i in range(length):
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wb.write(wb.mems.main_ram.base + 4 * i, seed_to_data(i))
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def check_pattern(length, debug=False):
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def check_pattern(wb, length, debug=False):
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errors = 0
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for i in range(length):
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error = 0
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@ -72,32 +53,176 @@ def check_pattern(length, debug=False):
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return errors
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# find working bitslips and delays
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nbitslips = 8
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ndelays = 32
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nmodules = 2
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nwords = 16
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def find_bitslips_delays(wb):
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""" Finds bitslip and delay values that can be used with the implemented DDR design."""
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nbitslips = 8
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ndelays = 32
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nmodules = 2
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nwords = 16
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for bitslip in range(nbitslips):
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print("bitslip {:d}: |".format(bitslip), end="")
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for delay in range(ndelays):
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for module in range(nmodules):
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wb.regs.ddrphy_dly_sel.write(1 << module)
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wb.regs.ddrphy_rdly_dq_rst.write(1)
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wb.regs.ddrphy_rdly_dq_bitslip_rst.write(1)
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for i in range(bitslip):
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wb.regs.ddrphy_rdly_dq_bitslip.write(1)
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for i in range(delay):
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wb.regs.ddrphy_rdly_dq_inc.write(1)
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write_pattern(nwords)
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errors = check_pattern(nwords)
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if errors:
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print("..|", end="")
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final_bitslip = None
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final_delay = None
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for bitslip in range(nbitslips):
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print("bitslip {:d}: |".format(bitslip), end="")
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for delay in range(ndelays):
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for module in range(nmodules):
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wb.regs.ddrphy_dly_sel.write(1 << module)
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wb.regs.ddrphy_rdly_dq_rst.write(1)
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wb.regs.ddrphy_rdly_dq_bitslip_rst.write(1)
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for i in range(bitslip):
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wb.regs.ddrphy_rdly_dq_bitslip.write(1)
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for i in range(delay):
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wb.regs.ddrphy_rdly_dq_inc.write(1)
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write_pattern(wb, nwords)
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errors = check_pattern(wb, nwords)
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if errors:
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print("..|", end="")
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else:
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print("{:02d}|".format(delay), end="")
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final_bitslip = bitslip if final_bitslip is None else final_bitslip
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final_delay = delay if final_delay is None else final_delay
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sys.stdout.flush()
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print("")
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assert final_bitslip is not None and final_delay is not None, "bitslip/delay values not found"
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return final_bitslip, final_delay
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def set_bitslip_delay(wb, bitslip, delay):
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""" Sets bitslip and delay values."""
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nmodules = 2
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for module in range(nmodules):
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wb.regs.ddrphy_dly_sel.write(1 << module)
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wb.regs.ddrphy_rdly_dq_rst.write(1)
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wb.regs.ddrphy_rdly_dq_bitslip_rst.write(1)
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for i in range(bitslip):
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wb.regs.ddrphy_rdly_dq_bitslip.write(1)
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for i in range(delay):
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wb.regs.ddrphy_rdly_dq_inc.write(1)
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def read_word_offset(read_only=False):
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word = None
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if not read_only:
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print("\n==================================================\n")
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print(
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"Set a byte long word to write to memory (e.g. 0xdeadbeef): ",
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end="")
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word = int(input(), 16) & 0xffffffff
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print("\n==================================================\n")
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print("Set offset from base memory address: ", end="")
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offset = int(input())
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print("\n==================================================\n")
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print("Set number of words to read or write: ", end="")
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length = int(input())
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return word, offset, length
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def write_user_pattern(wb, offset, length, pattern):
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for i in range(length):
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wb.write(wb.mems.main_ram.base + 4 * (offset + i), pattern)
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def read_user_pattern(wb, offset, length, pattern=None):
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for i in range(length):
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read_value = wb.read(wb.mems.main_ram.base + 4 * (offset + i))
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if pattern is None:
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print("0x{:08x}".format(read_value))
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else:
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print("{:02d}|".format(delay), end="")
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sys.stdout.flush()
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print("")
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if read_value == pattern:
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outcome = "CORRECT"
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else:
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outcome = "INCORRECT"
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# # #
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print(
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"{} --> 0x{:08x}, 0x{:08x}".format(
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outcome, read_value, pattern))
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wb.close()
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def start_command_interface(wb):
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cmd_list = """
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Commands list:
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0 --> Write memory
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1 --> Read memory
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2 --> Write/Read memory
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3 --> Print commands list
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4 --> Exit
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"""
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print(cmd_list)
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while True:
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print("\nWaiting for command: ", end="")
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cmd = int(input())
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if cmd == 0:
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word, offset, length = read_word_offset()
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write_user_pattern(wb, offset, length, word)
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elif cmd == 1:
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word, offset, length = read_word_offset(True)
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read_user_pattern(wb, offset, length)
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elif cmd == 2:
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word, offset, length = read_word_offset()
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write_user_pattern(wb, offset, length, word)
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read_user_pattern(wb, offset, length, word)
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elif cmd == 3:
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print(cmd_list)
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elif cmd == 4:
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break
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else:
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print("Command not recognized, try again...")
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def main():
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parser = argparse.ArgumentParser(
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description="Script to test correct DDR behaviour.")
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parser.add_argument(
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'--bitslip', default=None, help="Defines a bitslip value.")
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parser.add_argument('--delay', default=None, help="Defines a delay value.")
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args = parser.parse_args()
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wb = RemoteClient(debug=False)
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wb.open()
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# software control
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wb.regs.sdram_dfii_control.write(0)
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# sdram initialization
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for i, (comment, a, ba, cmd, delay) in enumerate(init_sequence):
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print(comment)
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wb.regs.sdram_dfii_pi0_address.write(a)
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wb.regs.sdram_dfii_pi0_baddress.write(ba)
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if i < 2:
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wb.regs.sdram_dfii_control.write(cmd)
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else:
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wb.regs.sdram_dfii_pi0_command.write(cmd)
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wb.regs.sdram_dfii_pi0_command_issue.write(1)
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# hardware control
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wb.regs.sdram_dfii_control.write(dfii_control_sel)
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if args.bitslip is None or args.delay is None:
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bitslip, delay = find_bitslips_delays(wb)
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else:
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bitslip = int(args.bitslip)
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delay = int(args.delay)
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set_bitslip_delay(wb, bitslip, delay)
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start_command_interface(wb)
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wb.close()
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if __name__ == "__main__":
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main()
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