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uart_ddr: checking out litex at specific commits 

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi 2020-02-03 17:17:35 +01:00
parent 8736d80af3
commit 8a7e7664f8
2 changed files with 12 additions and 2 deletions
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minitests/litex/uart_ddr/arty/README.md
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# LiteX UART DDR minitest
This test aims at providing a minimal DDR design.
The design is tested with a python script that provides memory control signals to the DDR controller
using an UART bridge.
The script performs the calbiration process, therfore it looks for the bitslip as well as the delay values.
### Litex environment
The litex module used is LiteDRAM, which should be checked-out at the correct commit:
| Repo URL | SHA |
| --- | --- |
| <https://github.com/antmicro/litex> | 3350d33 |
| <https://github.com/enjoy-digital/litedram> | d8f3feb |
| <https://github.com/m-labs/migen> | d11565a |
### Implementation
There are two different ways to test this design:

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minitests/litex/uart_ddr/arty/scripts/Makefile
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litex/litex/tools/litex_client.py:
git clone https://github.com/enjoy-digital/litex.git
cd litex && git checkout 3350d33 && cd ../
test_dram: litex/litex/tools/litex_client.py
./test_sdram.py