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Author SHA1 Message Date
R. Timothy Edwards e1528a797c Corrected the parsing for assignment left-hand-side to allow for
whitespace inside the array declaration, as was (correctly) done
for pin connections.  Previously, "assign x[ 0] = 1'b1" would
fail due to "x[" being parsed as a token by itself.  Now, upon
reading an array opening bracket delimiter, the verilog parser
will continue to read tokens until it finds the closing bracket,
as it does for pin connections.
2026-07-06 10:22:02 -04:00
R. Timothy Edwards 2c94087510 Corrected an error in delimiter parsing, which is due to the lack of
any standard array delimiter character in SPICE.  Often brackets are
used, but just as often angle brackets are used instead, and do not
match the bracket syntax of verilog.  The "matchnocase" function
automatically casts common delimiter characters to a single type to
facilitate matching between names using different delimiters.
However, some code in MatchPins() was assuming square brackets and
breaking this allowance, causing pins to be marked mismatch in spite
of the handling in "matchnocase".  The code has been corrected to
make the same allowance for different delimiter characters everywhere.
2026-06-28 11:44:42 -04:00
R. Timothy Edwards 3eadc8b0dc Corrected some issues in the SPICE parser where a subcircuit name
was checked using "subcktname" before its initialization.  Added
a check for a subcircuit called inside itself, which causes an
immediate failure (see issue tracker issue #106).  If allowed to
continue, netgen will either crash or produce inscrutable output
that doesn't pinpoint the issue.
2026-06-08 14:11:07 -04:00
R. Timothy Edwards 9630670071 The example cited in the last commit is not completely solved by
the code changes in the last commit.  There is still an issue in
which pins should match between name X on one side and X[Y] on
the other side, if there is no X[Z] where Z != Y, specifically if
one or both cells is a black box, since the equivalence cannot
be determined by net matching.

The pin matching has gotten out of hand and really should be
completely redone. . .
2026-05-21 15:35:57 -04:00
R. Timothy Edwards f29452e550 An example found by Leo Moser showed that netgen makes an incorrect
pin assignment when a verilog input file declares a signal "bundle"
with only one signal in it.  The solution is to detect bundles which
have only one component in them, and remove the bundle delimiters
("{...}") so that the pin connection is treated as a simple signal
or vector.
2026-05-21 14:19:24 -04:00
R. Timothy Edwards 8a2bbe0723 Updated version to go along with PR #105 from user jalcim on github. 2026-04-27 09:50:37 -04:00
jalcim a0c49a026a
fix(netcmp): correct signal handler type for K&R declaration
netcmp.c:55 declares oldinthandler with empty parameter list:
    void (*oldinthandler)() = SIG_DFL;

In K&R / pre-C23, this means 'function with unspecified parameters'.
GCC 14+ infers void(*)(void), which is incompatible with signal(2)'s
expected void(*)(int) handler. The signal(SIGINT, oldinthandler) calls
at lines 8777 and 8784 then fail with -Wincompatible-pointer-types
(now a default error in GCC 14+).

This 1-line fix matches the actual usage as a SIGINT handler with int
signum parameter, and restores tclnetgen.so build on Fedora 41+ /
Debian 13+ / Ubuntu 24.04+ (any system with GCC 14+).

Tested: tclnetgen.so now builds successfully and 'netgen -batch lvs'
mode works again.
2026-04-26 22:06:07 +02:00
R. Timothy Edwards 665203bba1 Corrected genhash() after Mitch Bailey pointed out that the function
was no longer hashing on both values passed to the function, as it
is supposed to.
2026-04-03 08:48:34 -04:00
R. Timothy Edwards 0192558d4b Updated version corresponding to the last commit. 2026-04-02 21:30:01 -04:00
R. Timothy Edwards 21d329b22d Modified the hash algorithm used by netgen after a discussion with
ChatGPT about hash implementations.  Switched from SDBM to FNV-1a,
which should be a better/stronger hash algorithm.  Could do
something more sophisticated, but this change can be done in a few
minutes.
2026-04-02 21:29:04 -04:00
R. Timothy Edwards 37b1a2a07d Cleaned up some errors (most minor, some not so minor) in the
code that were surfaced by Stefan Thiede running clang on Mac
OS.  Function prototype warnings have not been fixed yet, as
that is a more involved fix, although it needs to be done.
2026-02-02 20:53:13 -05:00
R. Timothy Edwards 777f7ef095 Found a counting issue with netcmp output that will overrun the
output string buffer if the size of the copied string is just
the wrong amount, due to the use of strcpy() instead of
strncpy() in at least one place.  Just hacked a solution by
allocating more space for the string, but this should be fixed
properly.  Also:  Discovered that the "zero valued resistor"
routine looks for shorted ports in the wrong place, and if it
finds shorted ports it wrongly decides that the device it's
looking at is a zero-valued resistor whether or not it really
is zero-valued.
2026-01-15 16:39:18 -05:00
R. Timothy Edwards 9b4185fe62 Reverted a change from a long time ago regarding removal of zero
valued resistors connecting two ports.  I do not recall exactly
why I put that in but it appears to cause incorrect behavior.
2025-12-28 14:54:07 -05:00
R. Timothy Edwards ddd95c4fe6 Added a few lines to the setup file parser so that if there is a
missing brace in the file (a common error), then the fact that
there is an unevaluated command when the file has finished being
read will trigger an evaluation of the unfinished code and emit
an error.  Previously, the command and anything after the
unterminated brace would just silently get ignored, which was not
helpful for debugging setup syntax errors.
2025-12-11 12:08:31 -05:00
R. Timothy Edwards c0c9993980 Corrected a major error with the verilog parser. The verilog
parser was not assigning the correct file number for the first
input file, which resulted in the effect that if the first
file read sets definitions for the netlist, then those definitions
are wiped out on the following file read.  There has been a workaround
to read from /dev/null on the first file read so that the file number
is set on all subsequent reads.  This fix avoids the need for the
workaround.
2025-12-08 16:45:27 -05:00
R. Timothy Edwards 8a20b90074 Corrected an issue that can cause a segfault in an incorrect run
setup when a cell has no pins.  Didn't really analyze the error
condition, just caught and handled the condition to avoid the
segfault.
2025-12-08 13:09:50 -05:00
R. Timothy Edwards 3392159243 Added some extra code to the verilog parser. It now handles some
additional syntax for wire bundles specified as a pin connection
on an array of instances, and a few other things.  These are not
exhaustive but are solving an immediate problem.  I will go back
and clean up the code to make it work for more general cases
later.
2025-11-29 11:55:26 -05:00
R. Timothy Edwards 24c6eb4cb9 Updated the version to go along with the merge of pull request 2025-11-24 12:26:57 -05:00
Mitch Bailey 9048191486 Allow processing of cellnames with $.
When loading a file, also print cellname on errors

Signed-off-by: Mitch Bailey <d.mitch.bailey@gmail.com>
2025-11-24 12:26:30 -05:00
R. Timothy Edwards 72d7d55bbe Corrected an issue with the "-noflatten" switch to "lvs", which is
also a problem with the underlying "flatten prohibit" command
option;  in one place, the cell's subcircuits were being prohibited
from being flattened, causing issues including a potential infinite
loop.
2025-11-21 15:52:14 -05:00
R. Timothy Edwards 04163aedcc One hopefully final modification to ensure that Tcl_InitStubs()
uses the Tcl version that the program has been compiled to.  This
should work with both Tcl 8.X and Tcl 9.X.
2025-11-12 11:32:18 -05:00
R. Timothy Edwards f7d35f9cca Accidentally changed a file in the last commit which gets
overwritten by "configure".  Moved the modification to the source
file that doesn't get overwritten.
2025-11-12 09:55:29 -05:00
R. Timothy Edwards 601277e539 Updated the revision number for the last set of changes. 2025-11-12 09:19:52 -05:00
R. Timothy Edwards 73344329f8 Made some updates for Tcl 9 compatibility; also changed the
Makefile to pass EXTRA_CFLAGS for testing with "-std=c99" and
"-std=gnu99".  Made some additional corrections to ensure a
clean compile using -std=gnu99.
2025-11-12 09:17:46 -05:00
R. Timothy Edwards 08485d28a7 Changed CONST and CONST84 everywhere in tclnetgen.c to "const".
The capitalized version of this got removed from the Tcl headers
as some point and is no longer valid.  Added an include of
"strings.h" to base/actel.c, which was missing it (uses
strcasecmp() in the code, and needs the function declaration).
2025-11-11 09:59:14 -05:00
R. Timothy Edwards 2ee286efb4 Corrected the pin permutation check for pin matching; previously,
this was not doing the correct cross-check, instead looking in the
same netlist for the permutable pin and checking its node number,
which is useless since the node number is the same by definition
for permutable pins.  This error would result in occasional false
negative results during pin matching, showing matching where pins
are actually not matched.
2025-11-07 14:06:22 -05:00
R. Timothy Edwards dae6919d4f Updating the version to go along with the merge of pull request 2025-10-23 09:54:36 -04:00
D. Mitch Bailey 017bdc6e48 Changed nested to static variable. Otherwise gets reset with each line.
Signed-off-by: D. Mitch Bailey <d.mitch.bailey@gmail.com>
2025-10-23 08:30:08 +00:00
R. Timothy Edwards b371af9235 Corrected an error that was assumed to have been fixed three years
ago (and may have been, but only under limited circumstances).  Do
to several errors, using "-noflatten" on the command line and using
"flatten prohibit" in a script would not prevent cells from being
flattened;  the "-noflatten" list needed to be used to call "flatten
prohibit", and "flatten prohibit" needed to be fixed to flag the
specified cell instead of the top level cell where it exists.
2025-10-22 10:43:00 -04:00
R. Timothy Edwards b5432d139b Corrected a corner-case where a module with no ports in verilog
was creating an implicit net for the stand-in "(no pins)" port.
2025-10-09 10:36:41 -04:00
R. Timothy Edwards 0e958bd45c Corrected an issue in which black-box entries (such as low-level
subcircuit devices) do not output information about mismatched
pins.  This can end up being treated as a non-error but the
mismatch should be noted in the output regardless.
2025-10-08 10:03:35 -04:00
R. Timothy Edwards b59196fa81 Modified the SPICE file read routine to accept the CDL syntax
"*.GLOBAL" as equivalent to ".GLOBAL".  Corrected the property
matching to handle property combination when no "critical"
property is given.  Critical properties exist when one property
must remain constant and equal for other properties to combine,
such as transistor length.  But, for example, capacitors can
combine area without any restriction based on another property.
Also, corrected the property matching code to allow more than
one property to be additive (example:  capacitor area and
perimeter).  Corrected the equation for adding properties in
parallel combination.
2025-10-02 12:33:28 -04:00
R. Timothy Edwards 6e6e9fb73f Added code to catch and print an error in connectivity between a
port and an internal node which can be missed when pin permutations
are present.  Previously, that could produce a situation where
netgen would report a "port error" but otherwise list all ports
as matching.  Because the permutation handling makes this hard to
detect while generating pin correspondence output, the non-matching
pins are listed separately at the end, and only if no mismatch was
detected during output.
2025-09-09 13:45:29 -04:00
R. Timothy Edwards e84700a607 Added a NULL check at one point in the SPICE read routine that
prevents a segfault under some condition (not fully investigated)
involving .include files.  Appears to resolve the problem without
any unintended consequences.
2025-08-31 16:52:35 -04:00
R. Timothy Edwards 0bee21ccc8 Corrected an issue in which a property error in a subcell would not
be reported at the end if there was a port error.  This is important
because port errors often resolve themselves, but the cell should not
be reported clean if the port errors resolved but it had property
errors.  Also:  Added a method to derive area and/or perimeter
properties from length and width, so that capacitors can be combined
in parallel without regard to which dimension is width and which is
length.  This feature has only been lightly tested.
2025-08-26 17:47:46 -04:00
R. Timothy Edwards c269f1de89 Corrected an unexpected corner-case error in which if a newline in
a spice netlist falls exactly on the last non-null position of the
input buffer after the buffer has been expanded to accept more
input data, then the next line gets read in automatically, and
the newline gets treated as whitespace and not a newline.
2025-08-25 10:31:19 -04:00
R. Timothy Edwards 4443826f9e Corrected a place in netcmp.c where a new instance net connection
is created without setting the cell name or instance name.  That
can cause a crash condition when attempting to locate the instance
from the net record.
2025-08-18 10:37:36 -04:00
R. Timothy Edwards a60dac6124 Modified the primary SPICE token reading routine so that the call
to strdtok() can differentiate between reading verilog and reading
SPICE.  Otherwise, SPICE containing the (dubious) syntax of using
backslashes in names will get treated as a verilog name with
verilog backslash notation, with generally undesirable results.
When called from the SPICE reading routine, backslashes are
treated as-is and not as verilog notation.
2025-05-17 20:29:38 -04:00
R. Timothy Edwards bbe645f0ab Corrected an error in which netgen was trying to reduce an
expression in a property that was not necessarily a parameter,
and if it wasn't, then netgen would crash.  Surfaced by an
example using complicated parameters that netgen was apparently
unable to handle (an issue for another day;  the main goal here
was to avoid a segmentation violation).
2025-03-25 17:00:58 -04:00
Tim Edwards 4f315d33d6 Fixed a corner case found by Sylvain Munaut (see github issue
tracker #96) in which a subcircuit with only one port (in this
case, a pad) but which has properties (in this case, "M") will
fail to set the pointer position ahead of the property because
the loop starts after the first pin, so it has already missed
the position that needs to be saved.  Fixed by initializing
the value to the first pin position before starting the loop.
2025-03-09 11:07:58 -04:00
Tim Edwards 4457248ecd Corrected a long-standing issue with permutation, which turned out
to be caused by failing to have a systematic way of determining
which pin's hash value would be used for the hash value of all the
pins.  Because equivalent cells in the two netlists may have pins in
different order, it was possible that they might end up with
different hashes.  This was solved simply by always taking the
larger hash value of the two pins belonging to the permutable pair.
Now permutation works correctly for arbitrary subcircuits.
(Previously it worked for low-level components like MOSFETs because
the pin order is always the same.)
2025-02-09 21:26:54 -05:00
Tim Edwards 021dfa6e8a Made changes to tkcon.tcl to ensure compatibility with Tcl version 9. 2025-01-04 14:18:21 -05:00
Tim Edwards 1d286f9973 Corrected an issue with generating proxy pins that had previously
forced flattening to be done whenever any pin mismatch occurred,
which undermined the whole proxy pin method.  With the proxy pins
fixed, reinstated the method of avoiding flattening when pin
issues can be trivially corrected.  Also:  Added output to the
pin matching for one mismatch case that was being missed.
2025-01-01 13:27:39 -05:00
Tim Edwards 6d2ef396ef After giving the previous code change some more thought, I
decided that it is beneficial to break symmetries by net name;
it's just that net names should not be used before all symmetries
related to pins have been broken.  So I rewrote the compare
routine to take an argument allowing or disallowing net name
matches, and make one call to break symmetries by pin name
followed by another call to break symmetries by net name.  This
still solves the original problem, but does not allow symmetries
to be broken randomly on internal nets if names have been matched
in both netlists.  Otherwise the output may report nets that
appear to be swapped, making the output confusing.
2024-12-27 16:20:00 -05:00
Tim Edwards 2483b7440f Corrected an error in "ResolveAutomorphsByPin" where the code states
to check that the nodes with matching names are pins, but never does.
This results in an attempt to resolve automorphs by matching pin
names AND net names.  However, net names can match without the nets
matching, as pointed out by Andrey Bondar (private communication).
Fixed simply by adding the specified check that the node being name-
matched is actually a pin.
2024-12-26 21:20:24 -05:00
Tim Edwards 49c0de0433 Corrected an error found by Sylvain Munaut and discussed on
open-source-silicon slack on Nov. 3 in which the simple verilog
expression "assign name1 = name2[a:b]";  this revealed an error
where the parsing of "name2" was being incorrectly run with
GetBusTok() which must be called when the token starts with "[".
This problem existed both for the left-hand-side parsing and
the right-hand-side parsing, and has been fixed for both (where
either side may be a subset of a bus and the other a complete
bus).
2024-11-14 21:28:51 -05:00
Tim Edwards 3b9dca0cf2 Implemented the patch from Sylvain Munaut in github PR#90 (issue
that the position in the code has shifted quite a bit and I
don't really trust that git will do a clean merge.
2024-11-14 20:39:19 -05:00
Tim Edwards 7d910b616c Modified the string matching "matchnocase()" routine to compare
a verilog escaped string against an equivalent non-escaped
string (requires that the escaped string differs from the non-
escaped string by having a "\" at the front and " " at the end.
The space character is always maintained as part of the string).
2024-10-19 17:07:09 -04:00
Tim Edwards b1032f846b Refactored code in netcmp.c involved in printing side-by-side
formatted output to make it much cleaner and easier to read.  This
is in preparation of correcting the circuit1<-->circuit2 asymmetry
in the MatchPins() routine.
2024-10-16 20:38:44 -04:00
Tim Edwards 4c546d1472 Corrected an error that prevents property errors from being
printed in detail if a port error is also found.
2024-10-16 09:44:48 -04:00
Tim Edwards e1aa231db1 Corrected another error discovered by Andrei Bondar in which
the critical property (e.g., L for transistors) is required to
match exactly between devices in order to allow the additive
property (e.g., W for transistors) to be summed.  The critical
property should match if all values are within the slop value,
for floating-point values.  Note:  The implementation is still
not rigorous, as the saved critical value may shift from
device to device;  so comparing, e.g., 1.00 to 1.01 to 1.02 to
1.03, etc., can find that all individual comparisons are within
the slop value even though the slop is exceeded across all values.
2024-10-15 20:52:23 -04:00
Tim Edwards df8fa29b2f Fixed an issue with property matching that was preventing the last-
ditch effort of matching based on combining devices with the same
critical property (e.g., adding gate widths together for transistors
of the same gate length, if the property records remain stubbornly
mismatched to the end).  Thanks to Bondar Andrey Renatovich for
surfacing this issue and providing a reproducible example.
2024-10-14 13:24:35 -04:00
Tim Edwards d14bf70f1c Working to get some MatchPins improvements from Mitch Bailey from
a long time ago into the code.  The improvements collided with
intervening changes to the same routines and would not merge
cleanly, which is why they were never merged.  Step 1:  Show the
net name of a matching net that is missing a pin.  Remove output
of missing pins that is redundant (pin names being output twice).
2024-10-07 11:10:33 -04:00
Tim Edwards 5c21000a8b Made a modification to accommodate the situation where a SPICE
instance is matched to a verilog module definition, and the SPICE
instance is read before the verilog definition, forcing a
placeholder cell to be created.  Netgen will now make the
assumption that the verilog ports are in the same order as the
SPICE instance port order.  At the same time, it will output a
warning message that it is making this not-necessarily-warranted
assumption.  If the number of ports don't match or the placeholder
did not come from a SPICE instance, then the placeholder pins are
left alone.
2024-10-03 14:52:42 -04:00
Tim Edwards 05872ca918 Corrected an apparently long-standing error that is responsible for
some errors failing to list in the output while also being responsible
for a number of non-errors showing up in the output.  This fix may
substantially clean up netgen output.  Also:  Added text to the
output noting that pin matching may be incorrect with respect to
symmetries if the nets have failed to match.
2024-10-02 21:20:27 -04:00
Tim Edwards e821381900 Corrected a rather obscure error in which an otherwise unconnected
port-to-port short (formed by "assign" in verilog or zero-valued
resistors in SPICE) does not get checked when counting nodes
before adding a proxy pin to a subcircuit in that cell, causing
the proxy pin to be assigned the same node number and forming an
unintended connection to the port-to-port connecting net.
2024-09-30 22:11:53 -04:00
Tim Edwards 8022e1370f Added a few lines to rebuild the node cache after removing devices
such a zero-ohm resistors or zero-volt sources during the pre-match
phase, since the list of nodes gets changed by merging nets across
the removed devices.  Otherwise, the node-name cache gets
corrupted and random LVS errors occur.
2024-09-27 10:08:37 -04:00
Tim Edwards 2b88d79adc Corrected a rare case where a NULL value propagates in the flattening
routine and is not caught until it causes a segfault.
2024-08-16 19:48:36 -04:00
Tim Edwards bf4112db07 Corrected two statements that can cause a segfault because a
structure variable is not checked for the condition of being NULL
before attempting to read a component of the structure.  These
conditions imply that something is badly wrong in the netlist but
should not be causing a segfault.
2024-05-16 11:49:56 -04:00
Tim Edwards fcee934580 Corrected the parsing of the "model" command, which was failing to
pass the right cell name to the routine which counts the number of
pins.  Using this in a setup file will prevent netgen from spending
time matching low-level devices.
2024-05-14 15:12:41 -04:00
Tim Edwards 2d427aef3c Corrected the bad placement of #ifdef TCL_NETGEN . . . #endif around
critical parts of the netcmp.c code, causing issues with the non-Tcl
build (not that anyone should be doing a non-Tcl build).
2024-05-09 14:11:26 -04:00
Tim Edwards fd0c8c87ea Corrected another error in which, for device sorting, "M" was set
to 1 before the loop over devices in "run", resulting in "M"
taking the value of the previous property record if the following
record did not have an "M" value, instead of setting it to 1.
2024-04-03 21:05:08 -04:00
Tim Edwards 3d180f778d Corrected an error that had previously been corrected in
PropertyMatch() but not corrected symmetrically between circuit1
and circuit2;  this left the possibility that "M=1" in one
circuit vs. no "M" entry in the other would still pop up as a
property error, depending on which circuit (layout or schematic)
was listed first.
2024-04-03 11:01:58 -04:00
Tim Edwards 035fef5c72 Corrected an issue that prevents "cells list <file>" from reporting
empty cells (this does not solve the problem at hand, but is a part
of it).
2024-03-04 21:26:09 -05:00
Tim Edwards 202ea0431f Also updated configure (in addition to configure.in) with the
change to remove the "m4" dependency.
2024-02-19 12:46:20 -05:00
Tim Edwards 94754dbc4e Removed the requirement for package "m4" that is in the configuration
script.  It is not needed and doesn't exist in many OS distributions.
2024-02-19 12:41:08 -05:00
Tim Edwards bf67d3c275 Having been given an example by Kareem Farid where the order of
verilog netlists makes a difference to the matching (or failure
thereof), I applied the same in-circuit pin matching as previously
applied to mixtures of SPICE and verilog netlists.  This is clearly
a more robust way to handle pin order differences between parent
and child than was implemented previously.
2024-02-18 15:22:40 -05:00
Tim Edwards 62feed812e Corrected an issue that arose due to a change made earlier: A
while back, shorted pins were moved into contiguous positions.
When that method was discovered to cause matching issues, it was
abandoned with a note that doing so might have unintended
consequences because other code might depend on the shorted pins
being contiguous.  Such a case was just found, and corrected.
However, it was also found that shorted pins were still not
completely handled correctly in MatchPins();  a solution was
found that adds such pins to the "permutes" list (which needs to
be done if the shorted pins are to be correctly handled in any
higher level of the hierarchy, if there is one), and the
"permutes" list is then checked by MatchPins() to determine if
pins match because they belong to the same group of shorted
pins.
2024-02-09 21:23:28 -05:00
Tim Edwards d1c2848e4b Corrected another error in which some simple expressions are
incorrectly evaluated;  "(w+l)" for example treats "w+l" as
a single string instead of three tokens.  Corrected the code
to watch for a failure of strtod() when parsing the expression
at the "+" sign (also for "-").
2024-02-06 16:27:32 -05:00
Tim Edwards 6b0bd4d97b Found an error with the property sorting in which float values
were not compared for sorting in the same way they are compared
for property matching.  The "slop" value was treated as absolute,
not a percentage, so for example a slop of 0.01 on a dimension
of microns would cause all dimensions to be treated as round-off
error, and no sorting would occur.
2024-02-06 15:02:50 -05:00
Tim Edwards d69fbc23bb Added code to handle the problem in which a verilog netlist is read
before its component cells, and the component cells are read in as
SPICE netlists.  Then the original verilog cell and its instances
need to have pins reordered to match the subcircuit definition in
the SPICE netlist.  Otherwise, when verilog and SPICE netlists are
mixed, the order in which the files are read is critical, and
failures due to reading out-of-order are very obscure and nearly
impossible to debug.
2024-02-03 21:21:09 -05:00
Tim Edwards c7fa0324d9 Added a piece of code that handles implicit pins in verilog by doing
the following:  (1) Checking that the parent cell is verilog,
(2) only running after the two cells themselves have been compared
and matched, then (3) added the missing pin or pins while reordering
pins on instances (note: this may not work if the verilog netlist is
the first passed to netgen;  that case needs to be checked).
2024-02-02 14:51:10 -05:00
Tim Edwards eb27a18ae3 Corrected two different errors:
(1) When a comment line follows a ".subckt" line, and the comment
    line is empty or all whitespace, then the following line would
    be ignored.  This condition appears to be very specific and
    was solved simply by detecting it and handling it.
(2) Occasionally the "M" parameter of a subcircuit will be recorded
    as type double, and this was not being anticipated by the code
    that checks if "M=1" matches a corresponding entry with no "M"
    parameter.  Simple fix to check the condition where the "M"
    parameter is type double.
2024-01-03 21:21:03 -05:00
Tim Edwards 1817f4dd6a Corrected the LDDL_FLAGS setting for Mac OS, which is to replace
"-flat_namespace -undefined suppress -noprebind" to "-undefined
dynamic_lookup" which is what was done in magic, which has a
similar structure to netgen.
2023-12-03 20:32:05 -05:00
Tim Edwards a7e859fcde Corrected an error in parallel_sort and series_sort that does not
move to the start index before relinking the sorted entries.  That
will cause properties to be lost whenever the start index is greater
than zero.  Not sure why this hasn't been caught previously, or
whether other errors are involved here.
2023-11-20 10:38:41 -05:00
Tim Edwards 6d23844483 Corrected an error in the flattening routine that will cause the
"flatten" command to crash if there are black-box subcircuits in
the netlist.
2023-10-27 10:35:27 -04:00
Tim Edwards cc84364263 Added code to the netgen Tcl startup script to grab the PDK_ROOT
variable used with open_pdks, so that PDK references can be made
independent of the local filesystem.
2023-10-27 09:54:21 -04:00
Tim Edwards 00b906c109 Corrected an error in the previous commit which made primitive
devices from a .prm file into class "subckt" when they should be
class "module" (because they are primitives).  Otherwise, netgen
will crash when attempting to flatten them.
2023-10-27 09:38:14 -04:00
Tim Edwards 25a0e12428 One correction to the last commit, to ensure that subcircuits
which are MOSFETs are output into the .sim file in correct
G-D-S-B order.
2023-10-26 20:50:43 -04:00
Tim Edwards eabb898578 Added support for converting a SPICE file to a SIM file simulatable
with IRSIM including recent changes made to support multiple device
types using the subcircuit "x" component type.  This requires
reading in a .prm file, which incidentally can be used with any
SPICE file to inform netgen of the specific component type of any
model defined as a subcircuit.
2023-10-26 15:08:20 -04:00
Tim Edwards ec0e097fcf Corrected the code from version 258 which was supposed to handle
the removal of zero-valued devices between ports on the top level
(from version 254 they are ignored for levels under the top to
prevent port order from getting scrambled).  An invalid check was
being made to determine if the cells being compared were the top
of the compare queue.  This has been fixed.
2023-10-22 10:36:54 -04:00
Tim Edwards f59c9ebcb7 Corrected an issue where a mismatch in property type (e.g.,
string vs. integer) will cause a segfault.  Not sure if
type promotion is needed at that point because the failing case
was a syntax error that caused a double value to be interpreted
as a string because it could not be cast into a numeric form.
2023-10-03 19:39:01 -04:00
Tim Edwards ce097d5d76 One minor change to the previous commit: The check for shorting
devices between two ports is ignored for top-level cells, because
the scrambled ports won't affect anything in that case, and the
error will be reported as a port error, as it should.
2023-09-04 14:47:23 -04:00
Tim Edwards 619409556c Modified the handling of zero-valued resistors and voltage sources
so that they are *not* removed to make a better match if they are
shorting across two ports.  If removed, then the port lists will
get screwed up.  It is better to let the subcircuits fail matching.
Then, after the mismatched subcircuits are flattened, if the zero-
valued resistor or voltage source no longer connects two ports, it
can be safely removed to make a better match.
2023-09-04 14:40:30 -04:00
Tim Edwards b1374e2bc8 Made two changes to the verilog token parsing in netfile.c in
response to Mitch Bailey's github issue #82:

(1) When skipping comments, skip the contents of "(* ... *)"
    delimiters as well as "/* ... */" delimiters.

(2) When checking for qflow's "\abcd\" names (final space
    replaced with a backslash for SPICE compatibility of
    names), make sure that the last "\" is followed by end-
    of-string.  Otherwise names like "\a\bcd " will fail to
    parse correctly.
2023-09-04 10:50:59 -04:00
Tim Edwards cff954f36a Removed a block of ill-considered code that moves pins together
when they are shorted, because doing so is scrambling the pin
order of cells with respect to the instance calls to the cell.
Not sure if there is any code that relies on shorted pins being
adjacent, though.
2023-09-01 16:04:41 -04:00
Tim Edwards c27d933adc Modified some of the verilog read-in code to avoid a segmentation
fault that would happen if the verilog had illegal syntax of a
misspelled net name (although normally netgen is expected not to
have to check the verilog for syntax, and there are probably many
such cases of netgen failing to handle incorrect verilog and then
crashing as a result).
2023-09-01 09:04:44 -04:00
Tim Edwards 615c55cbe2 Updated the config.guess and config.sub files; the newer ones
support, among other things, RISC-V.
2023-08-27 11:53:16 -04:00
Tim Edwards 87d8759a69 Corrected part of the MatchPins() routine so that the JSON output
tracks the output printed to stdout when matching pins.  One section
of this subroutine used the wrong pointers when writing to the Tcl
list (for eventual JSON output) which was the fundamental error.
Beyond that, the "debug" case (if used) would fail to run some of
the matching code, and the "no matching pin" case needed to be
handled for the Tcl list output.  Now the terminal output, terminal
debug output, and Tcl list output should all be in agreement on the
pin lists.
2023-07-11 15:40:00 -04:00
Tim Edwards 1efa054ac1 Corrected an issue with shorted ports. When shorted ports are
connected only to ports and not to any devices, then they do not
show up in NodeClasses() and so pass through most of the checks
in MatchPins().  A separate correspondence check is needed to make
sure that the same shorted ports appear in both netlists.
2023-06-12 17:16:49 -04:00
Tim Edwards 609d1de250 Corrected a problem in the flattening routine, which was a missing
method for flattening a subcircuit with property M != 1.
2023-04-14 20:09:36 -04:00
Tim Edwards 47c3b34612 Corrected the node merging around zero-volt voltage sources and
zero-ohm resistors so that if one of the nodes being merged is a
port, it is preferred over the other.
2023-04-13 15:41:12 -04:00
Tim Edwards 66317c9848 Corrected an error in order-of-precedence of arithmetic operators,
ensuring that, e.g., in (a)*b+c, (a)*b gets evaluated before b+c.
2023-03-29 19:45:39 -04:00
Tim Edwards eeb3c0e5c6 Added support for simple forms of for() loops in generate blocks.
This is done by treating the loop variable as a temporary parameter
that is valid only inside the loop, and changing the parameter
value on each loop iteration.  The file stream position is used
to iterate the loop with calls to fseek() and ftell(), so that the
input tokenizer continues to work within loops.
2023-03-29 16:17:37 -04:00
Tim Edwards 490f9f7dbc Added a missing check for using a verilog macro definition as an
array delimeter for an instance array in verilog.
2023-03-29 09:54:45 -04:00
Tim Edwards 40cf82c2cb Slightly modified the fix from the last commit to allow an empty
string for the setup file to be the "trivial default" previously
used in case of the setup file not being found.  Put a newline
around the setup file messages so that they stand out from the
rest of the initial output information.
2023-03-07 09:00:39 -05:00
Tim Edwards 1ac2b592fb Changed what was a not-very-well thought out behavior: On being
passed an invalid setup file, the netgen "lvs" script uses a
trivial default setup and issues no error or warning.  Replaced
this behavior with an error message and a hard stop.
2023-03-07 08:53:06 -05:00
Tim Edwards e12883037c Modified code from EquivalenceClasses() that forces the two cells
to have unique class hashes.  This has the problem that it prevents
comparing N-to-1 cells because declaring X->X1 as equivalent breaks
the original name equivalence of X->X.  The new implementation adds
the switch "-unique" to preserve the original behavior.  Otherwise,
the class hashes are made the same as the 2nd cell passed to the
command, and it is the responsibility of the person running LVS to
ensure that this is done in the correct direction.
2023-03-06 09:36:35 -05:00
Tim Edwards 2d63fd63c1 Corrected the wrong order of arguments in an strncpy() command
that was introduced in a recent pull request, as pointed out by
Mitch Bailey in github issue #72.
2023-03-04 10:05:57 -05:00
Tim Edwards e557e61a02 Updated version and fixed a redundant include statement after
merging pull request #71 from Donn.
2023-02-28 09:04:45 -05:00
Donn 67da250615 Patches for Clang 2023-02-28 09:02:41 -05:00
Tim Edwards cd013621a7 Relaxed the prohibition on ((S != 1) && (M != 1)) in device
network parallel/series networks.  Instead, added a global option
with command "property tolerance strict|relaxed" to reinstate the
original (strict) behavior on demand, while relaxing it by default.
This allows certain series/parallel networks to match numerically
even though the schematic netlist may have combined individual
devices.
2023-02-27 15:26:18 -05:00
Tim Edwards 45712a04f1 Removed X11 definitions from the configuration when compiling
with Tcl, since Tk is launched independently through the console
script and nothing inside of netgen itself involves graphics.
This prevents netgenexec from linking to Tk and X11 libraries.
2023-02-24 10:42:59 -05:00
Tim Edwards 28a2950439 Modified netgen output to not print information about combining
individual components in parallel and series as it reduces the
networks.  This information is available in total in the cell
summary.
2022-12-19 14:37:11 -05:00
Tim Edwards 013fff9f37 (1) Fixed the series sorting, which needed to be modified to match
the parallel sorting routine.  This fixes occasional property
errors with series-connected devices such as resistors.  (2) Added
a method to associate properties with specific pins when pins are
permutable.  This allows netgen to properly check a value like
source/drain area when the definition of source and drain has
changed due to permutation of the device.  (3) Added a "property"
command extension "associate" to associate a property with a pin,
for use with the method described in (2).
2022-12-15 21:34:56 -05:00
Tim Edwards 2292ab813b Corrected a badly implemented routine that can cause very long
run-times on large projects where a lot of cells need to be
deleted.
2022-11-16 12:37:05 -05:00
Tim Edwards 7e8508db53 Additional correction to the property match subroutine to better
check instances with permutable pins when checking parallelized
instances with disconnected pins vs. mutually connected pins.
2022-11-04 20:40:37 -04:00
Tim Edwards c9f7b24e0f Found an error in property matching causing weird errors in the
LVS result.  The property matching was failing to match (M=1) to
(M!=1) if M was not registered as a property name (which it often
isn't).  This would allow devices with different numbers of
instances in parallel to be put in the same matching group,
which then could later identify as a mismatch if the instances
were checked in a different order.
2022-11-04 12:07:21 -04:00
Tim Edwards 95605ebbd4 Prevented checks from automatically treating two empty cells as
black boxes.  The check was supposed to check that both empty
cells really are black box entries.
2022-11-02 09:48:39 -04:00
Tim Edwards 98e6a4bd8f Implemented the change from pull request #65 from Mitch Bailey
(slightly altered to put the inexpensive flag checks before the
more expensive string match).
2022-11-01 13:21:35 -04:00
Tim Edwards c73d9ec4ff Updated version to go along with pull request #67 from Mitch
Bailey.
2022-11-01 11:44:36 -04:00
D. Mitch Bailey a5375177c5 parameterized string length and increased to 256
Rebasing over latest commit.
2022-11-01 11:43:43 -04:00
Tim Edwards 27b095754e Fixed an error that prints bogus property mismatch errors when
netgen is supposed to be checking properties for symmetry sorting,
but not reporting anything.  This causes mysterious property
mismatch errors that don't actually exist to show up in the
output.
2022-10-31 17:32:15 -04:00
Tim Edwards db457c562b Corrected a problem that is very similar to the last issue, which
is that when the "class ignore" command is used, then ports of a
parent cell need to be checked for being disconnected if they
connect only to ports of an ignored/deleted child cell.
2022-10-29 11:43:01 -04:00
Tim Edwards 06386bee1b Corrected an issue with "flatten": If a cell has disconnected ports,
then flattening instances of that cell can cause a port of the parent
cell connected to the disconnected port of the child cell to itself
become disconnected.  If the parent port is not changed to show the
disconnected state, then pin mismatch can occur if the netlist being
matched didn't have the same flattened subcell.  This condition is
now detected and handled correctly.
2022-10-25 20:14:44 -04:00
Tim Edwards 7cd8d82964 Fix for an error causing a segfault. This does not fix the
underlying issue (which needs to be investigated), but it does
prevent netgen from crashing when it encounters it (netgen will
generate an erro message instead).
2022-10-24 21:45:14 -04:00
Tim Edwards 3aeea9d164 Re-applied the modifications of revisions 231 and 232, and updated
the version to revision 234.
2022-09-30 11:47:36 -04:00
Tim Edwards 12e1ff295f Revert "Part 2 of folding in Mitch Bailey's code. This part is a"
This reverts commit 4fa4d046c8.

Reverting back to before the major change to MatchPins(), which is
breaking existing LVS scripts.
2022-09-30 11:36:09 -04:00
Tim Edwards 2f9e898ec6 Version updated along with the merge of pull request #62 from
Mitch Bailey.
2022-09-23 16:04:49 -04:00
D. Mitch Bailey 9663579dd0 Restore matching circuits if one is empty (but only if pins match). 2022-09-21 08:05:39 -07:00
Tim Edwards f02e2b1ee0 Handled backslash-escapes (convert "\" to "\\") when writing pins
to the JSON format file (since JSON does not allow single backslash
characters.  Previously nets had been handled correctly, but not
pins.  Resolves github issue tracker Issue #60 from Proppy.
2022-09-17 14:33:27 -04:00
Tim Edwards cc5f6d929f Added a missing block of code from Mitch Bailey's version that
fails to handle a topology match with a pin mismatch situation.
2022-09-16 13:55:23 -04:00
Tim Edwards 4fa4d046c8 Part 2 of folding in Mitch Bailey's code. This part is a
significant overhaul of the MatchPins() code, and better handles
issues with pins disconnected from nets and removes cases in
which proxy pins are incorrectly generated.
2022-09-15 10:50:52 -04:00
Tim Edwards 9297090dc1 Start of merging Mitch Bailey's code changes from github pull
request #59 ("Pin match").  Because the pull request has rather
sweeping modifications, I am doing this in two steps.  The change
that most breaks with existing comparison methods is in the
PinMatch() routine in netcmp.c, where the method of generating
proxy pins has been removed.  There are specific cases for which
the proxy pin method exists, although these were coping with
issues arising from extraction in magic which have been dealt
with to some extend.  Possibly the proxy pin method is no longer
needed.  So the PinMatch() changes will be done in a second
commit where it's easier to revert or modify the changes without
affecting the modifications from this commit.
2022-09-13 10:55:00 -04:00
Tim Edwards 79e193e0c9 Modified behavior for the "-noflatten" option on LVS: Added a
command option "flatten prohibit" (or "flatten deny") to prevent
a subcell from being flattened at any time during the compare
process.  Previously, the "-noflatten" option for the "lvs"
script had been used to prevent flattening during initial
pre-match, but if the circuit passed the prematch phase and
subcells were mismatched, they would be flattened regardless of
whether or not they were listed by the "-noflatten" option.  This
also codifies a way to prevent subcells from being flattened in
the setup file rather than in the "lvs" command line.  Also:
Found and fixed a bug that prevents the use of "-noflatten=" with
a cell name or list of cell names instead of a filename.
2022-09-12 11:26:21 -04:00
Tim Edwards 2056b37c95 Yesterday's commit surfaced two errors in series; this fixes the
second one of them, which is a failure to change CurrentTail when
an extra (implicit) pin was added to the last component in the
current cell, resulting in the failure of Node() to add the new
no-connect node, which instead overwrites the pin just created.
2022-06-27 20:35:30 -04:00
Tim Edwards 7550ef9258 Corrected an error in reworking verilog instances to add pins that
were implicit in the first instances but made explicit in a later
one.  If more than one such implicit pin was handled for the same
cell, then the pin count would become wrong and rather unpredictable
behavior results.
2022-06-26 22:16:03 -04:00
Tim Edwards a795981eff Corrected a prematch issue that will flatten a cell on one side
even when the opposing netlist has a black-box entry for the same
cell.  The black-box entry can't be flattened, so this just
results in the cell mysteriously disappearing from one side.
2022-06-26 14:57:25 -04:00
Tim Edwards 1b6e4e2b36 Corrected an error in the last commit which can cause the pin
enumeration in MatchPins() to overflow the cover() array and
cause a segmentation fault.
2022-06-14 11:36:30 -04:00
Tim Edwards edbe5d6e86 Made minor changes to MatchPins() to handle multiple pins connected
to a single net (as can be done with assignments in verilog or with
zero-voltage sources or zero-value resistors in SPICE).  Corrected
an error in the SPICE netlist reader that prevented the proper use
of zero-voltage sources as net splitters.
2022-06-12 17:25:37 -04:00
Tim Edwards f8ed4e42e2 Corrected the parsing of verilog netlists to use the right
delimiter set when parsing pin names (the correct delimiter set
was used in one place but not in another).  Extended the pin
matching to include the minor hack of ignoring the backslash
before backslash-escaped verilog names when there is otherwise
no exact match, since many tools convert verilog to SPICE by
removing the backslash and trailing space.  This avoids pin
mismatches in a known set of use cases.
2022-06-08 11:53:47 -04:00
Tim Edwards 89ef83c597 Corrected an error in the verilog parser that incorrectly handles
the syntax "assign a = b" when both a and b are vectors (but no
vector delimiters appear in the assignment).
2022-04-15 14:13:11 -04:00
Tim Edwards 4e96c84ec6 Extended the method created in the last commit so that it properly
handles both operator order of precedence and parenthetical groups
including nested groups.
2022-04-15 12:19:48 -04:00
Tim Edwards 592c16706e Extended the verilog parsing to parse definitions such that nested
definitions are handled correctly.  Also:  Added code to evaluate
simple expressions for array bounds.  Previously the parser could
handle a value followed by "+" or "-" and a constant.  Now it can
handle all basic arithmetic.
2022-04-14 22:33:58 -04:00
Tim Edwards bfb01e032f Implemented another change discussed in netgen github issue #47
by Anton Blanchard, which prevents the double-loop in the
PropertyOptimize() routine from continuing the outer loop if
all devices in the run have already been merged.
2022-01-16 14:47:52 -05:00
Tim Edwards d0ec17e442 Implemented a change to the way that netgen generates the subcircuit
summary, so that the summary lists the total number of devices as well
as the number of devices after parallel optimization, in the form
"device_name (M->N)", where "M" is the total number of devices, and
"N" is the number of devices after parallel combination.  This makes
the output somewhat more meaningful to the end user.  Implementation
as discussed in github issue #47.
2022-01-16 14:16:30 -05:00
Tim Edwards 6195745b45 Modified the parallel combination code so that properties of
parallel devices are prepended rather than appended, which avoids
having to search for the end of what may be a rapidly increasing
linked list of properties.  This reduces the amount of time spent
in the parallel combination code.  Thanks to Anton Blanchard for
pointing out this inefficiency.
2022-01-15 12:06:43 -05:00
Tim Edwards 68ec2b2a7c Modified two print statements to change "%s(%d)" to "%s (%d)" as
is my typographic preference.
2021-12-31 13:30:13 -05:00
Tim Edwards ca49a90ed6 Merged changes from github issue #45 from Mitch Bailey. These changes
speed up the time needed to flatten an instance, and add clarity to the
output by specifying the file number for each cell name being modified
during the pre-match stage.
2021-12-31 12:13:11 -05:00
Tim Edwards e07a5b416a Removed lvs_manager.py, which is a derived file and should not have
ended up in the repository, as pointed out by Mitch Bailey in github
issue #44.  Added lvs_manager.py to .gitignore to prevent that from
happening again in the future.
2021-12-30 09:19:44 -05:00
Tim Edwards 8094740048 Corrected a problem that stems from code that was deprecated and
marked as unneeded, so I simply removed the code rather than
debug the issue, which was that buses got the delimeters erased
for checking but never put back again.  Also:  Modified the verilog
reading code so that if an empty set "()" is given for a pin, then
the initial proxy, which is a single net with the name prefix
"_noconnect_", can be promoted to a bus if further processing
reveals it to be a bus and not a single-bit signal.
2021-12-29 14:31:38 -05:00
Tim Edwards a026d37f11 Corrected a place in the verilog read routine where ob->next is
used when ob may be NULL.  Added a check in front for ob == NULL.
Also:  Changed the disconnected node alert so that it does not
mention nodes marked "port_mismatch_error".  These are disconnected
by definition, will show up in the pin list, and printing them as
"disconnected pins" is just confusing to the end user.
2021-12-26 10:31:48 -05:00
Tim Edwards ab614b63f7 Corrected the last commit (again) because FlattenUnmatched()
should not be called after CreateTwoLists().  CreateTwoLists()
was being called in one case only to print the contents of the
cells, so that part was pulled out into a separate routine.
2021-12-19 16:25:32 -05:00
Tim Edwards 83dce151d8 Made a correction to the last commit. The "FlattenUnmatched()"
routine does not have an exact equivalent in PrematchLists() and
needs to be run beforehand.  This fix keeps FlattenUnmatched()
from being run on all cells at the beginning and restricts it
to being run on the contents of individual cells during matching,
after checking if either of the cells is a black-box.  Avoiding
flattening contents of one side when the other is a black-box
(or simply doesn't contain any subcircuits or devices) prevents
unnecessary flattening of cells that will never get compared.
2021-12-17 20:31:41 -05:00
Tim Edwards de18ae85a4 Removed the call to FlattenUnmatched() in CreateCompareQueue().
The FlattenUnmatched() is inefficient compared to just letting
the PrematchLists() routine handle flattening of unmatched
instances.
2021-12-15 11:05:00 -05:00
Tim Edwards 9908349fdd Modified the output of "debug on" mode to print the instance name
for each connection in the dump of incorrect nets.  This is
definitely critical to finding local swapping errors, and needs
to be incorporated into the non-debug mode, preferably as part of
the JSON file dump.  But that's for later.
2021-12-07 16:33:43 -05:00
Tim Edwards 964bb0e91a Added sorting of the output lines for items which match both name and
contents (previously wasn't done), and also added sorting for items with
non-matching names which have only one item in the group for each circuit
(so they must be matching in some sense).  This makes the output a bit
more readable without re-enabling the compute-intensive sorting method
for non-matching entries.
2021-12-07 15:34:45 -05:00
Tim Edwards cfdc60104b Updated version to go along with the merge of pull request #39
from Kamyar Mohajerani, with a few minor edits such as renaming
my_hash to hashcase, as a better counterpoint to "hashnocase".
2021-11-17 12:05:01 -05:00
Kamyar Mohajerani 879711def3 revert removal of superfluous 'extern'
.. for functions based on review comments
2021-11-17 11:53:04 -05:00
Kamyar Mohajerani 5def9e0ffc remove <xlocale.h> 2021-11-16 22:18:59 -05:00
Kamyar Mohajerani b5c70decbd fix wrong 'hash' being linked in + C99 compat
This fixes crash on macos due to wrong hash() being linked in.
It also makes sure that proper function defs are declared and available
(as required by C99) to make compile possible in newer compilers (e.g.
Apple clang) and to some extend prevent similar linkage issues happening
again.
2021-11-16 20:06:15 -05:00
Tim Edwards 20f6d76926 Corrected the "format" command, which failed to return TCL_OK
after executing the command with non-zero options.
2021-11-11 08:42:46 -05:00
Tim Edwards e4a15f12fb Updated version to go along with the merge of pull request #37
from Mitch Bailey.
2021-10-29 18:11:03 -04:00
D. Mitch Bailey c6fb204f0c Cosmetic report changes.
Changed line breaks in log and stdout to better differentiate subcircuits.
Added merged series device counts and differentiated from parallel merged device counts.
Added file number to disconnected net, merged count messages.
Changed black box errors to show file numbers instead of hard coded values.
Final error cell list changed from all on one line to one per line.
Removed redundant display in black box warning.
2021-10-29 18:10:30 -04:00
Tim Edwards c7dfff4bb9 Updated version to go along with the merge of pull request #36 from
Mitch Bailey.
2021-10-28 14:24:47 -04:00
D. Mitch Bailey 12fa080212 When comparing instance counts to determine is flattening makes a better match,
flatten cells that have no instances in common.
Display a screen message to indicate a re-compare afterr flattening.
2021-10-28 01:29:32 -07:00
Tim Edwards 4c4bad08f2 After reverting back to before pull request #33, updated the
version and re-applied the fixes from issue #34.
2021-10-23 14:47:30 -04:00
Tim Edwards 23ff2f00a3 Revert "Remove disconnected ports after flattening."
This reverts commit 6d6da9cf5c.

Reverting back to before pull request #33.
2021-10-23 14:42:37 -04:00
Tim Edwards d09f0dd53b Revert "Flatten unmatched cells that don't contain instances from the other file."
This reverts commit 42b1acc564.

Reverting back to before pull request #33.
2021-10-23 14:42:32 -04:00
Tim Edwards 56d4d581e7 Revert "Minor syntactical editing of pull request #33, and updated version"
This reverts commit 6ceeddf096.

Reverting back to before pull request #33.
2021-10-23 14:42:28 -04:00
Tim Edwards 1bb4866226 Revert "Made a correction to the flattening code, removed a duplicate"
This reverts commit 625e043eff.

Reverting back to before pull request #33.
2021-10-23 14:41:58 -04:00
Tim Edwards 625e043eff Made a correction to the flattening code, removed a duplicate
print statement, and clarified the messages about non-matching
circuits at the end, all of them suggestions made by Mitch
Bailey (see issue #34 on github).
2021-10-15 09:13:02 -04:00
Tim Edwards 6ceeddf096 Minor syntactical editing of pull request #33, and updated version
to go along with the merge of the pull request (from Mitch Bailey).
2021-10-14 11:22:20 -04:00
D. Mitch Bailey 42b1acc564 Flatten unmatched cells that don't contain instances from the other file. 2021-10-13 21:00:49 -07:00
D. Mitch Bailey 6d6da9cf5c Remove disconnected ports after flattening. 2021-10-13 01:15:15 -07:00
Tim Edwards bbcc79fc72 Updated version to go along with merge of pull request #32 from
Harald Pretl.
2021-10-05 09:41:24 -04:00
Harald Pretl 6d5946eaf2 Added MacOS (Big Sur) installation instructions. 2021-10-03 13:58:34 +02:00
Tim Edwards 18dcac73bc Updated version to go along with the merge of pull request #31
from Mitch Bailey.
2021-09-07 22:27:31 -04:00
D. Mitch Bailey 1338e3beb5 Removed debugging statement. 2021-09-07 19:16:33 -07:00
D. Mitch Bailey df1c4c5153 Changed debug print increment from 100 -> 10000. 2021-09-07 10:19:27 -07:00
D. Mitch Bailey a05ede99db Added missing newlines
Print debug message every 100 lines
2021-09-06 18:31:38 -07:00
D. Mitch Bailey 2d6f1f71b5 Reduce and clarify debugging message.
Add missing new line to "Flattening non-matched subcircuits.
2021-09-02 22:29:17 -07:00
Tim Edwards d7355cea95 Updated the vezzal docker image version for CI. 2021-08-29 19:41:14 -04:00
Tim Edwards 32585a572c Corrected the badge link at the top of README.md to point to my
own repository instead of a fork.
2021-08-28 13:14:11 -04:00
Tim Edwards e773739e7d Updated VERSION as a forced change to check continuous integration
on github.
2021-08-06 11:37:29 -04:00
Tim Edwards 583cc3a151 Updated VERSION to go along with the merge of pull request #27 from
Sai Charan.  Subsequent mirror pushes to github should trigger the
continuous integration.
2021-08-06 11:18:56 -04:00
Sai Charan Lanka bdd7d25943 Update main.yml 2021-08-06 11:18:32 -04:00
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Sai Charan Lanka f50093e6c6 Rename README to README.md 2021-08-06 11:18:32 -04:00
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Sai Charan Lanka 7e15a26417 Create main.yml 2021-08-06 11:18:31 -04:00
Tim Edwards 21750da6c4 Corrected the Makefile in the python directory to set the
lvs_manager.py script to be executable, or else "netgen -gui" will
not work.
2021-07-29 10:45:44 -04:00
Tim Edwards a332c23524 Corrected an error in "series_sort" that will overwrite memory
randomly if combining series devices that do not have an "S"
property (which is the typical case).  This will normally result in
a crash.
2021-07-15 16:03:43 -04:00
Tim Edwards 064195ecc9 Reinstated some code that had been commented out that prints pin
information for a non-matching pin in circuit1 and generates a
proxy pin in circuit2---there is some case where this is redundant,
I think, but I need to find the example.
2021-07-11 17:04:50 -04:00
Tim Edwards 88d53fab15 Correction to the verilog parser to recognize modifiers such as
"~", "!", or "-" in front of variable names in a pin list that would
render the module behavioral verilog.
2021-07-11 12:06:16 -04:00
Tim Edwards c287b6cd28 A previous attempt (in revision 193) to make the "lvs" script stop
saying that pins were mismatched when pin matching was never run
accidentally resulted in pin matching not being applied to black-box
entries.  This has been corrected.
2021-07-11 10:58:30 -04:00
Tim Edwards 0a0a6bcf63 Modified the handling of missing pins (again) such that netgen
continues to allow missing pins to match unconnected pins, but
*only* on subcircuits below the top level.  This essentially forces
layouts to separate merged pins with metal resistors, although
there should be an option in magic's ext2spice routine that allows
"equiv" statements, when declaring equivalence of two ports, to be
replaced by a zero volt source or zero ohm ideal resistor.
2021-07-10 13:54:14 -04:00
Tim Edwards 72ef2f2637 Corrected the pin matching so that it runs the same loop on unmatched
pins on non-black-boxed circuits as it does not black-boxed circuits,
but specifically looking for pins that are disconnected on both sides,
since those do not appear in the node list and are not otherwise
handled.  Otherwise, disconnected pins will appear to have disappeared
from the first netlist.
2021-07-10 11:25:07 -04:00
Tim Edwards 287f5963d1 Corrected an error that crept into the netgen.tcl script that causes
the "failed pin matching" error message to appear for cells mismatching
topology (in which case pin matching is never done).
2021-07-08 08:56:52 -04:00
Tim Edwards a984ac1a4d Corrected an error in a recent update that handles the case where
a final parallel or series combination needs to be done but there
are still multiple property records.  The multiplier was being
incorrectly applied twice, causing an automatic mismatch in
parameter values.
2021-07-02 10:51:44 -04:00
Tim Edwards 738c1f7b37 Corrected an error probably introduced into the code with the handling
of multiple devices during flattening, that will skip over a node
record at the end of a subcircuit call being flattened and therefore
remove it from the netlist.
2021-06-25 13:16:42 -04:00
Tim Edwards c3cf6c3765 Made another correction that prevents netgen from truncating the pin
list that it prints in the side-by-side element mismatch comparison
for an element, when there is no node record associated with the pin
connection.  This makes the output clearer.
2021-06-25 12:35:11 -04:00
Tim Edwards 99dcc20c0a Corrected MatchPins so that it returns an error code of 0 when pins are
swapped, so that if pin names are swapped on the top level, netgen will
report this as a final error message.  Otherwise, the mismatch is only
reported back in the pin list where it is not obvious.
2021-06-25 10:27:24 -04:00
Tim Edwards 4bbc496749 Corrected an error in the "run converge" and "run resolve" methods.
The algorithm is to run without exhaustive subdivision until the
last step because this is much faster.  The final iteration must
be run with exhaustive subdivision on, or else it is possible to
have cells with swapped pins matching.  The routines that resolve
automorphisms were setting exhaustive subdivision for the final
iteration.  But simple "run converge" and "run resolve" were not.
2021-06-24 14:53:24 -04:00
Tim Edwards c4f03eabaf Corrected an error not checking for running off the end of a list,
in code from a recent commit.
2021-06-18 21:23:21 -04:00
Tim Edwards 6a555ad6ed Added a missing method from parallel/series matching which is to
add properties across multiple property records in the last matching
step, if there are still multiple properties and the values can be
combined.  Previously, netgen had been assuming that there would only
be one property record left at this point, which is not true.  This
shows up particularly for BSIM fingered devices, since "nf" is
ignored.
2021-06-18 10:44:44 -04:00
Tim Edwards 1c5457e180 Corrected a minor issue that cropped up today in which the search
for file extensions is greedy and picks the first matching extension
starting at the front of the string, such that, e.g., "file.ext.spice"
is interpreted as a ".ext" file and not a ".spice" file.
2021-06-16 15:20:39 -04:00
Tim Edwards 7d246c36a6 Corrected an issue with flattening when the instances to be flattened
run to the end of the list of circuit elements.  Also corrected
another issue caused by the flag to denote multiple no-connect pins,
which can be on an instance pin and so cannot share the data from the
instance record.
2021-06-16 14:32:14 -04:00
Tim Edwards 92dfa74403 Corrected an issue that was caused by introducing a type of parallel
device with one or more no-connect pins.  The flag that indicates a
no-connect pin was checked incorrectly, potentially causing obscure
and misleading property mismatch messages to be generated.
2021-06-14 14:30:10 -04:00
Tim Edwards d53541d1d3 Correction to previous commit (failed to link to last pointer
after processing properties during flattening).
2021-06-12 20:15:55 -04:00
Tim Edwards 57b2d21221 Modified the way flattening is done to account for multiple property
records, which were being ignored.  This really only applies to
parallel subcircuits being flattened.  To flatten correctly requires
that any circuit with N property records must be flattened into the
parent at least N times.  To do:  Must look for M > 1 records in the
properties and flatten (M - 1) additional times.
2021-06-12 17:37:50 -04:00
Tim Edwards dfabdaa367 Modified the JSON output so that missing pins which do not match
unconnected pins in the other netlist are marked as "(no pin)"
rather than "(no matching pin)".  This allows a script parsint the
JSON file (e.g., count_lvs.py from qflow) to distinguish between a
real pin error and one that can be ignored.
2021-06-09 09:34:02 -04:00
Tim Edwards c5c1306f6a Corrected a minor error where the property mismatch check outputs
an error message while doing a non-final iteration, where all
output is supposed to be suppressed.
2021-06-09 09:20:45 -04:00
Tim Edwards 0614461c84 Modified MatchPins so that pin mismatches on nets that are not
connected to anything are once again ignored (the prior commit
to prevent netgen from not reporting swapped pins as an error
overcorrected).
2021-06-08 17:25:17 -04:00
Tim Edwards 6e94886b65 Messed up basic pin comparison between black-box vs. non-black-box
subcircuit situations in the last commit.  This commit fixes it.
2021-06-08 16:52:57 -04:00
Tim Edwards 0556abf3c1 Finally corrected the issue with pins being able to be swapped
without netgen noticing---this behavior got broken by an
exception for "black box" circuits, but failed to check if the
circuit really was marked as a "black box" or not.  Fixing that
revealed another issue with verilog implicit pins.  Both issues
have now been corrected.
2021-06-03 17:42:54 -04:00
Tim Edwards 3356dd784e Made a number of usability corrections to the python GUI for
netgen.  More work will be done later.  Also:  Removed the
derived file lvs_manager.py from the repository, and modified
the Makefile to remove it as part of "make clean".
2021-05-30 20:39:47 -04:00
Tim Edwards 00949970b4 The previous method change for sorting to accommodate capacitors and
other devices that do not have a "critical property" that determines
which properties can add together was flawed and messed up the sorting
of devices like transistors and resistors that do have a critical
property.  Reworked the sorting order so that it makes sense for both
situations.
2021-05-28 21:20:39 -04:00
Tim Edwards c83b6def5b Corrected an issue with swapped arguments to PromoteProperty().
Also corrected a superficial issue with an attempt to print out an
instance name that doesn't exist.  There is an underlying bug here
related to cells that have no pins and/or no contents which has not
been debugged.  The fix just keeps netgen from segfaulting.
2021-05-26 12:46:57 -04:00
Tim Edwards 8fc2c097d2 Added one modification that automatically ignores any cell that has
no pins at all.  This overrides the default behavior of treating
empty cells as "black-box" entries, and avoids attempts to compare
cells like logo artwork.
2021-05-25 12:41:57 -04:00
Tim Edwards 2ac2a3b6f8 Fixed a bad assumption; PropertyOptimize allows devices with
different additive properties (like transistor width) to combine;
this is totally wrong and may have been left over from code written
before the routine was split into simple combinations (add similar
devices) and agressive combinations (e.g., add widths together).
2021-05-24 10:05:10 -04:00
Tim Edwards 759d63cea9 Changed a comment in the code that no longer applies after the last
modification.
2021-05-19 16:42:03 -04:00
Tim Edwards 476da015f0 Added support for expression parameters to be added to a device
class during setup, for the purpose of generating some derived
value that is used for merging and sorting, such as area = l*w.
Note that this likely needs adjusting so that the expression is
evaluated but not replaced for the purpose of sorting, since the
values to the parameter may change after parallel and series
merging.
2021-05-19 16:27:52 -04:00
Tim Edwards 4aa8a72769 Corrected an error found in ResolveAutomorphsByProperty which would
cause inexplicable output in case of a property error by showing a
netlist topography error instead of a property error (but the output
shows that the netlists match, and there is no reporting of any
property errors).  This error was discovered while implementing a
better sorting method for parallel combination.  The improved method
sorts on two properties rather than one, and so should not fall into
the error where, say, devices are sorted on W but have different L
for a device like a capacitor where no "critical" property is
specified (and other similar cases, although that is a common one).
2021-05-19 14:56:38 -04:00
Tim Edwards 47e7367c26 Updated the versio with the last commit. 2021-05-13 15:58:49 -04:00
Tim Edwards 362fb7120b Modified the behavior of the parallel combination of devices with
"similar no connect" pins so that it is not done on top-level
netlists.  This is mainly to deal with the problem where connections
that would normally be pins (but may have, for example, been
connected to a voltage source in a schematic that was deleted because
it was not a netlistable device) are treated as no-connects.
The parallel combination of devices with similar no-connects can then
differ between netlists that differ in describing transistors as
fingered vs. individual devices.  This is an obscure case, but the
output of netgen then becomes not only wrong but difficult to
understand what happened, so it is better to avoid.
2021-05-13 15:50:12 -04:00
Tim Edwards 92e8fed8be Corrected an error in checking merge flags when doing sorting of
parallel and series devices.  This was a fairly major error
undermining the property sorting (the case where the same number
of devices are in parallel in both circuits and need to be sorted
by, e.g., width, prior to checking for matches).
2021-05-03 11:20:44 -04:00
Tim Edwards 01b2484be3 Updated version. 2021-05-01 22:49:59 -04:00
Tim Edwards fe47d84ace Missed a corner case in the series combination code where a device
has been shuffled to the beginning of the cell, which requires
different handling.
2021-05-01 22:48:59 -04:00
Tim Edwards 0a2adeb593 Modified the "flatten" command to allow class "module" to be
flattened.  This is marginally useful---since the "module" class
is a black box, it is essentially the same as using the "ignore"
command.
2021-03-19 13:57:11 -04:00
Tim Edwards 330b34139c Slight modification to print the list of cells being forced to
match for both the filename option and immediate list.
2021-03-19 10:51:42 -04:00
Tim Edwards 62d0352149 Modified the "-noflatten" command option to "lvs" so that it can be
given a filename as a value in addition to being passed a list of
cells directly.
2021-03-19 09:41:42 -04:00
Tim Edwards b1b04b8e87 Corrected a statement related to proxy pins that can cause a
segfault condition.
2021-03-17 16:31:22 -04:00
Tim Edwards 6b9d92de65 Corrected some pointer-to-int and int-to-pointer conversions to
keep the compiler happy.
2021-03-05 20:19:04 -05:00
Tim Edwards d763ad0e60 First and simplest (but most effective) cut at aligning the two
sides of the output when presenting side-by-side results.  This
matches up net or device names within a partition.  Where net or
device names match, the contents are also aligned on either side.
I attempted to also do a "best match" of contents between sides,
but as this involves a lot of analyzing the contents, it is very
computationally expensive, and so the code has been disabled.  It
could be added back in as an option.  There are also various ways
to optimize it for speed.
2021-03-05 17:23:22 -05:00
Tim Edwards fd72e24a86 Corrected an error in the code that handles no-connects as valid
pins for enabling parallel combinations, which could cause a crash.
Added a "-force" option to "equate pins" to allow pins to be matched
even on subcircuits that did not correctly match;  this was done in
conjuction with an extra option to the "lvs" command "-noflatten="
to pass a list of cellname to not be flattened even if they do not
match.  This is generally discouraged, as it prevents netgen from
resolving differences between layout and schematic hierarchy, but it
can be useful for checking that the hierarchy above a certain cell
is correct, given that if a subcell is really unmatched, then its
errors will keep propagating up the top level, making additional
errors hard to diagnose.
2021-03-05 11:32:17 -05:00
Tim Edwards 20077d3d56 Modifed the handling of parallelized no-connects so that the behavior
can be turned on or off from the setup using "property parallel open"
to allow parallelizing devices with no-connect pins vs. "property
parallel connected" to only allow parallelizing of devices with all
pins connected.
2021-03-03 17:31:45 -05:00
Tim Edwards a21ba820e9 Corrected a missing variable in a print statement in the SPICE read
routine that can cause a segfault.
2021-03-02 21:48:48 -05:00
Tim Edwards 792c5e569a Resolved the case mentioned in a prior commit where the case of N
devices in parallel with unconnected pins would be confused with
N devices in parallel with those pins all tied together.  This is
treated as a property error.
2021-03-02 16:49:03 -05:00
Tim Edwards f92192efd4 Corrected an error from yesterday's commit; the test case for
parallel combinations with disconnected nodes works with the error,
but in general it won't.
2021-03-02 10:58:36 -05:00
Tim Edwards 1f50c7ccc5 Updating VERSION with pull request #18 on github. 2021-03-02 10:16:54 -05:00
Ahmed Ghazy 8282460774 Remove netgen.{sh,tcl} and add them to .gitignore 2021-03-02 10:24:17 +02:00
Tim Edwards ea07642172 Removed the symmetry breaking option from the scripted "lvs"
command.
2021-03-01 16:57:49 -05:00
Tim Edwards e9da037001 Removed the code for fast symmetry breaking, as it has been found
to generate incorrect results on occasion.  The method to parallelize
cells with the same no-connect pins should avoid the worst-case
symmetry breaking that was previously plaguing the LVS of large
standard-cell layouts.
2021-03-01 16:55:07 -05:00
Tim Edwards 7ee50a3f8f Modified the parallel combination code to treat cells as equivalently
parallel if the same pins are no-connects.  These were previously not
treated as parallel because each no-connect has a unique node number,
and cells were only considered as parallel if all pins connected to
the same node numbers.  This avoids issues with long-running symmetry
breaking on standard cell designs due to cells like antenna taps or
any cell that is placed without connecting it up.  To do:  This
makes indistinguishable certain cases, e.g., N cells in circuit 1
with pin X open vs. N cells in circuit 2 with pin X all tied together.
This could be caught during property matching.
2021-03-01 16:33:55 -05:00
Tim Edwards c7848c9c02 Corrected an error that (in a rare circumstance) can cause netgen
to go into an infinite loop and fill memory until it crashes, due
to a complete pin mismatch between devices causing one device to
have its pins removed and replaced with proxy pins.
2021-02-24 16:12:19 -05:00
Tim Edwards 402e1f0f25 Found a chokepoint in FlattenInstancesOf that was unnecessary as it
was running through the entire object linked list to find the
predecessor of a record that it had already found.  Solved by simply
keeping track of the predecessor record.
2021-02-16 17:12:00 -05:00
Tim Edwards 19471275df Added handling of control blocks (.CONTROL ... .ENDC) in ngspice-
format files to the SPICE parser, so that netgen can be run
directly on a testbench file and not generate errors due to
statements in the control block.
2021-02-09 09:30:27 -05:00
Tim Edwards e75f5661e2 Added a zero-value current source to the zero-valued devices handled
by the pre-matching method.  The current source is treated like the
others except that it forms an open circuit rather than a short.
2021-02-09 09:12:22 -05:00
Tim Edwards a034fc16d6 Updated VERSION. 2021-01-21 13:41:20 -05:00
Tim Edwards 62fbd422e2 Modified netcmp.c "addproxies" routine to not get confused by cells
with no pins marked with a "(no pins)" placeholder.  Otherwise it
goes into an infinite loop and eats up memory until it crashes.
2021-01-21 13:38:44 -05:00
Tim Edwards d0bae6aff4 Updated VERSION with the merge of pull request #15 from Alessandro de
Laurenzis.
2021-01-17 11:38:11 -05:00
Alessandro De Laurenzis 8a7bb7f2ca
Fix missing prototype for ReadVerilogFile function
Unbreak OpenBSD port for mips64 arch
2021-01-17 10:21:52 +01:00
Tim Edwards 0df6c83df5 Updated VERSION to go along with the merge of pull request #14
from Anton Blanchard.
2021-01-16 12:05:52 -05:00
Anton Blanchard 8996fe03dc Increase OBJHASHSIZE
I have a design that is taking quite a long time for netgen to complete LVS
checking. Profiles show a large chunk of runtime is in the hash functions.

Some of the hashtables are very sparsely populated, but others are
heavily used. One hashtable has chains of over 250. Longer term it would
be worth investigating resizing the hashtables (or perhaps using other
data strutures), but for now I looked at what changing the number of
hash buckets (OBJHASHSIZE) does for performance:

OBJHASHSIZE	time (mm:ss)
997		24:18
10093		 4:42
42073		 3:12
104729		 2:51

I somewhat arbitrarily chose 42073 which gives us a 7.6x improvement in
runtime.
2021-01-15 18:24:34 -07:00
Tim Edwards f3cebd9099 Corrected a potential crash condition while doing series combination. 2021-01-08 09:55:00 -05:00
Tim Edwards 920c6e6928 Corrected a problem causing a segfault during a property record
copy if the property record does not have a model.class record
(should it always?).
2020-12-20 11:55:20 -05:00
Tim Edwards 69780aa048 Added patch from Mitch Bailey which sorts the objects in a verilog
file input so that pins occur first before nodes, as they do in a
SPICE netlist.  Certain parts of the comparison code depend on pins
being first in the netlist, and reordering them when reading input
is easier than rewriting the rest of the code.
2020-12-15 09:57:49 -05:00
Tim Edwards 2a0ebfde93 Updated VERSION with the commit. 2020-12-05 15:46:45 -05:00
Tim Edwards 6e9e6abe98 Removed the netgen.sh and netgen.tcl scripts from the repository,
which are generated by ./configure and should not be in the repo.
2020-12-05 15:46:03 -05:00
Tim Edwards b9769b9f55 Updated version to go along with pull request merge from github. 2020-12-03 20:17:59 -05:00
Tim 'mithro' Ansell 7e42483986 Fix configure script to not clobber CFLAGS.
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
2020-11-29 16:39:28 -08:00
Tim 'mithro' Ansell 97b0d08e4f Rework configure script so exit code works.
The previous script would swallow the exit code of the `./configure`
script and thus it looked like doing a configure always succeeded.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
2020-11-29 16:35:47 -08:00
Tim Edwards d2c356f9e2 Added a "-full" switch to the scripted "lvs" command that switches
to the old symmetry breaking method (see previous commit message).
2020-10-08 09:57:01 -04:00
Tim Edwards 5e99fd5ef9 Found a counterexample which shows that the fast symmetry breaking
introduced in revision 150 can result in an incorrect result
reporting a bad match where the match is actually good (as proven
by running the full symmetry breaking on the same netlist).
Because the fast symmetry breaking is orders of magnitude faster
for large circuits, and because the false positive result appears
to be rare, I have introduced a command "symmetry" to switch
methods between fast and full.  So fast symmetry breaking can be
run unless the result fails on symmetry breaking, in which case
the method can be switched to full to see if the problem is a
false positive or not.  This is not an ideal solution, and some
investigation is needed to determine if there is a way to apply
fast symmetry breaking without encountering a false positive
error.
2020-10-08 09:43:25 -04:00
Tim Edwards 04dd4a64d5 Corrected problems with the port count routine not being specified
with the file number, so that it can get confused between libraries.
Also made a fix to coerce one cell class to be forced to be the
same in both circuits under some circumstances.
2020-10-07 21:32:07 -04:00
Tim Edwards 50b0e9cb65 Found examples where the automated "pin matching" algorithm causes
the top level circuits to be declared matching with no errors even
though the pins do not match.  "proxy pins" are fine for subcells
to detect cases where one subcell has an unused pin and the matching
subcell does not declare it, but that should not be allowed on the
top level, as it cannot be known whether the pin is unused or not.
2020-08-08 13:19:26 -04:00
Tim Edwards 82be18ec4b Corrected a bounds check on sub-arrays inside bundles, that prevents
the bundle from being parsed correctly when any sub-array is only one
bit wide.
2020-08-03 22:57:19 -04:00
Tim Edwards 4ee3a1464b Corrected the left-hand side assignment for "assign" statements and
corrected the error statement so that it refers both to the (corrected)
left-hand side and also the portion of the right-hand side that cannot
be parsed as structural verilog.
2020-08-03 11:49:09 -04:00
Tim Edwards 8e215d3b66 Corrected the PropertyMatch() routine; previously the symmetry
breaking by property was only matching properties between circuits but
not within the same circuit, which is needed for correct symmetry
breaking.  But the PropertyMatch() routine assumed that it is passed
one item from each circuit, leading to a segfault when running the
symmetry breaking within a single circuit.  This has been fixed.
2020-07-31 12:56:20 -04:00
Tim Edwards c45d51e950 Tracked down and fixed problems with implicit pins in verilog (pins
that are not declared in the verilog netlist because they don't
connect to anything, and their presence is not required by verilog
syntax) and the printing of proxy pins created to act as placeholders
for those implicit pins.  Also removed the pinting of the "disconnected
pin" messages for black-box modules (since by definition they have
disconnected pins, because black-box modules have no contents).
2020-07-31 12:22:50 -04:00
Tim Edwards 85eb34c01e Made several corrections to handling of proxy pins when matching
black-box circuits, especially those coming from verilog netlists
where a pin does not need to be declared and is implicitly floating.
This prevents the need to have an explicit black-box entry for any
verilog module that may have an instance that does not declare all
the pin connections.  Also corrected an error which causes mysterious
failures if a verilog netlist is read before a SPICE netlist,
because the former gets hashed case-sensitive and the latter changes
the hashing to case-insensitive.  Modified to force the SPICE
netlist to be treated case-sensitive, which may cause errors, but
is consistent with the reverse order handling, and doesn't cause
unexplained errors.
2020-07-30 22:51:34 -04:00
Tim Edwards 8a24c6c3ca Modified the ResolveAutomorphisms() routine once again, to break
symmetry of all elements in all symmetric partitions, rather than
(as previously done) all elements in each partition, before re-
running iterations to convergence.  This solves the problem of
having a very large number of partitions with a few elements each
taking a long time to run.
2020-07-30 14:48:08 -04:00
Tim Edwards 46cdf48bc4 Updated the version to force the tarball and github mirror. 2020-07-30 08:10:09 -04:00
Tim Edwards 9d542b92b0 Corrected one logical error in netcmp.c from the last commit,
discovered and fixed by Ahmed Ghazy.
2020-07-30 08:06:44 -04:00
Tim Edwards 71ad228d8d Modified the symmetry breaking routine that arbitrarily resolves
automorphisms so that it arbitrarily assigns all pairs from
circuit1 and circuit2 at once rather than assigning one pair at
a time and rerunning to convergence.  I'm not sure of the validity
of this, other than that I have never seen a circuit fail to match
after resolving automorphisms, leading me to believe that the way
the symmetry breaking is done is irrelevant.
2020-07-29 21:13:45 -04:00
Tim Edwards 339a0d5d4e Updated version to force the new tarball and github mirror. 2020-07-29 13:59:24 -04:00
Tim Edwards 9cebb76787 Corrected a problem in ResolveAutomorphsByProperty() that causes
long run-times even when there are no properties to check.  Corrected
a problem with SPICE and verilog netlist reading which arbitrarily
replaces file extensions even when a file extension is given,
resulting in reading the wrong file.
2020-07-29 13:57:08 -04:00
Tim Edwards 251622c8bc Corrected the routines DescendCountQueue and DescendCompareQueue
to include type CLASS_MODULE in the list of types to descend into,
since "module" (black-box) types need to be checked for pin
matching even if they have no contents.  This allows two verilog
netlists to be compared against each other.
2020-07-24 20:50:07 -04:00
Tim Edwards 18739235a9 Extended the code from the last commit to cover cases in which the
definition covers multiple lines;  this also is a general handler
of the backslash-newline continuation line.
2020-07-01 16:00:54 -04:00
Tim Edwards 07c493c796 Corrected the verilog parser's behavior with respect to string
definitions:  Now correctly parses everything from the definition
name to the end of line as the definition value.  Also:  The
search for definitions in the body of the text does not reject
non-alphanumerics "_" and "$" in the definition name, without
which definition names containing those characters will go
unrecongized.  Have not yet extended this to multi-line definition
values.
2020-07-01 14:28:00 -04:00
Tim Edwards cca0e4b3f3 Corrected an error in bundle assignment that failed to make a copy
of the root name of the LHS net, and so would use the last root
name copied, which might have belonged to something entirely
different, or nothing at all.
2020-07-01 13:11:37 -04:00
Tim Edwards fb0e1d10b0 Added back a correction that did not get made in this code base
and so didn't make it into the commit.  Handles implicit pins in
verilog.
2020-06-16 17:16:30 -04:00
Tim Edwards 6f81e1d294 Removed a restriction on the "equate pins" command such that pins
are matched on circuits that have no elements.  This condition
does not necessarily indicate an error, and matching pins has no
adverse affect (while refusing to match them certainly can).
2020-06-16 15:56:59 -04:00
Tim Edwards cec6d89474 Corrected an uninitialized variable error in the verilog reading code
that produces a segfault condition.
2020-06-16 12:52:29 -04:00
Tim Edwards 9bcca3ac21 Corrected the verilog parsing (yet again!) so that it does not
mistakenly flag bus delimiter characters inside backslash-escaped
names when looking for bus delimiters.
2020-06-03 17:00:42 -04:00
Tim Edwards 6ae6a246e9 Some additional changes to better identify behavioral verilog
blocks.
2020-03-27 15:09:56 -04:00
Tim Edwards d985ea340e One more bug fix. . . unitialized variable error. 2020-03-27 12:47:24 -04:00
Tim Edwards 5ea7916ff1 Final (I hope) correction to netgen for handling signal wraparound
for buses applied to instance arrayes.
2020-03-27 12:15:57 -04:00
Tim Edwards cf9dedb2f7 Additional corrections; needed to maintain port width in the
scan structure because it is used in two different places and
would have to run a cost-prohibitive search of the cell's
object list.  Also, was missing recording a bus input/output
signal from an "input" or "output" statement (as opposed to
in-line signals in the I/O list).
2020-03-27 11:31:21 -04:00
Tim Edwards da667c3b17 Corrected handling of wire bundles in the verilog parser. 2020-03-27 08:48:48 -04:00
Tim Edwards 36aa373fb2 Corrected an error in the verilog read to correctly assign signals
to bus pins over an array of instances.  Takes care of the three
situations where the length of the signal bus equals the number of
instances;  where the length of the signal bus is a multiple of
the number of instances;  and where the number of instances is a
multiple of the length of the signal bus.
2020-03-26 11:53:52 -04:00
Tim Edwards 18f230fc46 Changed the default string size for tmpstr in flattenInstancesOf
from 200 to 1024.  Probably this should be dynamically allocated
and expanded as needed, as it is holding names that are of
increasing length as a hierarchy is descended and the instance
prefixes appended to the name.
2020-03-26 09:04:52 -04:00
Tim Edwards 0f5a618353 Corrected some problems with property matching in netcmp.c.
However, I have identified an issue that has not yet been resolved,
which is that there can be automorphisms that are potentially
broken by property matching.  Currently, the automorphisms are
arbitrarily resolved, then properties are matched---and may fail
accordingly.
2020-03-10 21:39:41 -04:00
Tim Edwards 983c654086 Corrected error in property matching that can cause a segfault. 2020-03-05 15:20:46 -05:00
Tim Edwards 515fccc633 Corrected error in printing the name of a file when it is not found
in an "include" statement in either SPICE or verilog.  Modified pin
matching behavior to force cells in both netlists to be marked as
black-box entries if either one is marked as a black-box entry (this
may not be needed, but shouldn't do any harm, either).
2020-03-05 09:41:22 -05:00
Tim Edwards 7d94a7d5f6 Updated VERSION for new tarball. 2020-03-04 21:06:21 -05:00
Tim Edwards 39b3bb4d96 Changed behavior of MatchPins so that disconnected pins that are to
be removed because they do not match pins on the other cell being
compared, are marked with a different number (-2) than the usual
(-1).  CleanupPins then only removes those pins that are marked,
rather than all disconnected pins.
2020-03-04 21:01:43 -05:00
Tim Edwards 44673a04b6 Corrected the verilog parser to handle backslash-escape notation
in instance names, and to ignore bus delimiters inside backslash-
escaped names when determining if a net is a bus or not.
2020-03-04 16:55:53 -05:00
Tim Edwards a34f08b20a Corrected problem in flattening code that would attempt to flatten
a cell that mismatched by having zero instances.  Which fails and
repeats indefinitely.
2020-03-04 15:17:42 -05:00
Tim Edwards 240a276431 Changed behavior of "equate pins" to detect placeholder cells as
a different way of treating "black box" cells.  Even when the
"-blackbox" option is specified, any cell that has no definition
will be treated as a black box.  This allows comparison of a
black-box netlist against a non-black-box netlist, such as a
verilog netlist vs. a SPICE netlist, without forcing the black-box
attribute on the SPICE netlist.  Then, if the SPICE netlist
contains cells without elements such as fill/decap/tap cells,
they can be flattened and removed instead of forcing an error or
requiring the use of "ignore".
2020-03-03 10:50:45 -05:00
Tim Edwards f7037fc9e6 Updated VERSION manually; checking regeneration of tarball. 2020-02-24 17:34:38 -05:00
Tim Edwards 23fb9356f4 Corrected Makefile to use -include instead of include on defs.mak
so that "make distclean" works.
2020-02-24 17:31:06 -05:00
Tim Edwards 027b4ae468 Test update of VERSION. 2020-02-24 16:38:56 -05:00
Tim Edwards 08a442fda2 Removed VERSION from .gitignore, and updated VERSION. 2020-02-24 11:50:38 -05:00
Tim Edwards cc0cc512c0 Modified the Makefile per the patch from Charlene at OpenBSD to
add GR_LIBS to the list of options to CC, as this apparently
prevents problems with older binutils, and should not affect
builds otherwise.
2020-02-17 14:04:40 -05:00
Tim Edwards e9c0596dfe One additional change to allow a single value to the "format" command
to apply to both column widths.
2020-02-10 09:17:45 -05:00
Tim Edwards 9a1e295367 Based on code from John Wood, added command "netgen::format <col1_width>
<col2_width>" to set the output format width, to avoid the fixed column
widths of 41 characters which can truncate long strings in the output
such as deep cell hierarchies.  This command can be placed in the setup
script to widen the output columns to accomodate the result (to-do:
provide an "auto" mode to automatically determine the best width).
2020-02-10 09:11:34 -05:00
Tim Edwards d7272e4ea1 One correction to a variable not pointing to the correct distributed
install location for --with-distdir.
2020-01-28 13:51:23 -05:00
Tim Edwards 7f4b5817e2 Corrected configure.in to correctly use withval for setting the
with-distdir option.
2020-01-28 13:48:24 -05:00
Tim Edwards b5ab38d5d7 Added a distributed install option "--with-distdir=" which replaces
"prefix" with the specified path during install, so that netgen can
be installed in a separate location to be migrated to the final
install location, without appending the entire install path to
DESTDIR.
2020-01-28 10:49:42 -05:00
Tim Edwards bf671937b9 Changed the behavior with respect to backslashes in the JSON so that
they are converted to the double-backslash escape that is the proper
JSON syntax for backslashes, instead of being removed, which changes
the name and can be confusing.
2020-01-13 09:03:36 -05:00
Tim Edwards a16086d2e9 Added handling of backslash characters in instance names in the
JSON output.  Previously, only net names were checked for
backslash characters.
2020-01-13 09:00:48 -05:00
Tim Edwards 0e03f0bf97 Corrected an error that allows a variable to be used uninitialized
in parallel_sort, resulting in a (potentially intermittant)
segfault condition.
2019-11-19 11:45:49 -05:00
Tim Edwards f12d03fcff Corrected the verilog parser for handling parameters and parameters
with increment/decrement syntax at the end.  Also the parser now
handles additional keywords associated with behavioral verilog
(initial, specify) and flags modules with them as black-box entries.
2019-10-08 12:18:13 -04:00
Tim Edwards f04c72b984 Corrected missing case (greater-than or equal instead of greater than)
that affects vectors sliced across instance arrays.  Can cause vector
numbers to be out-of-bounds if an instance is arrayed but each
instance is listed separately.
2019-09-10 10:52:15 -04:00
Tim Edwards d38bd77825 Additional fixes to the verilog parser, including handling the
inline-I/O syntax with "wire" (e.g., "input wire [3:0] test")
and addressed the failure to add buses declared in inline I/O
to the list of known buses.
2019-09-09 13:42:21 -04:00
Tim Edwards ea4083893c A fairly large refactoring of the conditional handling code in the
verilog parser.  The parser should now be able to handle any
conditionals anywhere in the verilog code.  Also a bug was found
in the code that handles "a = b" assignments, and corrected.
2019-09-09 11:26:31 -04:00
Tim Edwards 3dc70148d1 Added support in the verilog parser for definitions anywhere in the
code using the backtick expression.  Also expanded the parsing of
"ifdef", "ifndef", and "endif" to include "elsif" and "else".  All
forms of "if" statements should now be handled, since verilog does
not define boolean expressions in ifdef operators like most languages
do.
2019-09-08 19:59:27 -04:00
Tim Edwards a8576d26a9 Modified the netgen token parser, which (unwisely) is used both for
SPICE and verilog, in spite of the syntactical differences, to
account for the trick that qflow uses to replace the trailing space
in a verilog backslash-escaped name with a second backslash to get
a SPICE-compatible name that can be easily converted back to its
original verilog name without loss of information.  What this means
is that verilog can read SPICE files containing verilog names (which
is illegal SPICE) and verilog files containing hacked-backslash
names (which is illegal verilog).  This should be mostly harmless
although the wisdom of it is surely questionable.
2019-08-19 17:06:05 -04:00
Tim Edwards a31390f152 Some corrections and updates to the commit of a few days ago to
handle wire bundles in wire assignments and pin connections.
Also corrected an error in which a comment after a wire statement
causes parsing issues.
2019-08-12 13:58:19 -04:00
Tim Edwards 44ec952872 Expanded the verilog parser to handle most forms of allowable wire and
assignment statements in verilog netlists, including assignment of
signal bundles.  Also corrected handling of signal bundles in pin
connections, which had been corrected in qflow's verilog parser but
not copied back to netgen.  Note that the syntax for signals multiplied
N times is still not handled.
2019-08-10 22:30:57 -04:00
Roman-Parise 3892529873 Removed generated files and edited .gitignore 2019-08-03 16:27:13 -04:00
Roman-Parise e3b51c6004 Fixed configure scripts for FreeBSD builds 2019-08-03 16:24:24 -04:00
Roman-Parise 3200b1bf95 Added FreeBSD installation comment to README. 2019-08-03 16:24:24 -04:00
Tim Edwards 814652e552 Updated tkcon.tcl, which was not corrected for a minor problem that
affects use with Tcl/Tk 8.6 (text option "-under" not recognized;
must be "-underline").
2019-08-03 16:22:26 -04:00
Tim Edwards 4d138b64ca Corrected a missing "#ifdef TCL_NETGEN" around a Tcl subroutine
call, in objlist.c.
2019-07-24 11:13:25 -04:00
Tim Edwards 9a2902abbb Removed "makedbh", which was copied from Magic (a long, long time
ago) when building out the netgen Makefile, and never removed.  The
script is very specific to Magic.
2019-07-14 09:39:39 -04:00
59 changed files with 10349 additions and 7558 deletions

40
.github/workflows/main.yml vendored Normal file
View File

@ -0,0 +1,40 @@
# This is a basic workflow to help you get started with Actions
name: CI
# Controls when the workflow will run
on:
# Triggers the workflow on push or pull request events but only for the master branch
push:
branches: [ master ]
pull_request:
branches: [ master ]
# Allows you to run this workflow manually from the Actions tab
workflow_dispatch:
# A workflow run is made up of one or more jobs that can run sequentially or in parallel
jobs:
# This workflow contains a single job called "build"
build:
# The type of runner that the job will run on
runs-on: ubuntu-latest
# Steps represent a sequence of tasks that will be executed as part of the job
steps:
# Runs a set of commands using the runners shell
#- name: Logging into Dockerhub
# run: docker login -u ${{ secrets.DOCKERHUB_USERNAME }} -p ${{ secrets.DOCKERHUB_PASSWORD }}
- name: Pulling the docker image
run: docker pull vezzal/vezzal:v1
- name: Start the container with the docker image
run: docker run -id --name test_netgen vezzal/vezzal:v1 bash | exit
- name: Run the testing on the container and send the mail
run: docker exec test_netgen /vezzal/test_netgen.sh "tim@opencircuitdesign.com,lankasaicharan123@gmail.com" ${{ secrets.MAILING_KEY }}

6
.gitignore vendored
View File

@ -1,11 +1,17 @@
netgen
netgenexec
defs.mak
scripts/defs.mak
config.cache
config.log
scripts/config.log
config.status
scripts/config.status
python/lvs_manager.py
*.o
*.so
*~
*.log
UPDATE_ME
tcltk/netgen.sh
tcltk/netgen.tcl

View File

@ -9,7 +9,7 @@ MODULES = base
MAKEFLAGS =
INSTALL_CAD_DIRS = lib doc
include defs.mak
-include defs.mak
all: $(ALL_TARGET)
@ -51,8 +51,8 @@ depend:
install: $(INSTALL_TARGET)
install-netgen:
@echo --- installing executable to $(DESTDIR)${BINDIR}
@echo --- installing run-time files to $(DESTDIR)${LIBDIR}
@echo --- installing executable to $(DESTDIR)${INSTALL_BINDIR}
@echo --- installing run-time files to $(DESTDIR)${INSTALL_LIBDIR}
@${MAKE} install-real >> install.log
install-real: install-dirs
@ -60,15 +60,15 @@ install-real: install-dirs
(cd $$dir && ${MAKE} install); done
install-tcl-dirs:
${NETGENDIR}/scripts/mkdirs $(DESTDIR)${BINDIR} \
$(DESTDIR)${TCLDIR} $(DESTDIR)${PYDIR}
${NETGENDIR}/scripts/mkdirs $(DESTDIR)${INSTALL_BINDIR} \
$(DESTDIR)${INSTALL_TCLDIR} $(DESTDIR)${INSTALL_PYDIR}
install-dirs:
${NETGENDIR}/scripts/mkdirs $(DESTDIR)${BINDIR}
${NETGENDIR}/scripts/mkdirs $(DESTDIR)${INSTALL_BINDIR}
install-tcl: install-dirs
@echo --- installing executable to $(DESTDIR)${BINDIR}
@echo --- installing run-time files to $(DESTDIR)${LIBDIR}
@echo --- installing executable to $(DESTDIR)${INSTALL_BINDIR}
@echo --- installing run-time files to $(DESTDIR)${INSTALL_LIBDIR}
@${MAKE} install-tcl-real 2>&1 >> install.log
install-tcl-real: install-tcl-dirs

View File

@ -1,4 +1,8 @@
NETGEN: VERSION 1.5
![Continuous Integration](https://github.com/RTimothyEdwards/netgen/actions/workflows/main.yml/badge.svg)
# NETGEN
### VERSION 1.5
NETGEN is a general-purpose netlist management system. It can read
and write several netlist formats, including NTK (Caltech, CMU),
@ -85,6 +89,51 @@ and IRSIM version 9.7:
make
make install
Note: For FreeBSD, use 'gmake' instead.
Note: On MacOS (Big Sur) follow the following procedure. If you have installed `xschem` and `magic` already on MacOS then steps (1) and (2) can likely be skipped.
**1) Build Tcl for X11**
We are following the instructions from `xschem` (https://github.com/StefanSchippers/xschem/blob/master/README_MacOS.md).
* Download `Tcl` from https://prdownloads.sourceforge.net/tcl/tcl8.6.10-src.tar.gz
We are using not `opt` but `opt2` so that this `Tcl` does not interfere with `tcl-tk` from HomeBrew.
```
./configure --prefix=/usr/local/opt2/tcl-tk
make
make install
```
**2) Build Tk for X11**
* Download `Tk` from https://prdownloads.sourceforge.net/tcl/tk8.6.10-src.tar.gz
```
./configure --prefix=/usr/local/opt2/tcl-tk \
--with-tcl=/usr/local/opt2/tcl-tk/lib --with-x \
--x-includes=/opt/X11/include --x-libraries=/opt/X11/lib
make
make install
```
**3) Build netgen**
We need to provide this custom-built `tcl-tk` and suppress compilation errors.
```
./configure --with-tcl=/usr/local/opt2/tcl-tk/lib \
--with-tk=/usr/local/opt2/tcl-tk/lib \
--x-includes=/opt/X11/include \
--x-libraries=/opt/X11/lib \
CFLAGS=-Wno-error=implicit-function-declaration
make
make install
```
IN CASE OF FAILURE
-------------------
Please contact me (tim@opencircuitdesign.com) to report compile-time and

View File

@ -1 +1 @@
1.5.122
1.5.323

View File

@ -22,6 +22,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
#include <stdio.h>
#include <stdarg.h>
#include <strings.h>
#include <ctype.h>
#ifdef IBMPC
#include <stdlib.h> /* for strtol on PC */
@ -90,7 +91,7 @@ char *ActelName(char *Name)
/* strip physical-pin information, if it exists */
if ((nm = strrchr(name,PHYSICALPIN[0])) != NULL) *nm = '\0';
if (strlen(name) > 13) {
ActelIndex = (++ActelIndex) % ACTELNAMESIZE;
ActelIndex = (ActelIndex + 1) % ACTELNAMESIZE;
/* format the value of the hashed value of the string */
sprintf(ActelNames[ActelIndex], "$%lX", ActelNameHash(name));
if (Debug)
@ -101,7 +102,7 @@ Printf("ActelNameHash returns %s on name %s\n",ActelNames[ActelIndex], name);
NeedsQuoting = 0;
if (NULL != strpbrk(name, ".,:; \t\"'\n\r")) NeedsQuoting = 1;
ActelIndex = (++ActelIndex) % ACTELNAMESIZE;
ActelIndex = (ActelIndex + 1) % ACTELNAMESIZE;
if (!NeedsQuoting) {
strcpy(ActelNames[ActelIndex], name);
return(ActelNames[ActelIndex]);
@ -131,7 +132,7 @@ if format = 1, use the actel .pin file format
struct nlist *tp;
struct objlist *ob, *ob2;
char *ptr;
char physicalpin[200];
char physicalpin[MAX_STR_LEN];
tp = LookupCell(name);
if (tp == NULL) return;

View File

@ -176,4 +176,6 @@ extern int open(char *path, int oflag, ...); /* HPUX has it in <sys/fcntl.h> */
#define FALSE 0
#endif
#define MAX_STR_LEN 256
#endif /* _CONFIG_H */

View File

@ -629,7 +629,7 @@ struct embed *FlattenEmbeddingTree(struct embed *E)
int LenEmbed(char *prefix, struct nlist *np, struct embed *E, int flatten)
/* return the number of characters required to print element E */
{
char longstr[200];
char longstr[MAX_STR_LEN];
if (E == NULL) return(0);
if (E->left == NULL && E->right == NULL) {
@ -668,7 +668,7 @@ void PrintEmb(FILE *outfile, char *prefix, struct nlist *np,
struct objlist *ob;
char *instancename;
struct nlist *np2;
char name[200];
char name[MAX_STR_LEN];
ob = InstanceNumber(np,E->instancenumber);
instancename = ob->instance.name;
@ -706,7 +706,7 @@ void PrintEmbed(FILE *outfile, char *prefix, struct nlist *np,
struct objlist *ob;
char *instancename;
struct nlist *np2;
char name[200];
char name[MAX_STR_LEN];
ob = InstanceNumber(np,E->instancenumber);
instancename = ob->instance.name;

View File

@ -23,12 +23,15 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
#include <stdio.h>
#include <stdlib.h> /* for strtod() */
#include <stdarg.h>
#include <ctype.h>
#include "netgen.h"
#include "hash.h"
#include "objlist.h"
#include "netfile.h"
#include "print.h"
#include "hash.h"
static int invlambda = 100; /* Used in sim and prm files */
void extCell(char *name, int filenum)
{
@ -166,7 +169,7 @@ char *ReadExt(char *fname, int doflat, int *fnum)
int filenum;
if ((filenum = OpenParseFile(fname, *fnum)) < 0) {
char name[100];
char name[MAX_STR_LEN];
SetExtension(name, fname, EXT_EXTENSION);
if ((filenum = OpenParseFile(name, *fnum)) < 0) {
@ -186,7 +189,7 @@ char *ReadExt(char *fname, int doflat, int *fnum)
/* Make sure all .ext file reading is case sensitive */
matchfunc = match;
matchintfunc = matchfile;
hashfunc = hash;
hashfunc = hashcase;
if (LookupCellFile(fname, filenum) != NULL) {
Printf("Error: Duplicate cell name \"%s\"!\n", fname);
@ -207,7 +210,7 @@ char *ReadExt(char *fname, int doflat, int *fnum)
else if (match(nexttok, "style")) SkipNewLine(NULL);
else if (match(nexttok, "resistclasses")) SkipNewLine(NULL);
else if (match(nexttok, "node")) {
char name[200];
char name[MAX_STR_LEN];
/* No cell is generated until at least one valid "node" or "use" */
/* has been read in the file. */
@ -222,8 +225,8 @@ char *ReadExt(char *fname, int doflat, int *fnum)
SkipNewLine(NULL);
}
else if (match(nexttok, "equiv")) {
char name[200];
char name2[200];
char name[MAX_STR_LEN];
char name2[MAX_STR_LEN];
SkipTok(NULL);
GetExtName(name, nexttok);
if (LookupObject(name,CurrentCell) == NULL) Node(name);
@ -234,8 +237,8 @@ char *ReadExt(char *fname, int doflat, int *fnum)
SkipNewLine(NULL);
}
else if (match(nexttok, "device")) {
char dev_name[100], dev_class[100];
char gate[200], drain[200], source[200], subs[200];
char dev_name[MAX_STR_LEN], dev_class[MAX_STR_LEN];
char gate[MAX_STR_LEN], drain[MAX_STR_LEN], source[MAX_STR_LEN], subs[MAX_STR_LEN];
char inststr[64];
SkipTok(NULL);
strcpy(dev_class, nexttok);
@ -305,8 +308,8 @@ char *ReadExt(char *fname, int doflat, int *fnum)
SkipNewLine(NULL);
}
else if (match(nexttok, "fet")) { /* old-style FET record */
char fet_class[100];
char gate[200], drain[200], source[200], subs[200];
char fet_class[MAX_STR_LEN];
char gate[MAX_STR_LEN], drain[MAX_STR_LEN], source[MAX_STR_LEN], subs[MAX_STR_LEN];
char inststr[64];
SkipTok(NULL);
strcpy(fet_class, nexttok);
@ -364,7 +367,7 @@ char *ReadExt(char *fname, int doflat, int *fnum)
SkipNewLine(NULL);
}
else {
char ctop[200], cbot[200], cdummy[200];
char ctop[MAX_STR_LEN], cbot[MAX_STR_LEN], cdummy[MAX_STR_LEN];
SkipTok(NULL);
GetExtName(ctop, nexttok);
SkipTok(NULL);
@ -374,8 +377,8 @@ char *ReadExt(char *fname, int doflat, int *fnum)
}
}
else if (match(nexttok, "use")) {
char name[200];
char instancename[200];
char name[MAX_STR_LEN];
char instancename[MAX_STR_LEN];
char *basename;
/* No cell is generated until at least one valid "node" or "use" */
@ -389,7 +392,7 @@ char *ReadExt(char *fname, int doflat, int *fnum)
SkipTok(NULL);
GetExtName(name, nexttok);
if ((basename = strrchr(name,'/')) != NULL) {
char tmp[200];
char tmp[MAX_STR_LEN];
strcpy(tmp, basename+1);
strcpy(name, tmp);
}
@ -404,8 +407,8 @@ char *ReadExt(char *fname, int doflat, int *fnum)
SkipNewLine(NULL);
}
else if (match(nexttok, "merge")) {
char name[200];
char name2[200];
char name[MAX_STR_LEN];
char name2[MAX_STR_LEN];
SkipTok(NULL);
GetExtName(name, nexttok);
SkipTok(NULL);
@ -449,7 +452,8 @@ void simCell(char *name, int filenum)
struct nlist *tp, *tp2;
struct objlist *ob, *ob2;
char FileName[500], simclass;
short i;
char writeLine[1024], paramString[128];
short i, p, mult;
double l, w, v;
tp = LookupCellFile(name, filenum);
@ -477,9 +481,9 @@ void simCell(char *name, int filenum)
}
/* print out header list */
/* distance units are multiplied by 100 (distances are in um) */
/* distance units are multiplied by invlambda */
FlushString("| units: 100 tech: scmos\n");
FlushString("| units: %d tech: scmos\n", 100 * invlambda);
/* now run through cell's contents, print instances */
for (ob = tp->cell; ob != NULL; ob = ob->next) {
@ -515,13 +519,17 @@ void simCell(char *name, int filenum)
case CLASS_NPN:
simclass = 'b';
break;
default:
case CLASS_SUBCKT:
case CLASS_MODULE:
simclass = 'x';
break;
default:
simclass = '|';
break;
}
if (simclass != 'x')
FlushString("%c", simclass);
FlushString("%c", simclass);
switch (tp2->class) {
case CLASS_NMOS: case CLASS_NMOS4:
@ -589,6 +597,115 @@ void simCell(char *name, int filenum)
FlushString(" %g\n", v);
break;
case CLASS_MODULE:
*writeLine = 'x';
*(writeLine + 1) = '\0';
mult = 1;
/* Important---Need to look up the cell definition; if
* the first pin is "drain" then it is a FET, and pins
* get swapped from D-G-S-B to G-S-D-B. Source and drain
* are treated here as equivalent because the .sim format
* has no concept of an asymmetric source and drain.
*/
ob2 = tp2->cell;
if ((*matchfunc)(ob2->next->name, "gate"))
{
strcat(writeLine, " ");
strcat(writeLine, NodeAlias(tp, ob->next));
strcat(writeLine, " ");
strcat(writeLine, NodeAlias(tp, ob));
ob2 = ob->next->next;
}
else
ob2 = ob;
while (ob2 != NULL) {
strcat(writeLine, " ");
strcat(writeLine, NodeAlias(tp, ob2));
ob2 = ob2->next;
if ((ob2 == NULL) || (ob2->type <= FIRSTPIN)) break;
}
if (ob2 && ob2->type == PROPERTY) {
struct valuelist *vl;
/* Only known parameters are L, W, X, and Y */
for (p = 0;; p++) {
vl = (struct valuelist *)(&(ob2->instance.props[p]));
if (vl->type == PROP_ENDLIST) {
strcat(writeLine, " l=1");
break;
}
else if ((*matchfunc)(vl->key, "L")) {
v = vl->value.dval;
sprintf(paramString, " l=%d", (int)(0.5 + (v * invlambda)));
strcat(writeLine, paramString);
break;
}
}
for (p = 0;; p++) {
vl = (struct valuelist *)(&(ob2->instance.props[p]));
if (vl->type == PROP_ENDLIST) {
strcat(writeLine, " w=1");
break;
}
else if ((*matchfunc)(vl->key, "W")) {
v = vl->value.dval;
sprintf(paramString, " w=%d", (int)(0.5 + (v * invlambda)));
strcat(writeLine, paramString);
break;
}
}
for (p = 0;; p++) {
vl = (struct valuelist *)(&(ob2->instance.props[p]));
if (vl->type == PROP_ENDLIST) {
strcat(writeLine, " x=0");
break;
}
else if ((*matchfunc)(vl->key, "X")) {
i = vl->value.ival;
sprintf(paramString, " x=%d", i);
strcat(writeLine, paramString);
break;
}
}
for (p = 0;; p++) {
vl = (struct valuelist *)(&(ob2->instance.props[p]));
if (vl->type == PROP_ENDLIST) {
strcat(writeLine, " y=0");
break;
}
else if ((*matchfunc)(vl->key, "Y")) {
i = vl->value.ival;
sprintf(paramString, " y=%d", i);
strcat(writeLine, paramString);
}
}
for (p = 0;; p++) {
vl = (struct valuelist *)(&(ob2->instance.props[p]));
if (vl->type == PROP_ENDLIST) {
break;
}
else if ((*matchfunc)(vl->key, "M")) {
if (vl->type == PROP_INTEGER)
mult = vl->value.ival;
else
mult = vl->value.dval;
}
}
}
strcat(writeLine, " ");
strcat(writeLine, tp2->name);
strcat(writeLine, "\n");
/* Multiple instances (M != 1) are written multiple times.
* NF is ignored in favor of having a single device with
* the total width.
*/
for (i = 0; i < mult; i++)
FlushString(writeLine);
break;
default:
FlushString("| unhandled component %s\n", tp2->name);
break;
@ -625,6 +742,181 @@ int StrIsInt(char *s)
return (1);
}
/*------------------------------------------------------*/
/* Read a .prm format file. This is specifically to */
/* get the "device" lines that indicate how a SPICE */
/* subcircuit model or a .sim "x" record needs to be */
/* translated into a specific component type like a */
/* FET, diode, resistor, etc. */
/*------------------------------------------------------*/
char *ReadPrm(char *fname, int *fnum)
{
int filenum;
struct keyvalue *kvlist = NULL;
struct nlist *tp;
if ((filenum = OpenParseFile(fname, *fnum)) < 0) {
char name[MAX_STR_LEN];
SetExtension(name, fname, PRM_EXTENSION);
if (OpenParseFile(name, *fnum) < 0) {
Printf("Error in prm file read: No file %s\n",name);
*fnum = filenum;
return NULL;
}
}
/* Make sure all .prm file reading is case INsensitive */
/* This is because the only reason to read a PRM file */
/* is to find all the subcircuit device types so that */
/* a SPICE file can be read and a SIM file written. */
matchfunc = matchnocase;
matchintfunc = matchfile;
hashfunc = hashnocase;
CellDef(fname, filenum);
while (!EndParseFile()) {
char devicename[MAX_STR_LEN];
SkipTok(NULL);
if (EndParseFile()) break;
if (nexttok[0] == ';') continue; /* Comment line */
else if (nexttok[0] == '\0') continue; /* Blank line */
else if (match(nexttok, "lambda")) {
SkipTok(NULL);
invlambda = (int)(0.5 + (1.0 / atof(nexttok)));
SkipNewLine(NULL); /* skip any attributes */
}
else if (match(nexttok, "device")) {
SkipTok(NULL);
if (match(nexttok, "nfet")) {
SkipTok(NULL);
strcpy(devicename, nexttok);
/* Create 4-terminal nfet subcircuit device record */
if (LookupCellFile(devicename, filenum) == NULL) {
CellDef(devicename, filenum);
Port("drain");
Port("gate");
Port("source");
Port("bulk");
PropertyDouble(devicename, filenum, "l", 0.01, 0.0);
PropertyDouble(devicename, filenum, "w", 0.01, 0.0);
PropertyInteger(devicename, filenum, "nf", 0, 1);
PropertyInteger(devicename, filenum, "m", 0, 1);
SetClass(CLASS_MODULE);
EndCell();
ReopenCellDef(fname, filenum);
}
LinkProperties(devicename, kvlist);
SkipNewLine(NULL); /* skip any attributes */
}
else if (match(nexttok, "pfet")) {
SkipTok(NULL);
strcpy(devicename, nexttok);
/* Create 4-terminal pfet subcircuit device record */
if (LookupCellFile(devicename, filenum) == NULL) {
CellDef(devicename, filenum);
Port("drain");
Port("gate");
Port("source");
Port("well");
PropertyDouble(devicename, filenum, "l", 0.01, 0.0);
PropertyDouble(devicename, filenum, "w", 0.01, 0.0);
PropertyInteger(devicename, filenum, "nf", 0, 1);
PropertyInteger(devicename, filenum, "m", 0, 1);
SetClass(CLASS_MODULE);
EndCell();
ReopenCellDef(fname, filenum);
}
LinkProperties(devicename, kvlist);
SkipNewLine(NULL); /* skip various attributes */
}
else if (match(nexttok, "resistor")) {
SkipTok(NULL);
strcpy(devicename, nexttok);
/* Resistor device has additional record for the value */
/* (Need to do something with this. . . ?) */
SkipTok(NULL);
/* Create resistor subcircuit device record */
if (LookupCellFile(devicename, filenum) == NULL) {
CellDef(devicename, filenum);
Port("end_a");
Port("end_b");
PropertyDouble(devicename, filenum, "value", 0.01, 0.0);
PropertyDouble(devicename, filenum, "l", 0.01, 0.0);
PropertyDouble(devicename, filenum, "w", 0.01, 0.0);
PropertyInteger(devicename, filenum, "m", 0, 1);
SetClass(CLASS_MODULE);
EndCell();
ReopenCellDef(fname, filenum);
}
LinkProperties(devicename, kvlist);
SkipNewLine(NULL); /* skip various attributes */
}
else if (match(nexttok, "capacitor")) {
SkipTok(NULL);
strcpy(devicename, nexttok);
/* Capacitor device has additional record for the value */
/* (Need to do something with this. . . ?) */
SkipTok(NULL);
/* Create capacitor subcircuit device record */
if (LookupCellFile(devicename, filenum) == NULL) {
CellDef(devicename, filenum);
Port("top");
Port("bottom");
PropertyDouble(devicename, filenum, "value", 0.01, 0.0);
PropertyDouble(devicename, filenum, "l", 0.01, 0.0);
PropertyDouble(devicename, filenum, "w", 0.01, 0.0);
PropertyInteger(devicename, filenum, "m", 0, 1);
SetClass(CLASS_MODULE);
EndCell();
ReopenCellDef(fname, filenum); /* Reopen */
}
LinkProperties(devicename, kvlist);
SkipNewLine(NULL);
}
else if (match(nexttok, "diode")) {
SkipTok(NULL);
strcpy(devicename, nexttok);
/* Create diode subcircuit device record */
if (LookupCellFile(devicename, filenum) == NULL) {
CellDef(devicename, filenum);
Port("anode");
Port("cathode");
PropertyInteger(devicename, filenum, "m", 0, 1);
SetClass(CLASS_MODULE);
EndCell();
ReopenCellDef(fname, filenum); /* Reopen */
}
LinkProperties(devicename, kvlist);
SkipNewLine(NULL);
}
else {
Printf("Unknown device type in .prm: '%s'\n", nexttok);
InputParseError(stderr);
SkipNewLine(NULL);
}
}
else {
/* Could spell out all the keywords used in .prm files */
/* but probably not worth the effort. */
SkipNewLine(NULL);
}
DeleteProperties(&kvlist);
}
EndCell();
CloseParseFile();
tp = LookupCellFile(fname, filenum);
if (tp) tp->flags |= CELL_TOP;
*fnum = filenum;
return fname;
}
/*-------------------------*/
/* Read a .sim format file */
/*-------------------------*/
@ -639,11 +931,11 @@ char *ReadSim(char *fname, int *fnum)
double simscale = 1.0;
if ((filenum = OpenParseFile(fname, *fnum)) < 0) {
char name[100];
char name[MAX_STR_LEN];
SetExtension(name, fname, SIM_EXTENSION);
if (OpenParseFile(name, *fnum) < 0) {
Printf("Error in ext file read: No file %s\n",name);
Printf("Error in sim file read: No file %s\n",name);
*fnum = filenum;
return NULL;
}
@ -652,7 +944,7 @@ char *ReadSim(char *fname, int *fnum)
/* Make sure all .sim file reading is case sensitive */
matchfunc = match;
matchintfunc = matchfile;
hashfunc = hash;
hashfunc = hashcase;
CellDef(fname, filenum);
@ -669,7 +961,7 @@ char *ReadSim(char *fname, int *fnum)
SkipNewLine(NULL);
}
else if (match(nexttok, "n")) {
char gate[200], drain[200], source[200];
char gate[MAX_STR_LEN], drain[MAX_STR_LEN], source[MAX_STR_LEN];
char inststr[25], *instptr = NULL;
SkipTok(NULL);
@ -713,7 +1005,7 @@ char *ReadSim(char *fname, int *fnum)
LinkProperties("n", kvlist);
}
else if (match(nexttok, "p")) {
char gate[200], drain[200], source[200];
char gate[MAX_STR_LEN], drain[MAX_STR_LEN], source[MAX_STR_LEN];
char inststr[25], *instptr = NULL;
SkipTok(NULL);
GetExtName(gate, nexttok);
@ -753,7 +1045,7 @@ char *ReadSim(char *fname, int *fnum)
LinkProperties("p", kvlist);
}
else if (match(nexttok, "e")) { /* 3-port capacitors (poly/poly2) */
char gate[200], drain[200], source[200];
char gate[MAX_STR_LEN], drain[MAX_STR_LEN], source[MAX_STR_LEN];
char inststr[25], *instptr = NULL;
SkipTok(NULL);
GetExtName(gate, nexttok);
@ -787,7 +1079,7 @@ char *ReadSim(char *fname, int *fnum)
E(fname, instptr, gate, drain, source);
}
else if (match(nexttok, "b")) { /* bipolars added by Tim 7/16/96 */
char base[200], emitter[200], collector[200];
char base[MAX_STR_LEN], emitter[MAX_STR_LEN], collector[MAX_STR_LEN];
char inststr[25], *instptr = NULL;
SkipTok(NULL);
GetExtName(base, nexttok);
@ -825,7 +1117,7 @@ char *ReadSim(char *fname, int *fnum)
SkipNewLine(NULL);
}
else {
char ctop[200], cbot[200], cdummy[200];
char ctop[MAX_STR_LEN], cbot[MAX_STR_LEN], cdummy[MAX_STR_LEN];
SkipTok(NULL);
GetExtName(ctop, nexttok);
if (LookupObject(ctop, CurrentCell) == NULL)
@ -846,11 +1138,11 @@ char *ReadSim(char *fname, int *fnum)
}
else if (match(nexttok, "r")) { /* 2-port resistors */
if (IgnoreRC) {
/* ignore all capacitances */
/* ignore all resistances */
SkipNewLine(NULL);
}
else {
char rtop[200], rbot[200];
char rtop[MAX_STR_LEN], rbot[MAX_STR_LEN];
SkipTok(NULL);
GetExtName(rtop, nexttok);
if (LookupObject(rtop, CurrentCell) == NULL)
@ -874,7 +1166,7 @@ char *ReadSim(char *fname, int *fnum)
SkipNewLine(NULL);
}
else {
char rtop[200], rbot[200], rdummy[200];
char rtop[MAX_STR_LEN], rbot[MAX_STR_LEN], rdummy[MAX_STR_LEN];
char inststr[25], *instptr = NULL;
SkipTok(NULL);
GetExtName(rdummy, nexttok);
@ -916,7 +1208,7 @@ char *ReadSim(char *fname, int *fnum)
SkipNewLine(NULL);
}
else if (match(nexttok, "=")) {
char node1[200], node2[200];
char node1[MAX_STR_LEN], node2[MAX_STR_LEN];
SkipTok(NULL);
GetExtName(node1, nexttok);
SkipTok(NULL);

File diff suppressed because it is too large Load Diff

8
base/flatten.h Normal file
View File

@ -0,0 +1,8 @@
#ifndef _FLATTEN_H
#define _FLATTEN_H
extern int UniquePins(char *name, int filenum);
extern void flattenCell(char *name, int file);
extern int HasContents(struct nlist *);
#endif /* _FLATTEN_H */

View File

@ -30,8 +30,8 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
#endif
#include "netgen.h"
#include "hash.h"
#include "objlist.h"
#include "hash.h"
unsigned long (*hashfunc)(char *, int) = NULL;
int (*matchfunc)(char *, char *) = NULL;
@ -137,32 +137,39 @@ static unsigned char uppercase[] = {
// horrible things can happen, as, for example, names AOI12 and OAI12
// have exactly the same hash result. Lousy for binning and even
// lousier for generating class magic numbers.
//
// Updated again 4/2/2026 to the FNV-1a hash, which is better than
// SDBM for this application, according to ChatGPT.
unsigned long hashnocase(char *s, int hashsize)
{
unsigned long hashval;
for (hashval = 0; *s != '\0'; )
hashval = uppercase[*s++]
+ (hashval << 6) + (hashval << 16) - hashval;
unsigned long hashval = 2166136261ul;
for (; *s != '\0'; s++) {
hashval ^= uppercase[*s];
hashval *= 16777619ul;
}
return (hashsize == 0) ? hashval : (hashval % hashsize);
}
unsigned long hash(char *s, int hashsize)
unsigned long hashcase(char *s, int hashsize)
{
unsigned long hashval;
for (hashval = 0; *s != '\0'; )
hashval = (*s++) + (hashval << 6) + (hashval << 16) - hashval;
unsigned long hashval = 2166136261ul;
for (; *s != '\0'; s++) {
hashval ^= (unsigned char)(*s);
hashval *= 16777619ul;
}
return (hashsize == 0) ? hashval : (hashval % hashsize);
}
unsigned long genhash(char *s, int c, int hashsize)
{
unsigned long hashval;
for (hashval = (unsigned long)c; *s != '\0'; )
hashval = (*s++) + (hashval << 6) + (hashval << 16) - hashval;
unsigned long hashval = 2166136261ul;
hashval ^= (unsigned long)c;
hashval *= 16777619ul;
for (; *s != '\0'; s++) {
hashval ^= (unsigned char)(*s);
hashval *= 16777619ul;
}
return (hashsize == 0) ? hashval : (hashval % hashsize);
}

View File

@ -48,7 +48,7 @@ extern void *HashFirst(struct hashdict *dict);
extern void *HashNext(struct hashdict *dict);
extern unsigned long hashnocase(char *s, int hashsize);
extern unsigned long hash(char *s, int hashsize);
extern unsigned long hashcase(char *s, int hashsize);
extern int (*matchfunc)(char *, char *);
/* matchintfunc() compares based on the name and the first */

View File

@ -17,6 +17,7 @@ along with this program; see the file copying. If not, write to
the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
/* inetcomp.c -- a simple wrapper to the NETCOMP() function */
#include "config.h"
#include <stdio.h>
#include "netgen.h"
@ -33,7 +34,7 @@ void STRCPY(char *dest, char *source)
int main(int argc, char *argv[])
{
char cell1[200], cell2[200];
char cell1[MAX_STR_LEN], cell2[MAX_STR_LEN];
Debug = 0;
if (argc != 1) {

File diff suppressed because it is too large Load Diff

View File

@ -7,6 +7,10 @@ extern struct nlist *Circuit1;
extern struct nlist *Circuit2;
extern int ExhaustiveSubdivision;
extern int ExactTopology;
extern int left_col_end;
extern int right_col_end;
#ifdef TCL_NETGEN
#include <tcl.h>
@ -23,6 +27,7 @@ extern void PrintCoreStats(void);
extern void ResetState(void);
extern void CreateTwoLists(char *name1, int file1, char *name2, int file2,
int dolist);
extern void DescribeContents(char *name1, int file1, char *name2, int file2);
extern int Iterate(void);
extern int VerifyMatching(void);
extern void PrintAutomorphisms(void);
@ -33,7 +38,8 @@ extern int PermuteSetup(char *model, int filenum, char *pin1, char *pin2);
extern int PermuteForget(char *model, int filenum, char *pin1, char *pin2);
extern int EquivalenceElements(char *name1, int file1, char *name2, int file2);
extern int EquivalenceNodes(char *name1, int file1, char *name2, int file2);
extern int EquivalenceClasses(char *name1, int file1, char *name2, int file2);
extern int EquivalenceClasses(char *name1, int file1, char *name2, int file2,
int dounique);
extern int IgnoreClass(char *name, int file, unsigned char type);
extern int MatchPins(struct nlist *tp1, struct nlist *tp2, int dolist);
extern int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run,
@ -43,6 +49,7 @@ extern int CreateCompareQueue(char *, int, char *, int);
extern int GetCompareQueueTop(char **, int *, char **, int *);
extern int PeekCompareQueueTop(char **, int *, char **, int *);
extern void RemoveCompareQueue();
extern int FlattenUnmatched(struct nlist *, char *, int, int);
extern void PrintIllegalClasses();
extern void PrintIllegalNodeClasses();
@ -51,9 +58,20 @@ extern void PrintIllegalElementClasses();
extern void DumpNetwork(struct objlist *ob, int cidx);
extern void DumpNetworkAll(char *name, int file);
extern void RegroupDataStructures();
extern void FormatIllegalElementClasses();
extern void FormatIllegalNodeClasses();
extern int ResolveAutomorphsByProperty();
extern int ResolveAutomorphsByPin(int match_nets);
extern void SummarizeElementClasses(struct ElementClass *EC);
extern int remove_group_tags(struct objlist *ob);
#ifdef TCL_NETGEN
extern int EquivalentNode();
extern int EquivalentElement();
extern void DeriveAreaProperty();
extern void DerivePerimeterProperty();
extern void enable_interrupt();
extern void disable_interrupt();

View File

@ -47,6 +47,18 @@ static FILE *outfile;
static int Graph = 0;
int File;
/*------------------------------------------------------*/
/* Structure for stacking nested `if[n]def in verilog */
/*------------------------------------------------------*/
struct ifstack {
int invert;
struct property *kl;
struct ifstack *next;
};
struct ifstack *condstack = NULL;
extern char *SetExtension(char *buffer, char *path, char *extension)
/* add 'extension' to 'path' (overwriting previous extension, if any),
write it into buffer (if buffer is null, malloc a buffer).
@ -171,7 +183,6 @@ void CloseFile(char *filename)
fclose(outfile);
}
/* STUFF TO READ INPUT FILES */
static char *line = NULL; /* actual line read in */
@ -191,11 +202,29 @@ struct filestack {
static struct filestack *OpenFiles = NULL;
struct hashdict *definitions = (struct hashdict *)NULL;
#define WHITESPACE_DELIMITER " \t\n\r"
/*----------------------------------------------------------------------*/
/* Seek and Tell on infile stream, for use with handling generate */
/* loops in verilog. */
/*----------------------------------------------------------------------*/
void SeekFile(long offset)
{
fseek(infile, offset, SEEK_SET);
}
long TellFile()
{
return ftell(infile);
}
/*----------------------------------------------------------------------*/
/* TrimQuoted() --- */
/* Remove spaces from inside single- or double-quoted strings. */
/* Ignore verilog constant bits (e.g., "1'b0") when parsing. */
/*----------------------------------------------------------------------*/
void TrimQuoted(char *line)
@ -211,6 +240,13 @@ void TrimQuoted(char *line)
{
changed = FALSE;
qstart = strchr(lptr, '\'');
if (qstart && (qstart > lptr)) {
if (isdigit(*(qstart - 1))) {
lptr = qstart + 1;
changed = TRUE;
continue;
}
}
if (qstart)
{
qend = strchr(qstart + 1, '\'');
@ -251,7 +287,6 @@ void TrimQuoted(char *line)
}
}
}
}
/*----------------------------------------------------------------------*/
@ -265,39 +300,231 @@ void TrimQuoted(char *line)
int GetNextLineNoNewline(char *delimiter)
{
char *newbuf;
int testc;
char *newbuf;
int testc;
static int nested = 0;
int llen;
if (feof(infile)) return -1;
if (feof(infile)) return -1;
// This is more reliable than feof() ...
testc = getc(infile);
if (testc == -1) return -1;
ungetc(testc, infile);
while (1) { /* May loop indefinitely in an `if[n]def conditional */
if (linesize == 0) {
/* Allocate memory for line */
linesize = 500;
line = (char *)MALLOC(linesize);
linetok = (char *)MALLOC(linesize);
}
fgets(line, linesize, infile);
while (strlen(line) == linesize - 1) {
newbuf = (char *)MALLOC(linesize + 500);
strcpy(newbuf, line);
FREE(line);
line = newbuf;
fgets(line + linesize - 1, 501, infile);
linesize += 500;
FREE(linetok);
linetok = (char *)MALLOC(linesize);
}
linenum++;
strcpy(linetok, line);
TrimQuoted(linetok);
// This is more reliable than feof() ...
testc = getc(infile);
if (testc == -1) return -1;
ungetc(testc, infile);
nexttok = strdtok(linetok, WHITESPACE_DELIMITER, delimiter);
return 0;
if (linesize == 0) {
/* Allocate memory for line */
linesize = 2000;
line = (char *)MALLOC(linesize + 1);
linetok = (char *)MALLOC(linesize + 1);
}
fgets(line, linesize, infile);
/* Immediately resolve backslash-EOL */
llen = strlen(line);
while ((llen > 1) && (llen < linesize - 1) && *(line + llen - 2) == '\\') {
*(line + llen - 2) = '\n';
fgets(line + llen - 1, linesize - llen + 1, infile);
llen = strlen(line);
}
while (llen == linesize - 1) {
/* Note that in the rare case where a newline is in the last buffer
* position, we're done.
*/
if (*(line + llen - 1) == '\n') break;
newbuf = (char *)MALLOC(linesize + 501);
strcpy(newbuf, line);
FREE(line);
line = newbuf;
fgets(line + linesize - 1, 501, infile);
llen = strlen(line);
while ((llen > 1) && (llen < linesize - 1) && *(line + llen - 2) == '\\') {
*(line + llen - 2) = '\n';
fgets(line + llen - 1, linesize - llen + 1, infile);
llen = strlen(line);
}
linesize += 500;
FREE(linetok);
linetok = (char *)MALLOC(linesize + 1);
}
if (definitions == NULL)
strcpy(linetok, line);
else {
char *s, *t, *w, e;
struct property *kl;
int len, dlen, vlen, addin = 0;
int oldlinesize = linesize;
unsigned char found = TRUE;
/* Check for substitutions (verilog only). Make sure linetok is */
/* large enough to hold the entire line after substitutions. */
while (found) { /* Do this recursively, for nested definitions */
found = FALSE;
for (s = line; *s != '\0'; s++) {
if (*s == '`') {
w = s + 1;
while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
e = *w;
*w = '\0';
kl = (struct property *)HashLookup(s + 1, definitions);
if (kl != NULL) {
dlen = strlen(s);
if (kl->type == PROP_STRING) {
vlen = strlen(kl->pdefault.string);
}
else vlen = 12; /* Leave room for numeric conversion */
addin += vlen - dlen + 1;
found = TRUE;
}
*w = e;
}
}
if (found) {
len = strlen(line);
if (len + addin > linesize) {
while (len + addin > linesize) linesize += 500;
FREE(linetok);
linetok = (char *)MALLOC(linesize);
}
}
/* Make definition substitutions (verilog only) */
t = linetok;
for (s = line; *s != '\0'; s++) {
if (*s == '`') {
w = s + 1;
while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
e = *w;
*w = '\0';
kl = (struct property *)HashLookup(s + 1, definitions);
if (kl != NULL) {
if (kl->type == PROP_STRING)
strcpy(t, kl->pdefault.string);
else if (kl->type == PROP_INTEGER)
sprintf(t, "%d", kl->pdefault.ival);
else if (kl->type == PROP_DOUBLE)
sprintf(t, "%g", kl->pdefault.dval);
t += strlen(t);
s = w - 1;
}
else *t++ = *s;
*w = e;
}
else *t++ = *s;
}
*t = '\0';
/* Copy substituted linetok back to line and repeat until */
/* there are no more substitutions to be made. */
if (oldlinesize != linesize) {
FREE(line);
line = (char *)MALLOC(linesize + 501);
oldlinesize = linesize;
}
strcpy(line, linetok);
}
}
TrimQuoted(linetok);
linenum++;
nexttok = strdtok(linetok, WHITESPACE_DELIMITER, delimiter);
if (nexttok == NULL) return 0;
/* Handle `ifdef, `ifndef, `elsif, `else, and `endif (verilog */
/* only, where indicated by a non-NULL "definitions") */
if (definitions == NULL) return 0;
/* If currently skipping through a section, handle conditionals differently */
if (condstack) {
if (((condstack->invert == 0) && (condstack->kl == NULL))
|| ((condstack->invert == 1) && (condstack->kl != NULL))) {
if (match(nexttok, "`ifdef") || match(nexttok, "`ifndef")) {
nested++;
continue;
}
else if (nested > 0) {
if (match(nexttok, "`endif")) nested--;
continue;
}
else if (nexttok[0] != '`') continue;
}
}
/* Handle conditionals (that is not being skipped over) */
if (match(nexttok, "`endif")) {
if (condstack == NULL) {
fprintf(stderr, "Error: `endif without corresponding `if[n]def\n");
}
else {
struct ifstack *iftop = condstack;
condstack = condstack->next;
FREE(iftop);
}
}
/* Note that `if[n]def may be nested. */
else if (match(nexttok, "`ifdef") || match(nexttok, "`ifndef") ||
match(nexttok, "`elsif") || match(nexttok, "`else")) {
/* Every `ifdef or `ifndef increases condstack by 1 */
if (nexttok[1] == 'i') {
struct ifstack *newif = (struct ifstack *)MALLOC(sizeof(struct ifstack));
newif->next = condstack;
condstack = newif;
}
if (condstack == NULL) {
fprintf(stderr, "Error: %s without `if[n]def\n", nexttok);
break;
}
else {
if (match(nexttok, "`else")) {
/* Invert the sense of the if[n]def scope */
condstack->invert = (condstack->invert == 1) ? 0 : 1;
}
else if (match(nexttok, "`elsif")) {
nexttok = strdtok(NULL, WHITESPACE_DELIMITER, delimiter);
if (nexttok == NULL) {
fprintf(stderr, "Error: `elsif with no conditional.\n");
return 0;
}
/* Keep the same scope but redefine the parameter */
condstack->invert = 0;
condstack->kl = (struct property *)HashLookup(nexttok, definitions);
}
else {
condstack->invert = (nexttok[3] == 'n') ? 1 : 0;
nexttok = strdtok(NULL, WHITESPACE_DELIMITER, delimiter);
if (nexttok == NULL) {
fprintf(stderr, "Error: %s with no conditional.\n", nexttok);
return 0;
}
condstack->kl = (struct property *)HashLookup(nexttok, definitions);
}
}
}
else if (condstack) {
if (((condstack->invert == 0) && (condstack->kl == NULL))
|| ((condstack->invert == 1) && (condstack->kl != NULL)))
continue;
else
break;
}
else
break;
}
return 0;
}
/*----------------------------------------------------------------------*/
@ -312,6 +539,24 @@ void GetNextLine(char *delimiter)
} while (nexttok == NULL);
}
/*----------------------------------------------------------------------*/
/* Return a pointer to the line at the position of nexttok */
/* This is used only when returning the entire line, untokenized, and */
/* is only called by the verilog read routine when reading the value of */
/* a `define statement. */
/*----------------------------------------------------------------------*/
char *GetLineAtTok()
{
char *lpos;
if (nexttok == NULL) return NULL;
if (line == NULL) return NULL;
lpos = strstr(line, nexttok);
return lpos;
}
/*----------------------------------------------------------------------*/
/* if nexttok is already NULL, force scanner to read new line */
/*----------------------------------------------------------------------*/
@ -347,19 +592,31 @@ void SkipTokNoNewline(char *delimiter)
/* */
/* Modified 3/30/2015 to include the condition where a comment line is */
/* in the middle of a series of continuation lines. */
/* */
/* Modified 1/3/2024 to avoid skipping two lines if a line has only the */
/* comment character '*' followed by a newline. It seems that '\n' is */
/* being ignored in WHITESPACE_DELIMITER, but it's easier to write the */
/* code to find the exception rather than track down the problem in */
/* GetNextLine(). */
/*----------------------------------------------------------------------*/
void SpiceTokNoNewline(void)
{
int contline;
if ((nexttok = strdtok(NULL, WHITESPACE_DELIMITER, NULL)) != NULL) return;
if ((nexttok = strdtok0(NULL, WHITESPACE_DELIMITER, NULL, FALSE)) != NULL) return;
while (nexttok == NULL) {
contline = getc(infile);
if (contline == '*') {
GetNextLine(WHITESPACE_DELIMITER);
SkipNewLine(NULL);
char testline = ' ';
while ((testline == ' ') || (testline == '\t'))
testline = getc(infile);
if (testline != '\n') {
ungetc(testline, infile);
GetNextLine(WHITESPACE_DELIMITER);
SkipNewLine(NULL);
}
continue;
}
else if (contline != '+') {
@ -371,7 +628,8 @@ void SpiceTokNoNewline(void)
}
/*----------------------------------------------------------------------*/
/* Skip to the next token, ignoring any C-style comments. */
/* Skip to the next token, ignoring any C-style comments and verilog */
/* "(* ... *)"-style comments. */
/*----------------------------------------------------------------------*/
void SkipTokComments(char *delimiter)
@ -387,6 +645,11 @@ void SkipTokComments(char *delimiter)
SkipTok(delimiter);
if (nexttok) SkipTok(delimiter);
}
else if (match(nexttok, "(*")) {
while (nexttok && !match(nexttok, "*)"))
SkipTok(delimiter);
if (nexttok) SkipTok(delimiter);
}
else break;
}
}
@ -422,6 +685,7 @@ void SpiceSkipNewLine(void)
ungetc(contline, infile);
}
#if 0 /* Commented with "#if 0" due to comment characters in the comment */
/*----------------------------------------------------------------------*/
/* Function similar to strtok() for token parsing. The difference is */
/* that it takes two sets of delimiters. The first is whitespace */
@ -442,8 +706,9 @@ void SpiceSkipNewLine(void)
/* the first character of the delimiter string in addition to marking */
/* the boundary between two-character and one-character delimiters. */
/*----------------------------------------------------------------------*/
#endif
char *strdtok(char *pstring, char *delim1, char *delim2)
char *strdtok0(char *pstring, char *delim1, char *delim2, char isverilog)
{
static char *stoken = NULL;
static char *sstring = NULL;
@ -478,9 +743,20 @@ char *strdtok(char *pstring, char *delim1, char *delim2)
/* space character becomes part of the verilog name. The remainder of the */
/* name is parsed according to the rules of "delim2". */
if (*s == '\\') {
/* Special verilog rule exception: To handle the problems caused by */
/* translating verilog backslash-escaped names into other netlist formats */
/* like SPICE where the convention is strictly prohibited, I have used the */
/* convention in qflow scripts to replace the trailing space with another */
/* backslash, so the name is effectively delimited by a pair of back- */
/* slashes. Therefore check for a space or another backslash, whichever */
/* comes first. That will satisfy both methods. Technically this routine */
/* should know whether it is parsing SPICE or verilog and handle the syntax */
/* accordingly (needs to be done). */
if (isverilog && (*s == '\\')) {
s++;
while (*s != '\0') {
if (*s == ' ') {
if ((*s == ' ') || ((*s == '\\') && (*(s + 1) == '\0'))) {
s++;
break;
}
@ -548,6 +824,17 @@ char *strdtok(char *pstring, char *delim1, char *delim2)
return sstring;
}
/*----------------------------------------------------------------------*/
/* strdtok() is the original string tokenizer. It calls strdtok0() */
/* with isverilog=TRUE, so that tokens are parsed as (potentially) */
/* verilog names, which includes verilog backslash notation. */
/*----------------------------------------------------------------------*/
char *strdtok(char *pstring, char *delim1, char *delim2)
{
return strdtok0(pstring, delim1, delim2, TRUE);
}
/*----------------------------------------------------------------------*/
void InputParseError(FILE *f)
@ -571,7 +858,7 @@ int OpenParseFile(char *name, int fnum)
FILE *locfile;
struct filestack *newfile;
locfile = fopen(name,"r");
locfile = fopen(name, "r");
linenum = 0;
/* reset the token scanner */
nexttok = NULL;
@ -629,7 +916,7 @@ char *ReadNetlist(char *fname, int *fnum)
};
#ifdef mips
struct filetype formats[7];
struct filetype formats[8];
formats[0].extension = NTK_EXTENSION;
formats[0].proc = ReadNtk;
@ -637,14 +924,16 @@ char *ReadNetlist(char *fname, int *fnum)
formats[1].proc = ReadExtHier;
formats[2].extension = SIM_EXTENSION;
formats[2].proc = ReadSim;
formats[3].extension = SPICE_EXTENSION;
formats[3].proc = ReadSpice;
formats[4].extension = NETGEN_EXTENSION;
formats[4].proc = ReadNetgenFile;
formats[5].extension = VERILOG_EXTENSION;
formats[5].proc = ReadVerilogFile;
formats[6].extension = NULL;
formats[6].proc = NULL;
formats[3].extension = PRM_EXTENSION;
formats[3].proc = ReadPrm;
formats[4].extension = SPICE_EXTENSION;
formats[4].proc = ReadSpice;
formats[5].extension = NETGEN_EXTENSION;
formats[5].proc = ReadNetgenFile;
formats[6].extension = VERILOG_EXTENSION;
formats[6].proc = ReadVerilogFile;
formats[7].extension = NULL;
formats[7].proc = NULL;
#else /* not mips (i.e. compiler with reasonable initializers) */
@ -653,10 +942,16 @@ char *ReadNetlist(char *fname, int *fnum)
{NTK_EXTENSION, ReadNtk},
{EXT_EXTENSION, ReadExtHier},
{SIM_EXTENSION, ReadSim},
{PRM_EXTENSION, ReadPrm},
{SPICE_EXTENSION, ReadSpice},
{SPICE_EXT2, ReadSpice},
{SPICE_EXT3, ReadSpice},
{SPICE_EXT4, ReadSpice},
{SPICE_EXT5, ReadSpice},
{SPICE_EXT6, ReadSpice},
{SPICE_EXT7, ReadSpice},
{VERILOG_EXTENSION, ReadVerilog},
{SYS_VERILOG_EXTENSION, ReadVerilog},
{NETGEN_EXTENSION, ReadNetgenFile},
{NULL, NULL}
};
@ -664,13 +959,15 @@ char *ReadNetlist(char *fname, int *fnum)
/* make first pass looking for extension */
for (index = 0; formats[index].extension != NULL; index++) {
if (strstr(fname, formats[index].extension) != NULL) {
int extlen = strlen(formats[index].extension);
int flen = strlen(fname);
if (!strcmp(fname + flen - extlen, formats[index].extension)) {
return (*(formats[index].proc))(fname, fnum);
}
}
/* try appending extensions in sequence, and testing for file existance */
for (index = 0; formats[index].extension != NULL; index++) {
char testname[200];
char testname[MAX_STR_LEN];
strcpy(testname, fname);
strcat(testname, formats[index].extension);
if (OpenParseFile(testname, *fnum) >= 0) {
@ -775,7 +1072,7 @@ void WriteNetgenFile(char *name, char *filename)
char *ReadNetgenFile (char *fname, int *fnum)
{
char name[100];
char name[MAX_STR_LEN];
char *LastCellRead = NULL;
int filenum;
@ -1011,7 +1308,7 @@ int READ(void *buf, int bytes)
char *ReadNetgenFile (char *fname, int *fnum)
{
char name[100];
char name[MAX_STR_LEN];
int len, chars;
char *LastCellRead = NULL;

View File

@ -7,13 +7,19 @@
#define WOMBAT_EXTENSION ".wom"
#define EXT_EXTENSION ".ext"
#define SIM_EXTENSION ".sim"
#define PRM_EXTENSION ".prm"
#define SPICE_EXTENSION ".spice"
#define SPICE_EXT2 ".spc"
#define SPICE_EXT3 ".fspc"
#define SPICE_EXT3 ".sp"
#define SPICE_EXT4 ".spi"
#define SPICE_EXT5 ".fspc"
#define SPICE_EXT6 ".cir"
#define SPICE_EXT7 ".ckt"
#define NETGEN_EXTENSION ".ntg"
#define CCODE_EXTENSION ".c.code"
#define ESACAP_EXTENSION ".esa"
#define VERILOG_EXTENSION ".v"
#define SYS_VERILOG_EXTENSION ".sv"
#define LINELENGTH 80
@ -24,14 +30,18 @@ extern void FlushString (char *format, ...);
extern char *SetExtension(char *buffer, char *path, char *extension);
extern int File;
extern struct hashdict *definitions;
/* input routines */
extern char *nexttok;
#define SKIPTO(a) do {SkipTok(NULL);} while (!match(nexttok,a))
extern char *strdtok0(char *pstring, char *delim1, char *delim2, char isverilog);
extern char *strdtok(char *pstring, char *delim1, char *delim2);
extern char *GetLineAtTok();
extern void SkipTok(char *delimiter);
extern void SkipTokNoNewline(char *delimiter);
extern void SkipTokComments(char *delimiter);
extern void SkipNewLine(char *delimiter);
extern void SpiceTokNoNewline(void); /* handles SPICE "+" continuation line */
extern void SpiceSkipNewLine(void); /* handles SPICE "+" continuation line */
@ -39,5 +49,7 @@ extern void InputParseError(FILE *f);
extern int OpenParseFile(char *name, int fnum);
extern int EndParseFile(void);
extern int CloseParseFile(void);
extern void SeekFile(long offset); /* handles verilog 'for' loops */
extern long TellFile(); /* handles verilog 'for' loops */
#endif /* _NETFILE_H */

File diff suppressed because it is too large Load Diff

View File

@ -39,11 +39,13 @@ extern void SetParallelCombine(int value);
extern void SetSeriesCombine(int value);
extern int PropertyTolerance(char *name, int fnum, char *key, int ival,
double dval);
extern int PropertyAssociatePin(char *name, int fnum, char *key, char *pin);
extern int PropertyMerge(char *name, int fnum, char *key, int merge_type,
int merge_mask);
extern void ResolveProperties(char *name1, int file1, char *name2, int file2);
extern void CopyProperties(struct objlist *obj_to, struct objlist *obj_from);
extern int PromoteProperty(struct property *, struct valuelist *);
extern int PromoteProperty(struct property *, struct valuelist *,
struct objlist *, struct nlist *);
extern int SetPropertyDefault(struct property *, struct valuelist *);
extern struct objlist *LinkProperties(char *model, struct keyvalue *topptr);
extern int ReduceExpressions(struct objlist *instprop, struct objlist *parprops,
@ -65,6 +67,15 @@ extern void AssignCircuits(char *name1, int file1, char *name2, int file2);
/* flatten.c */
extern int PrematchLists(char *, int, char *, int);
/* verilog.c */
struct cellstack {
char *cellname;
struct cellstack *next;
};
void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,
int blackbox);
/* Define (enumerate) various device classes, largely based on SPICE */
/* model types, mixed with some ext/sim types. */
@ -140,6 +151,7 @@ extern int NoOutput; /* set this to 1 to disable stdout output */
extern int Composition; /* direction of composition */
extern int UnixWildcards; /* TRUE if *,?,{},[] only; false if full REGEXP */
extern int GlobalParallelNone; /* If TRUE, don't parallel combine any cells */
extern int GlobalParallelOpen; /* If TRUE, parallel combine cells w/no-connects */
/* magic internal flag to restrict searches to recently placed cells */
extern int QuickSearch;
/* does re"CellDef"ing a cell add to it or overwrite it??? */
@ -179,6 +191,7 @@ extern char *ReadNtk (char *fname, int *fnum);
extern char *ReadExtHier(char *fname, int *fnum);
extern char *ReadExtFlat(char *fname, int *fnum);
extern char *ReadSim(char *fname, int *fnum);
extern char *ReadPrm(char *fname, int *fnum);
extern char *ReadSpice(char *fname, int *fnum);
extern char *ReadSpiceLib(char *fname, int *fnum);
extern char *ReadNetgenFile (char *fname, int *fnum);

View File

@ -181,7 +181,7 @@ void Ntk(char *name, char *filename)
char *ReadNtk (char *fname, int *fnum)
{
char model[100], instancename[100], name[100];
char model[MAX_STR_LEN], instancename[MAX_STR_LEN], name[MAX_STR_LEN];
struct objlist *ob;
int CellDefInProgress = 0;
int filenum;
@ -218,7 +218,7 @@ char *ReadNtk (char *fname, int *fnum)
}
}
else if (match(nexttok, "s")) {
char last[100];
char last[MAX_STR_LEN];
*last = '\0';
if (!CellDefInProgress) {
/* fake cell declaration for top-level call */

View File

@ -22,6 +22,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
#include <stdio.h>
#include <ctype.h>
#include <limits.h>
#ifdef IBMPC
#include <alloc.h>
#endif
@ -31,13 +32,13 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
#endif
#include "netgen.h"
#include "hash.h"
#include "objlist.h"
#include "regexp.h"
#include "dbug.h"
#include "print.h"
#include "netfile.h"
#include "netcmp.h"
#include "hash.h"
#ifdef TCL_NETGEN
extern Tcl_Interp *netgeninterp;
@ -129,6 +130,7 @@ struct property *NewProperty(void)
kl = (struct property *)CALLOC(1,sizeof(struct property));
if (kl == NULL) Fprintf(stderr,"NewProperty: Core allocation error\n");
kl->pin = (char *)NULL;
return (kl);
}
@ -221,12 +223,35 @@ int matchnocase(char *st1, char *st2)
{
char *sp1 = st1;
char *sp2 = st2;
char v1 = FALSE, v2 = FALSE;
/* In case of a property that does not exist in one netlist, matchnocase()
* may be passed a null value, so return 0 to indicate a non-match.
* *Both* values null will also be treated as a mismatch (debatable
* behavior).
*/
if (!sp1 || !sp2) return 0;
/* Verilog back-slash escaped names should match an equivalent non-
* back-slashed name. (NOTE: This behavior needs to be added to match().)
*/
if ((*sp1 == '\\') && (*sp2 != '\\')) {
v1 = TRUE;
sp1++;
}
if ((*sp2 == '\\') && (*sp1 != '\\')) {
v2 = TRUE;
sp2++;
}
while (*sp1 != '\0' && *sp2 != '\0') {
if (to_lower[*sp1] != to_lower[*sp2]) break;
sp1++;
sp2++;
}
if (v1 && (*sp1 == ' ')) sp1++;
if (v2 && (*sp2 == ' ')) sp2++;
if ((*sp1 != '\0') || (*sp2 != '\0')) return 0;
return 1;
}
@ -257,6 +282,33 @@ int matchfilenocase(char *st1, char *st2, int f1, int f2)
return 1;
}
/* Delimiter matching---Find an opening delimiter in a string. */
/* Return the position of the first opening delimeter in the string, */
/* like strchr(). Place the actual delimeter character in *delim. */
char *get_array_delimiter(char *name, char *delim)
{
char *stest = name;
while (*stest != '\0')
{
if (to_lower[*stest] == '<') {
*delim = *stest;
return stest;
}
stest++;
}
return NULL;
}
/* Delimiter parsing---Check if a character is an opening array delimiter. */
/* Return TRUE if the character is an opening delimiter, FALSE if not. */
int is_delimiter(char testc)
{
return (to_lower[testc] == '<') ? TRUE : FALSE;
}
#ifdef HAVE_MALLINFO
void PrintMemoryStats(void)
{
@ -288,8 +340,8 @@ static struct hashdict cell_dict;
void InitCellHashTable(void)
{
hashfunc = hash;
matchfunc = match;
hashfunc = hashcase;
matchfunc = NULL;
matchintfunc = matchfile;
InitializeHashTable(&cell_dict, CELLHASHSIZE);
}
@ -424,6 +476,7 @@ int removeshorted(struct hashlist *p, int file)
ob = nob;
}
}
return 1;
}
/* Remove shorted instances of class "class" from the database */
@ -439,15 +492,32 @@ void RemoveShorted(char *class, int file)
RecurseCellFileHashTable(removeshorted, file);
}
/* Remove instances of a deleted class from the database. */
/* NOTE: This treats deleted classes as not existing, so it */
/* needs to take care of disconnected ports in the same manner */
/* as flattenInstancesOf() in disconnecting the port of a */
/* parent cell if it connected to nothing other than the */
/* deleted instance. */
int deleteclass(struct hashlist *p, int file)
{
struct nlist *ptr;
struct objlist *ob, *lob, *nob;
struct objlist *ob, *lob, *nob, *portnode;
unsigned char *checknodes;
int i;
ptr = (struct nlist *)(p->ptr);
if ((file != -1) && (ptr->file != file)) return 0;
/* Note: This could be made faster by enumerating all times each
* node is used during the full pass, then subtracting each time
* the node is deleted in a child, then disconnecting all nodes
* that ended up with a zero count.
*/
checknodes = (unsigned char *)CALLOC(ptr->nodename_cache_maxnodenum + 1,
sizeof(unsigned char));
lob = NULL;
for (ob = ptr->cell; ob != NULL;) {
nob = ob->next;
@ -455,6 +525,8 @@ int deleteclass(struct hashlist *p, int file)
if ((*matchfunc)(ob->model.class, OldCell->name)) {
HashDelete(ob->instance.name, &(ptr->instdict));
while (1) {
if (ob->type >= FIRSTPIN)
checknodes[ob->node] = (unsigned char)1;
FreeObjectAndHash(ob, ptr);
ob = nob;
if (ob == NULL) break;
@ -476,6 +548,26 @@ int deleteclass(struct hashlist *p, int file)
ob = nob;
}
}
for (i = 0; i <= ptr->nodename_cache_maxnodenum; i++) {
if (checknodes[i] != 0) {
portnode = NULL;
for (ob = ptr->cell; ob != NULL; ob = ob->next) {
if ((ob->type != PORT) && (portnode == NULL))
break;
else if ((ob->type == PORT) && (ob->node == i))
portnode = ob;
else if ((ob->type >= FIRSTPIN) && (ob->node == i))
break;
}
if ((ob == NULL) && (portnode != NULL)) {
/* Port became disconnected when child was deleted */
portnode->node = -1;
}
}
}
FREE(checknodes);
return 1;
}
/* Remove all instances of class "class" from the database */
@ -513,6 +605,7 @@ int renameinstances(struct hashlist *p, int file)
}
}
}
return 1;
}
void InstanceRename(char *from, char *to, int file)
@ -535,9 +628,10 @@ int freeprop(struct hashlist *p)
struct property *prop;
prop = (struct property *)(p->ptr);
if (prop->type == PROP_STRING)
if (prop->type == PROP_STRING) {
if (prop->pdefault.string != NULL)
FREE(prop->pdefault.string);
}
else if (prop->type == PROP_EXPRESSION) {
struct tokstack *stackptr, *nptr;
stackptr = prop->pdefault.stack;
@ -556,61 +650,65 @@ int freeprop(struct hashlist *p)
void CellDelete(char *name, int fnum)
{
/* delete all the contents of cell 'name', and remove 'name' from
the cell hash table. NOTE: this procedure does not care or check
if 'name' has been instanced anywhere. It is assumed that if this
is the case, the user will (quickly) define a new cell of that name.
*/
struct objlist *ob, *obnext;
struct nlist *tp;
/* delete all the contents of cell 'name', and remove 'name' from
the cell hash table. NOTE: this procedure does not care or check
if 'name' has been instanced anywhere. It is assumed that if this
is the case, the user will (quickly) define a new cell of that name.
*/
struct objlist *ob, *obnext;
struct nlist *tp;
tp = LookupCellFile(name, fnum);
if (tp == NULL) {
Printf ("No cell '%s' found.\n", name);
return;
}
tp = LookupCellFile(name, fnum);
if (tp == NULL) {
Printf ("No cell '%s' found.\n", name);
return;
}
HashIntDelete(name, fnum, &cell_dict);
/* now make sure that we free all the fields of the nlist struct */
if (tp->name != NULL) FREE(tp->name);
HashKill(&(tp->objdict));
HashKill(&(tp->instdict));
RecurseHashTable(&(tp->propdict), freeprop);
HashKill(&(tp->propdict));
FreeNodeNames(tp);
ob = tp->cell;
while (ob != NULL) {
obnext = ob->next;
FreeObject (ob);
ob = obnext;
}
HashIntDelete(name, fnum, &cell_dict);
/* now make sure that we free all the fields of the nlist struct */
if (tp->name != NULL) FREE(tp->name);
HashKill(&(tp->objdict));
HashKill(&(tp->instdict));
RecurseHashTable(&(tp->propdict), freeprop);
HashKill(&(tp->propdict));
FreeNodeNames(tp);
ob = tp->cell;
while (ob != NULL) {
obnext = ob->next;
FreeObject (ob);
ob = obnext;
}
}
static int PrintCellHashTableElement(struct hashlist *p)
{
struct nlist *ptr;
struct nlist *ptr;
ptr = (struct nlist *)(p->ptr);
if ((TopFile >= 0) && (ptr->file != TopFile)) return 1;
ptr = (struct nlist *)(p->ptr);
if ((TopFile >= 0) && (ptr->file != TopFile)) return 1;
if (ptr->class != CLASS_SUBCKT) {
/* only print primitive cells if Debug is enabled */
if (Debug == 1) Printf("Cell: %s (instanced %d times); Primitive\n",
if ((ptr->class != CLASS_SUBCKT) && (ptr->class != CLASS_MODULE)) {
/* only print primitive cells if Debug is enabled */
if (Debug == 1) Printf("Cell: %s (instanced %d times); Primitive\n",
ptr->name, ptr->number);
else if (Debug == 3) { /* list */
Tcl_AppendElement(netgeninterp, ptr->name);
}
}
else if ((Debug == 2) || (Debug == 3)) { /* list only */
else if (Debug == 3) { /* list */
#ifdef TCL_NETGEN
Tcl_AppendElement(netgeninterp, ptr->name);
Tcl_AppendElement(netgeninterp, ptr->name);
#else
Printf("%s ", ptr->name);
Printf("%s ", ptr->name);
#endif
}
else
Printf("Cell: %s (instanced %d times)\n",ptr->name,ptr->number);
return(1);
}
}
else if ((Debug == 2) || (Debug == 3)) { /* list only */
#ifdef TCL_NETGEN
Tcl_AppendElement(netgeninterp, ptr->name);
#else
Printf("%s ", ptr->name);
#endif
}
else
Printf("Cell: %s (instanced %d times)\n", ptr->name, ptr->number);
return(1);
}
/* Print the contents of the cell hash table. */
@ -619,65 +717,65 @@ static int PrintCellHashTableElement(struct hashlist *p)
void PrintCellHashTable(int full, int filenum)
{
int total, bins;
int OldDebug;
int total, bins;
int OldDebug;
if ((filenum == -1) && (Circuit1 != NULL) && (Circuit2 != NULL)) {
if ((filenum == -1) && (Circuit1 != NULL) && (Circuit2 != NULL)) {
PrintCellHashTable(full, Circuit1->file);
PrintCellHashTable(full, Circuit2->file);
return;
}
}
TopFile = filenum;
TopFile = filenum;
bins = RecurseHashTable(&cell_dict, CountHashTableBinsUsed);
total = RecurseHashTable(&cell_dict, CountHashTableEntries);
if (full < 2)
Printf("Hash table: %d of %d bins used; %d cells total (%.2f per bin)\n",
bins = RecurseHashTable(&cell_dict, CountHashTableBinsUsed);
total = RecurseHashTable(&cell_dict, CountHashTableEntries);
if (full < 2)
Printf("Hash table: %d of %d bins used; %d cells total (%.2f per bin)\n",
bins, CELLHASHSIZE, total, (bins == 0) ? 0 :
(float)((float)total / (float)bins));
OldDebug = Debug;
Debug = full;
RecurseHashTable(&cell_dict, PrintCellHashTableElement);
Debug = OldDebug;
OldDebug = Debug;
Debug = full;
RecurseHashTable(&cell_dict, PrintCellHashTableElement);
Debug = OldDebug;
#ifndef TCL_NETGEN
if (full >= 2) Printf("\n");
if (full >= 2) Printf("\n");
#endif
}
struct nlist *FirstCell(void)
{
return((struct nlist *)HashFirst(&cell_dict));
return((struct nlist *)HashFirst(&cell_dict));
}
struct nlist *NextCell(void)
{
return((struct nlist *)HashNext(&cell_dict));
return((struct nlist *)HashNext(&cell_dict));
}
static int ClearDumpedElement(struct hashlist *np)
{
struct nlist *p;
struct nlist *p;
p = (struct nlist *)(np->ptr);
p->dumped = 0;
return(1);
p = (struct nlist *)(np->ptr);
p->dumped = 0;
return(1);
}
void ClearDumpedList(void)
{
RecurseHashTable(&cell_dict, ClearDumpedElement);
RecurseHashTable(&cell_dict, ClearDumpedElement);
}
int RecurseCellHashTable(int (*foo)(struct hashlist *np))
{
return RecurseHashTable(&cell_dict, foo);
return RecurseHashTable(&cell_dict, foo);
}
int RecurseCellFileHashTable(int (*foo)(struct hashlist *, int), int value)
{
return RecurseHashTableValue(&cell_dict, foo, value);
return RecurseHashTableValue(&cell_dict, foo, value);
}
/* Yet another version, passing one parameter that is a pointer */
@ -685,14 +783,14 @@ int RecurseCellFileHashTable(int (*foo)(struct hashlist *, int), int value)
struct nlist *RecurseCellHashTable2(struct nlist *(*foo)(struct hashlist *,
void *), void *pointer)
{
return RecurseHashTablePointer(&cell_dict, foo, pointer);
return RecurseHashTablePointer(&cell_dict, foo, pointer);
}
/************************** WILD-CARD STUFF *******************************/
char *FixTemplate(char *t)
{
char buffer[200];
char buffer[MAX_STR_LEN];
char *rstr;
int i,j;
int InsideBrace;
@ -971,6 +1069,7 @@ struct objlist *CopyObjList(struct objlist *oldlist, unsigned char doforall)
newob->model.class = NULL;
else
newob->model.class = strsave(tmp->model.class);
newob->flags = tmp->flags;
newob->instance.name = (tmp->instance.name) ?
strsave(tmp->instance.name) : NULL;
}
@ -1108,13 +1207,17 @@ void FreeObjectAndHash(struct objlist *ob, struct nlist *ptr)
/*************** GENERAL UTILITIES ****************************/
int NumberOfPorts(char *cellname)
int NumberOfPorts(char *cellname, int file)
{
struct nlist *tp;
struct objlist *ob;
int ports;
tp = LookupCell(cellname);
if (file == -1)
tp = LookupCell(cellname);
else
tp = LookupCellFile(cellname, file);
if (tp == NULL) return(0);
ports = 0;
for (ob = tp->cell; ob != NULL; ob = ob->next)
@ -1198,7 +1301,7 @@ static char *OldNodeName(struct nlist *tp, int node)
struct objlist *firstuniqueglobal;
struct objlist *firstglobal;
struct objlist *firstpin;
static char StrBuffer[100];
static char StrBuffer[MAX_STR_LEN];
#if 0
/* make second pass, looking for ports */

View File

@ -28,6 +28,8 @@
#define PROXY (0) /* Used in model.port record of ports */
#define NO_CONNECT 1 /* Use in object list to flag an isolated net */
/* Lists of device properties. Order is defined at the time of */
/* the cell definition; values are sorted at the time instances */
/* are read. */
@ -133,6 +135,7 @@ struct property {
unsigned char idx; /* index into valuelist */
unsigned char type; /* string, integer, double, value, expression */
unsigned char merge; /* how property changes when devices are merged */
char *pin; /* associated pin (or NULL if not associated) */
union {
char *string;
double dval;
@ -162,6 +165,7 @@ struct objlist {
/* (string) value of property for properties */
struct valuelist *props; /* Property record */
} instance;
unsigned char flags; /* Used by NODE type to flag isolated net */
int node; /* the electrical node number of the port/node/pin */
struct objlist *next;
};
@ -192,9 +196,8 @@ struct Permutation {
struct Permutation *next;
};
#define OBJHASHSIZE 997 /* the size of the object and instance hash lists */
#define OBJHASHSIZE 42073 /* the size of the object and instance hash lists */
/* prime numbers are good choices as hash sizes */
/* 101 is a good number for IBMPC */
/* cell definition for hash table */
/* NOTE: "file" must come first for the hash matching by name and file */
@ -204,7 +207,7 @@ struct nlist {
char *name;
int number; /* number of instances defined */
int dumped; /* instance count, and general-purpose marker */
unsigned char flags;
unsigned short flags;
unsigned char class;
unsigned long classhash; /* randomized hash value for cell class */
struct Permutation *permutes; /* list of permuting pins */
@ -220,17 +223,18 @@ struct nlist {
/* Defined nlist structure flags */
#define CELL_MATCHED 0x01 /* cell matched to another */
#define CELL_NOCASE 0x02 /* cell is case-insensitive (e.g., SPICE) */
#define CELL_TOP 0x04 /* cell is a top-level cell */
#define CELL_PLACEHOLDER 0x08 /* cell is a placeholder cell */
#define CELL_PROPSMATCHED 0x10 /* properties matched to matching cell */
#define CELL_DUPLICATE 0x20 /* cell has a duplicate */
#define CELL_MATCHED 0x001 /* cell matched to another */
#define CELL_NOCASE 0x002 /* cell is case-insensitive (e.g., SPICE) */
#define CELL_TOP 0x004 /* cell is a top-level cell */
#define CELL_PLACEHOLDER 0x008 /* cell is a placeholder cell */
#define CELL_PROPSMATCHED 0x010 /* properties matched to matching cell */
#define CELL_DUPLICATE 0x020 /* cell has a duplicate */
#define CELL_VERILOG 0x040 /* cell is verilog module */
/* Flags for combination allowances and prohibitions */
#define COMB_SERIES 0x40
#define COMB_NO_PARALLEL 0x80
#define COMB_SERIES 0x100
#define COMB_NO_PARALLEL 0x200
extern struct nlist *CurrentCell;
extern struct objlist *CurrentTail;
@ -242,7 +246,7 @@ extern void FreeObjectAndHash(struct objlist *ob, struct nlist *ptr);
extern void FreePorts(char *cellname);
extern struct IgnoreList *ClassIgnore;
extern int NumberOfPorts(char *cellname);
extern int NumberOfPorts(char *cellname, int file);
extern struct objlist *InstanceNumber(struct nlist *tp, int inst);
extern struct objlist *List(char *list_template);
@ -305,11 +309,26 @@ extern int match(char *, char *);
extern int matchnocase(char *, char *);
extern int matchfile(char *, char *, int, int);
extern int matchfilenocase(char *, char *, int, int);
extern int is_delimiter(char);
extern char *get_array_delimiter(char *, char *);
extern void GarbageCollect(void);
extern void InitGarbageCollection(void);
extern void AddToGarbageList(struct objlist *head);
extern void DeleteProperties(struct keyvalue **topptr);
extern void AddProperty(struct keyvalue **topptr, char *key, char *value);
extern void AddScaledProperty(struct keyvalue **topptr, char *key, char *value, double scale);
extern void DeleteProperties(struct keyvalue **topptr);
extern struct objlist *LinkProperties(char *model, struct keyvalue *topptr);
extern void ClassDelete(char *class, int file);
extern void RemoveShorted(char *class, int file);
extern void CellRehash(char *name, char *newname, int file);
/* defined in netgen.c */
extern int ConvertStringToInteger(char *string, int *ival);
#ifdef HAVE_MALLINFO
void PrintMemoryStats(void);
#endif

View File

@ -511,8 +511,8 @@ int OpenEmbeddingFile(char *cellname, char *filename)
/* returns 1 if OK */
{
struct nlist *tp;
char outfilename[200];
char logfilename[200];
char outfilename[MAX_STR_LEN];
char logfilename[MAX_STR_LEN];
tp = LookupCell(cellname);
if (tp == NULL) {
@ -783,7 +783,7 @@ void SetupArray(char *prompt1, char *prompt2, char *prompt3, int *data,
void (*proc)(void))
{
int i, oldfanout;
char name[100];
char name[MAX_STR_LEN];
Printf(prompt1);
for (i = 1; i <= MAX_TREE_DEPTH; i++)
@ -792,7 +792,7 @@ void SetupArray(char *prompt1, char *prompt2, char *prompt3, int *data,
oldfanout = 1;
for (i = 1; i <= MAX_TREE_DEPTH; i++) {
char prompt[100];
char prompt[MAX_STR_LEN];
int newfanout;
sprintf(prompt, prompt2, i);
promptstring(prompt, name);
@ -822,7 +822,7 @@ void SetupArrayFromString(char *prompt1, char *prompt3, int *data,
void (*proc)(void), char *text)
{
int i, oldfanout, newfanout;
char string[100];
char string[MAX_STR_LEN];
char *ch;
char *endch;
@ -929,7 +929,7 @@ void ToggleDebug(void)
void DescribeCell(char *name, int detail)
{
Printf("Cell: %s contains %d instances, %d nodes and %d ports\n", name,
NumberOfInstances(name), RenumberNodes(name), NumberOfPorts(name));
NumberOfInstances(name), RenumberNodes(name), NumberOfPorts(name, -1));
PrintEmbeddingTree(stdout,name,detail);
}
@ -962,7 +962,7 @@ void ProtoPrintParameters(void)
void PROTOCHIP(void)
/* a simple command interpreter to manage embedding/routing */
{
char name[100];
char name[MAX_STR_LEN];
char ch;
InitializeFanout();
@ -1136,7 +1136,7 @@ void PROTOCHIP(void)
oldfanout = 1;
for (i = 1; i <= MAX_TREE_DEPTH; i++) {
char prompt[100];
char prompt[MAX_STR_LEN];
int newfanout;
sprintf(prompt,"Fanout for level %d (0 to quit): ",i);
promptstring(prompt, name);
@ -1168,7 +1168,7 @@ void PROTOCHIP(void)
oldfanout = 1;
for (i = 1; i <= MAX_TREE_DEPTH; i++) {
char prompt[100];
char prompt[MAX_STR_LEN];
int newfanout;
sprintf(prompt,"Common nodes for level %d (0 to quit): ",i);
promptstring(prompt, name);
@ -1200,7 +1200,7 @@ void PROTOCHIP(void)
oldfanout = 1;
for (i = 1; i <= MAX_TREE_DEPTH; i++) {
char prompt[100];
char prompt[MAX_STR_LEN];
int newfanout;
sprintf(prompt,"Used leaves for level %d (0 to quit): ",i);
promptstring(prompt, name);

View File

@ -37,7 +37,7 @@ extern int ColumnBase;
struct filestr {
FILE *f;
char buffer[200];
char buffer[MAX_STR_LEN];
int wrap; /* column to wrap around in, or 0 if no wrap */
} file_buffers[MAXFILES];
@ -107,7 +107,7 @@ void Fprintf(FILE *f, char *format, ...)
{
va_list ap;
int FileIndex;
char tmpstr[200];
char tmpstr[MAX_STR_LEN];
int bufferlongenough;
int linewrapexceeded;
@ -203,7 +203,7 @@ void Printf(char *format, ...)
void Printf(char *format, ...)
{
va_list ap;
char tmpstr[200];
char tmpstr[MAX_STR_LEN];
va_start(ap, format);
vsprintf(tmpstr, format, ap);

View File

@ -52,7 +52,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
/*************************************************************************/
static int SuppressPrompts = 0;
static char InputLine[200];
static char InputLine[MAX_STR_LEN];
void typeahead(char *str)
{
@ -73,7 +73,7 @@ but reads from 'promptstring_infile' if nec. */
/* If interactive, puts out 'prompt' */
{
char *nexttok;
char tmpstr[200];
char tmpstr[MAX_STR_LEN];
int echo;
if (promptstring_infile == NULL)
@ -319,7 +319,7 @@ void Fanout(char *cell, char *node, int filter)
while (ob != NULL) {
char *obname = ob->name;
if (*obname == '/') obname++;
if (ob->node == nodenum)
if (ob->node == nodenum) {
if (filter == ALLOBJECTS) {
Printf(" %s (", obname);
PrintObjectType(ob->type);
@ -331,6 +331,7 @@ void Fanout(char *cell, char *node, int filter)
else if (ob->type == filter) {
Printf(" %s\n", obname);
}
}
ob = ob->next;
}
}
@ -801,9 +802,19 @@ void DescribeInstance(char *name, int file)
{
if (ob->node > nodemax) nodemax = ob->node;
else if ((ob->node == -1) && (ob->model.port != PROXY)) {
if (disconnectednodes == 0) Fprintf(stderr, "\n");
disconnectednodes++;
Fprintf(stderr, "Cell %s disconnected node: %s\n", tp->name, ob->name);
/* All black-box modules and placeholders by definition have all */
/* disconnected pins, so don't report those. */
if ((!(tp->flags & CELL_PLACEHOLDER)) && (tp->class != CLASS_MODULE)) {
// if (disconnectednodes == 0) Fprintf(stderr, "\n");
disconnectednodes++;
/* Don't report on ports marked "port_match_error", which is just confusing. */
if (strcmp(ob->name, "port_match_error")) {
Fprintf(stderr, "Cell %s (%d) disconnected node: %s\n",
tp->name, tp->file, ob->name);
}
}
}
}
instlist = (unsigned char *) CALLOC((nodemax + 1), sizeof(unsigned char));
@ -900,7 +911,7 @@ void PrintLeavesInCell(char *cellname, int filenum)
np->dumped = 1;
if (np->class != CLASS_SUBCKT) {
Printf("%s; %d ports; Primitive.\n", cellname, NumberOfPorts(cellname));
Printf("%s; %d ports; Primitive.\n", cellname, NumberOfPorts(cellname, filenum));
return;
}
@ -913,7 +924,7 @@ void PrintLeavesInCell(char *cellname, int filenum)
am_a_leaf = 0;
}
if (am_a_leaf) Printf("%s; %d ports\n", cellname, NumberOfPorts(cellname));
if (am_a_leaf) Printf("%s; %d ports\n", cellname, NumberOfPorts(cellname, filenum));
return;
}
@ -923,7 +934,7 @@ static int PrintLeavesInCellHash(struct hashlist *p)
struct nlist *ptr;
ptr = (struct nlist *)(p->ptr);
if ((ptr->class == CLASS_SUBCKT)) PrintLeavesInCell(ptr->name, ptr->file);
if (ptr->class == CLASS_SUBCKT) PrintLeavesInCell(ptr->name, ptr->file);
return(0);
}
@ -949,8 +960,8 @@ void Query(void)
{
/* little interactive debugger */
char reply;
char repstr[100];
char repstr2[100];
char repstr[MAX_STR_LEN];
char repstr2[MAX_STR_LEN];
float StartTime; /* for elapsed CPU times */
int Timing; /* if true, print times of each command */
int filenum = -1;
@ -1026,7 +1037,7 @@ void Query(void)
break;
case 'v':
promptstring("Write Verilog: circuit name: ", repstr);
VerilogModule(repstr, filenum, "");
VerilogTop(repstr, filenum, "");
break;
case 'E':
promptstring("Write ESACAP: circuit name: ", repstr);
@ -1063,7 +1074,7 @@ void Query(void)
ActelLib();
break;
case 'S':
promptstring("Read SPICE (.ckt) file? ", repstr);
promptstring("Read SPICE (.spice) file? ", repstr);
ReadSpice(repstr, &filenum);
break;
case 'V':

View File

@ -21,11 +21,15 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
#include "config.h"
#include <stdio.h>
#include <string.h>
#include <strings.h>
#include <ctype.h>
#if 0
#include <stdarg.h> /* what about varargs, like in pdutils.c ??? */
#endif
#include <stdlib.h> /* for calloc(), free(), getenv() */
#include <ctype.h> /* for toupper(), isascii() */
#ifndef IBMPC
#include <sys/types.h> /* for getpwnam() tilde expansion */
#include <pwd.h>
@ -40,6 +44,9 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
#include "objlist.h"
#include "netfile.h"
#include "print.h"
#include "query.h"
#include "objlist.h"
#include "netcmp.h"
// Global storage for parameters from .PARAM
struct hashdict spiceparams;
@ -189,7 +196,7 @@ void SpiceSubCell(struct nlist *tp, int IsSubCell)
if (ob->type == PROPERTY) {
struct valuelist *vl;
int i;
for (i == 0;; i++) {
for (i = 0;; i++) {
vl = &(ob->instance.props[i]);
if (vl->type == PROP_ENDLIST) break;
else if (vl->type == PROP_VALUE) {
@ -209,7 +216,7 @@ void SpiceSubCell(struct nlist *tp, int IsSubCell)
if (ob->type == PROPERTY) {
struct valuelist *vl;
int i;
for (i == 0;; i++) {
for (i = 0;; i++) {
vl = &(ob->instance.props[i]);
if (vl->type == PROP_ENDLIST) break;
else if (vl->type == PROP_VALUE) {
@ -229,7 +236,7 @@ void SpiceSubCell(struct nlist *tp, int IsSubCell)
if (ob->type == PROPERTY) {
struct valuelist *vl;
int i;
for (i == 0;; i++) {
for (i = 0;; i++) {
vl = &(ob->instance.props[i]);
if (vl->type == PROP_ENDLIST) break;
else if (vl->type == PROP_VALUE) {
@ -392,7 +399,7 @@ int renamepins(struct hashlist *p, int file)
ptr = (struct nlist *)(p->ptr);
if (ptr->file != file)
return 1;
return 0;
for (ob = ptr->cell; ob != NULL; ob = ob->next) {
if (ob->type == FIRSTPIN) {
@ -419,6 +426,7 @@ int renamepins(struct hashlist *p, int file)
}
}
}
return 1;
}
/* If any pins are marked unconnected, see if there are */
@ -473,15 +481,6 @@ void CleanupSubcell() {
SetClass(CLASS_MODULE);
}
/*------------------------------------------------------*/
/* Structure for stacking nested subcircuit definitions */
/*------------------------------------------------------*/
struct cellstack {
char *cellname;
struct cellstack *next;
};
/*------------------------------------------------------*/
/* Push a subcircuit name onto the stack */
/*------------------------------------------------------*/
@ -524,21 +523,27 @@ void ReadSpiceFile(char *fname, int filenum, struct cellstack **CellStackPtr,
int warnings = 0, update = 0, hasports = 0;
char *eqptr, devtype, in_subckt;
struct keyvalue *kvlist = NULL;
char inst[256], model[256], instname[256];
struct nlist *tp;
char inst[MAX_STR_LEN], model[MAX_STR_LEN], instname[MAX_STR_LEN];
struct nlist *tp, *tpsave;
struct objlist *parent, *sobj, *nobj, *lobj, *pobj;
inst[255] = '\0';
model[255] = '\0';
instname[255] = '\0';
inst[MAX_STR_LEN-1] = '\0';
model[MAX_STR_LEN-1] = '\0';
instname[MAX_STR_LEN-1] = '\0';
in_subckt = (char)0;
while (!EndParseFile()) {
SkipTok(NULL); /* get the next token */
if ((EndParseFile()) && (nexttok == NULL)) break;
if (nexttok == NULL) break;
if (nexttok[0] == '*') SkipNewLine(NULL);
/* Handle comment lines. Note that some variants of CDL format
* use "*." for information that is transparent to SPICE simulators.
* Handle "*.GLOBAL" entries. All others are ignored.
*/
if ((nexttok[0] == '*') && (!matchnocase(nexttok, "*.GLOBAL")))
SkipNewLine(NULL);
else if (matchnocase(nexttok, ".SUBCKT")) {
SpiceTokNoNewline();
@ -561,8 +566,9 @@ void ReadSpiceFile(char *fname, int filenum, struct cellstack **CellStackPtr,
/* Check for existence of the cell. We may need to rename it. */
snprintf(model, 99, "%s", nexttok);
snprintf(model, MAX_STR_LEN-1, "%s", nexttok);
tp = LookupCellFile(nexttok, filenum);
tpsave = NULL;
/* Check for name conflict with duplicate cell names */
/* This may mean that the cell was used before it was */
@ -601,11 +607,46 @@ void ReadSpiceFile(char *fname, int filenum, struct cellstack **CellStackPtr,
tp = LookupCellFile(nexttok, filenum);
}
else if (tp != NULL) { /* Make a new definition for an empty cell */
FreePorts(nexttok);
CellDelete(nexttok, filenum); /* This removes any PLACEHOLDER flag */
CellDef(model, filenum);
tp = LookupCellFile(model, filenum);
update = 1; /* Will need to update existing instances */
/* Handle issue with SPICE read after verilog, where a placeholder
* was created from the verilog. (1) If the pin names are "1", "2",
* "3", then this is a SPICE placeholder, and just remove the CellDef
* and re-create it. Otherwise, create new cell "_PLACEHOLDER_".
* (2) After encountering .ends, run MatchPins between the two cells.
* (3) delete the original cell and rename the new cell.
*/
int i = 1;
char pname[10];
for (pobj = tp->cell; pobj && pobj->type == PORT; pobj = pobj->next) {
sprintf(pname, "%d", i);
if (!matchnocase(pobj->name, pname)) break;
i++;
}
if ((pobj == NULL) || (pobj->type != PORT)) {
/* This is a SPICE placeholder created because the cell was instanced
* before it was defined. However, the pins can be assumed to be in
* the correct order, and pin reordering does not need to be done.
*/
FreePorts(nexttok);
CellDelete(nexttok, filenum); /* This removes any PLACEHOLDER flag */
CellDef(model, filenum);
tp = LookupCellFile(model, filenum);
update = 1; /* Will need to update existing instances */
}
else {
/* This is (probably) a verilog placeholder created because the
* verilog was read before the (SPICE) definitions. The verilog
* netlist should have named the pins of the parent cell. However,
* there is no guarantee the order of pins is correct. The MatchPins()
* routine from netcmp.c can be used here to match the cell against
* the placeholder, and reorder the pins in all instances to match.
* Note that we cannot just reorder the SPICE pins to match the
* verilog order, because there may be other SPICE netlists which
* instance the cell with the correct SPICE port order.
*/
tpsave = tp;
CellDef("_PLACEHOLDER_", filenum);
tp = LookupCellFile("_PLACEHOLDER_", filenum);
}
}
else if (tp == NULL) { /* Completely new cell, no name conflict */
CellDef(model, filenum);
@ -697,6 +738,38 @@ skip_ends:
if (*CellStackPtr) PopStack(CellStackPtr);
if (*CellStackPtr) ReopenCellDef((*CellStackPtr)->cellname, filenum);
SkipNewLine(NULL);
if (tpsave != NULL) {
struct nlist *tpplace;
char *savename;
/* Handle a placeholder from a verilog file that has been replaced
* by a netlist with pins in a different order. The pins need to
* be matched, corrected in the original cell and all instances,
* and the new cell deleted.
*/
Printf("Verilog placeholder %s replaced by SPICE definition\n",
tpsave->name);
tpplace = LookupCellFile("_PLACEHOLDER_", filenum);
/* MatchPins is part of netcmp and normally Circuit2 is the
* circuit being matched, so set Circuit2 to the original
* verilog black-box cell, and MatchPins() will force its
* pins to be rearranged to match the SPICE definition just
* read.
*/
Circuit2 = tpsave;
MatchPins(tpplace, tpsave, 0);
savename = strsave(tpsave->name);
/* Now the original verilog black-box cell can be removed */
FreePorts(savename);
CellDelete(savename, filenum);
/* And _PLACEHOLDER_ is renamed to the original name of the cell. */
CellRehash("_PLACEHOLDER_", savename, filenum);
tpsave = NULL;
Circuit2 = NULL;
FREE(savename);
}
}
else if (matchnocase(nexttok, ".MODEL")) {
unsigned char class = CLASS_SUBCKT;
@ -709,7 +782,7 @@ skip_ends:
SpiceTokNoNewline();
if (nexttok == NULL) continue; /* Ignore if no model name */
snprintf(model, 99, "%s", nexttok);
snprintf(model, MAX_STR_LEN-1, "%s", nexttok);
SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
@ -758,7 +831,10 @@ skip_ends:
// Handle some commonly-used cards
else if (matchnocase(nexttok, ".GLOBAL")) {
/* .GLOBAL and *.GLOBAL. Note that *.GLOBAL is excepted from comment-line
* handling, above, so any line starting with '*' is "*.GLOBAL".
*/
else if (matchnocase(nexttok, ".GLOBAL") || (nexttok[0] == '*')) {
while (nexttok != NULL) {
int numnodes = 0;
SpiceTokNoNewline();
@ -874,6 +950,17 @@ skip_ends:
}
}
/* Ignore anything in a .CONTROL ... .ENDC block */
else if (matchnocase(nexttok, ".CONTROL")) {
while (1) {
SpiceSkipNewLine();
SkipTok(NULL);
if (EndParseFile()) break;
if (matchnocase(nexttok, ".ENDC"))
break;
}
}
// Blackbox (library) mode---parse only subcircuits and models;
// ignore all components.
@ -882,29 +969,29 @@ skip_ends:
}
else if (toupper(nexttok[0]) == 'Q') {
char emitter[100], base[100], collector[100];
emitter[99] = '\0';
base[99] = '\0';
collector[99] = '\0';
char emitter[MAX_STR_LEN], base[MAX_STR_LEN], collector[MAX_STR_LEN];
emitter[MAX_STR_LEN-1] = '\0';
base[MAX_STR_LEN-1] = '\0';
collector[MAX_STR_LEN-1] = '\0';
if (!(*CellStackPtr)) {
CellDef(fname, filenum);
PushStack(fname, CellStackPtr);
}
strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline();
strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(collector, nexttok, 99); SpiceTokNoNewline();
strncpy(collector, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(base, nexttok, 99); SpiceTokNoNewline();
strncpy(base, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(emitter, nexttok, 99); SpiceTokNoNewline();
strncpy(emitter, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
/* make sure all the nodes exist */
if (LookupObject(collector, CurrentCell) == NULL) Node(collector);
if (LookupObject(base, CurrentCell) == NULL) Node(base);
if (LookupObject(emitter, CurrentCell) == NULL) Node(emitter);
/* Read the device model */
snprintf(model, 99, "%s", nexttok);
snprintf(model, MAX_STR_LEN-1, "%s", nexttok);
while (nexttok != NULL)
{
@ -935,30 +1022,30 @@ skip_ends:
goto baddevice;
}
snprintf(instname, 255, "%s%s", model, inst);
snprintf(instname, MAX_STR_LEN-1, "%s:%s", model, inst);
Cell(instname, model, collector, base, emitter);
pobj = LinkProperties(model, kvlist);
ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
DeleteProperties(&kvlist);
}
else if (toupper(nexttok[0]) == 'M') {
char drain[100], gate[100], source[100], bulk[100];
drain[99] = '\0';
gate[99] = '\0';
source[99] = '\0';
bulk[99] = '\0';
char drain[MAX_STR_LEN], gate[MAX_STR_LEN], source[MAX_STR_LEN], bulk[MAX_STR_LEN];
drain[MAX_STR_LEN-1] = '\0';
gate[MAX_STR_LEN-1] = '\0';
source[MAX_STR_LEN-1] = '\0';
bulk[MAX_STR_LEN-1] = '\0';
if (!(*CellStackPtr)) {
CellDef(fname, filenum);
PushStack(fname, CellStackPtr);
}
strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline();
strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(drain, nexttok, 99); SpiceTokNoNewline();
strncpy(drain, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(gate, nexttok, 99); SpiceTokNoNewline();
strncpy(gate, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(source, nexttok, 99); SpiceTokNoNewline();
strncpy(source, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
/* make sure all the nodes exist */
if (LookupObject(drain, CurrentCell) == NULL) Node(drain);
@ -966,11 +1053,11 @@ skip_ends:
if (LookupObject(source, CurrentCell) == NULL) Node(source);
/* handle the substrate node */
strncpy(bulk, nexttok, 99); SpiceTokNoNewline();
strncpy(bulk, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (LookupObject(bulk, CurrentCell) == NULL) Node(bulk);
/* Read the device model */
snprintf(model, 99, "%s", nexttok);
snprintf(model, MAX_STR_LEN-1, "%s", nexttok);
while (nexttok != NULL)
{
@ -1008,7 +1095,7 @@ skip_ends:
goto baddevice;
}
snprintf(instname, 255, "%s%s", model, inst);
snprintf(instname, MAX_STR_LEN-1, "%s:%s", model, inst);
Cell(instname, model, drain, gate, source, bulk);
pobj = LinkProperties(model, kvlist);
ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
@ -1022,19 +1109,19 @@ skip_ends:
SpiceSkipNewLine();
}
else {
char ctop[100], cbot[100];
ctop[99] = '\0';
cbot[99] = '\0';
char ctop[MAX_STR_LEN], cbot[MAX_STR_LEN];
ctop[MAX_STR_LEN-1] = '\0';
cbot[MAX_STR_LEN-1] = '\0';
if (!(*CellStackPtr)) {
CellDef(fname, filenum);
PushStack(fname, CellStackPtr);
}
strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline();
strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(ctop, nexttok, 99); SpiceTokNoNewline();
strncpy(ctop, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(cbot, nexttok, 99); SpiceTokNoNewline();
strncpy(cbot, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
/* make sure all the nodes exist */
if (LookupObject(ctop, CurrentCell) == NULL) Node(ctop);
@ -1053,7 +1140,7 @@ skip_ends:
model[0] = '\0';
if ((nexttok != NULL) && ((eqptr = strchr(nexttok, '=')) == NULL))
snprintf(model, 99, "%s", nexttok);
snprintf(model, MAX_STR_LEN-1, "%s", nexttok);
/* Any other device properties? */
while (nexttok != NULL)
@ -1066,7 +1153,7 @@ skip_ends:
}
else if (!strncmp(nexttok, "$[", 2)) {
// Support for CDL modeled capacitor format
snprintf(model, 99, "%s", nexttok + 2);
snprintf(model, MAX_STR_LEN-1, "%s", nexttok + 2);
if ((eqptr = strchr(model, ']')) != NULL)
*eqptr = '\0';
}
@ -1099,7 +1186,7 @@ skip_ends:
usemodel = 1;
}
snprintf(instname, 255, "%s%s", model, inst);
snprintf(instname, MAX_STR_LEN-1, "%s:%s", model, inst);
if (usemodel)
Cell(instname, model, ctop, cbot);
else
@ -1116,19 +1203,19 @@ skip_ends:
SpiceSkipNewLine();
}
else {
char rtop[100], rbot[100];
rtop[99] = '\0';
rbot[99] = '\0';
char rtop[MAX_STR_LEN], rbot[MAX_STR_LEN];
rtop[MAX_STR_LEN-1] = '\0';
rbot[MAX_STR_LEN-1] = '\0';
if (!(*CellStackPtr)) {
CellDef(fname, filenum);
PushStack(fname, CellStackPtr);
}
strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline();
strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(rtop, nexttok, 99); SpiceTokNoNewline();
strncpy(rtop, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(rbot, nexttok, 99); SpiceTokNoNewline();
strncpy(rbot, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
/* make sure all the nodes exist */
if (LookupObject(rtop, CurrentCell) == NULL) Node(rtop);
if (LookupObject(rbot, CurrentCell) == NULL) Node(rbot);
@ -1147,7 +1234,7 @@ skip_ends:
model[0] = '\0';
if ((nexttok != NULL) && ((eqptr = strchr(nexttok, '=')) == NULL))
snprintf(model, 99, "%s", nexttok);
snprintf(model, MAX_STR_LEN-1, "%s", nexttok);
/* Any other device properties? */
while (nexttok != NULL) {
@ -1159,7 +1246,7 @@ skip_ends:
}
else if (!strncmp(nexttok, "$[", 2)) {
// Support for CDL modeled resistor format
snprintf(model, 99, "%s", nexttok + 2);
snprintf(model, MAX_STR_LEN-1, "%s", nexttok + 2);
if ((eqptr = strchr(model, ']')) != NULL)
*eqptr = '\0';
}
@ -1184,7 +1271,7 @@ skip_ends:
else if (CountPorts(model, filenum) != 2) {
/* Modeled device: Make sure it has the right number of ports */
Fprintf(stderr, "Device \"%s\" has wrong number of ports for a "
"resistor.\n");
"resistor.\n", model);
goto baddevice;
}
usemodel = 1;
@ -1192,7 +1279,7 @@ skip_ends:
else
strcpy(model, "r"); /* Use default resistor model */
snprintf(instname, 255, "%s%s", model, inst);
snprintf(instname, MAX_STR_LEN-1, "%s:%s", model, inst);
if (usemodel)
Cell(instname, model, rtop, rbot);
else
@ -1203,25 +1290,25 @@ skip_ends:
}
}
else if (toupper(nexttok[0]) == 'D') { /* diode */
char cathode[100], anode[100];
cathode[99] = '\0';
anode[99] = '\0';
char cathode[MAX_STR_LEN], anode[MAX_STR_LEN];
cathode[MAX_STR_LEN-1] = '\0';
anode[MAX_STR_LEN-1] = '\0';
if (!(*CellStackPtr)) {
CellDef(fname, filenum);
PushStack(fname, CellStackPtr);
}
strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline();
strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(anode, nexttok, 99); SpiceTokNoNewline();
strncpy(anode, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(cathode, nexttok, 99); SpiceTokNoNewline();
strncpy(cathode, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
/* make sure all the nodes exist */
if (LookupObject(anode, CurrentCell) == NULL) Node(anode);
if (LookupObject(cathode, CurrentCell) == NULL) Node(cathode);
/* Read the device model */
snprintf(model, 99, "%s", nexttok);
snprintf(model, MAX_STR_LEN-1, "%s", nexttok);
while (nexttok != NULL)
{
@ -1250,7 +1337,7 @@ skip_ends:
Fprintf(stderr, "Device \"%s\" has wrong number of ports for a diode.\n");
goto baddevice;
}
snprintf(instname, 255, "%s%s", model, inst);
snprintf(instname, MAX_STR_LEN-1, "%s:%s", model, inst);
Cell(instname, model, anode, cathode);
pobj = LinkProperties(model, kvlist);
ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
@ -1263,25 +1350,25 @@ skip_ends:
SpiceSkipNewLine();
}
else {
char node1[100], node2[100], node3[100], node4[100];
node1[99] = '\0';
node2[99] = '\0';
node3[99] = '\0';
node4[99] = '\0';
char node1[MAX_STR_LEN], node2[MAX_STR_LEN], node3[MAX_STR_LEN], node4[MAX_STR_LEN];
node1[MAX_STR_LEN-1] = '\0';
node2[MAX_STR_LEN-1] = '\0';
node3[MAX_STR_LEN-1] = '\0';
node4[MAX_STR_LEN-1] = '\0';
if (!(*CellStackPtr)) {
CellDef(fname, filenum);
PushStack(fname, CellStackPtr);
}
strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline();
strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(node1, nexttok, 99); SpiceTokNoNewline();
strncpy(node1, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(node2, nexttok, 99); SpiceTokNoNewline();
strncpy(node2, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(node3, nexttok, 99); SpiceTokNoNewline();
strncpy(node3, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(node4, nexttok, 99); SpiceTokNoNewline();
strncpy(node4, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
/* make sure all the nodes exist */
if (LookupObject(node1, CurrentCell) == NULL) Node(node1);
if (LookupObject(node2, CurrentCell) == NULL) Node(node2);
@ -1293,7 +1380,7 @@ skip_ends:
model[0] = '\0';
if ((nexttok != NULL) && ((eqptr = strchr(nexttok, '=')) == NULL))
snprintf(model, 99, "%s", nexttok);
snprintf(model, MAX_STR_LEN-1, "%s", nexttok);
/* Any other device properties? */
while (nexttok != NULL) {
@ -1329,7 +1416,7 @@ skip_ends:
else
strcpy(model, "t"); /* Use default xline model */
snprintf(instname, 255, "%s%s", model, inst);
snprintf(instname, MAX_STR_LEN-1, "%s:%s", model, inst);
if (usemodel)
Cell(instname, model, node1, node2, node3, node4);
@ -1342,20 +1429,20 @@ skip_ends:
}
}
else if (toupper(nexttok[0]) == 'L') { /* inductor */
char end_a[100], end_b[100];
char end_a[MAX_STR_LEN], end_b[MAX_STR_LEN];
int usemodel = 0;
end_a[99] = '\0';
end_b[99] = '\0';
end_a[MAX_STR_LEN-1] = '\0';
end_b[MAX_STR_LEN-1] = '\0';
if (!(*CellStackPtr)) {
CellDef(fname, filenum);
PushStack(fname, CellStackPtr);
}
strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline();
strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(end_a, nexttok, 99); SpiceTokNoNewline();
strncpy(end_a, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(end_b, nexttok, 99); SpiceTokNoNewline();
strncpy(end_b, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
/* make sure all the nodes exist */
if (LookupObject(end_a, CurrentCell) == NULL) Node(end_a);
if (LookupObject(end_b, CurrentCell) == NULL) Node(end_b);
@ -1374,7 +1461,7 @@ skip_ends:
model[0] = '\0';
if ((nexttok != NULL) && ((eqptr = strchr(nexttok, '=')) == NULL))
snprintf(model, 99, "%s", nexttok);
snprintf(model, MAX_STR_LEN-1, "%s", nexttok);
/* Any other device properties? */
while (nexttok != NULL)
@ -1412,7 +1499,7 @@ skip_ends:
else
strcpy(model, "l"); /* Use default inductor model */
snprintf(instname, 255, "%s%s", model, inst);
snprintf(instname, MAX_STR_LEN-1, "%s:%s", model, inst);
if (usemodel)
Cell(instname, model, end_a, end_b);
else
@ -1426,25 +1513,38 @@ skip_ends:
/* black-box subcircuits (class MODULE): V, I, E */
else if (toupper(nexttok[0]) == 'V') { /* voltage source */
char pos[100], neg[100];
pos[99] = '\0';
neg[99] = '\0';
char pos[MAX_STR_LEN], neg[MAX_STR_LEN];
pos[MAX_STR_LEN-1] = '\0';
neg[MAX_STR_LEN-1] = '\0';
if (!(*CellStackPtr)) {
CellDef(fname, filenum);
PushStack(fname, CellStackPtr);
}
strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline();
strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(pos, nexttok, 99); SpiceTokNoNewline();
strncpy(pos, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(neg, nexttok, 99); SpiceTokNoNewline();
strncpy(neg, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
/* make sure all the nodes exist */
if (LookupObject(pos, CurrentCell) == NULL) Node(pos);
if (LookupObject(neg, CurrentCell) == NULL) Node(neg);
/* Any device properties? */
/* Get voltage value (if present); save as property "value" */
if (nexttok != NULL) {
if (matchnocase(nexttok, "DC")) {
SpiceTokNoNewline();
}
}
if (nexttok != NULL) {
if (StringIsValueOrExpression(nexttok)) {
AddProperty(&kvlist, "value", nexttok);
}
}
/* Any other device properties? */
while (nexttok != NULL)
{
SpiceTokNoNewline();
@ -1472,7 +1572,7 @@ skip_ends:
else if (CountPorts(model, filenum) != 2) {
/* Modeled device: Make sure it has the right number of ports */
Fprintf(stderr, "Device \"%s\" has wrong number of ports for a "
"voltage source.\n");
"voltage source.\n", inst);
goto baddevice;
}
Cell(instname, model, pos, neg);
@ -1481,19 +1581,19 @@ skip_ends:
DeleteProperties(&kvlist);
}
else if (toupper(nexttok[0]) == 'I') { /* current source */
char pos[100], neg[100];
pos[99] = '\0';
neg[99] = '\0';
char pos[MAX_STR_LEN], neg[MAX_STR_LEN];
pos[MAX_STR_LEN-1] = '\0';
neg[MAX_STR_LEN-1] = '\0';
if (!(*CellStackPtr)) {
CellDef(fname, filenum);
PushStack(fname, CellStackPtr);
}
strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline();
strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(pos, nexttok, 99); SpiceTokNoNewline();
strncpy(pos, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(neg, nexttok, 99); SpiceTokNoNewline();
strncpy(neg, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
/* make sure all the nodes exist */
if (LookupObject(pos, CurrentCell) == NULL) Node(pos);
if (LookupObject(neg, CurrentCell) == NULL) Node(neg);
@ -1535,25 +1635,25 @@ skip_ends:
DeleteProperties(&kvlist);
}
else if (toupper(nexttok[0]) == 'E') { /* controlled voltage source */
char pos[100], neg[100], ctrlp[100], ctrln[100];
pos[99] = '\0';
neg[99] = '\0';
ctrlp[99] = '\0';
ctrln[99] = '\0';
char pos[MAX_STR_LEN], neg[MAX_STR_LEN], ctrlp[MAX_STR_LEN], ctrln[MAX_STR_LEN];
pos[MAX_STR_LEN-1] = '\0';
neg[MAX_STR_LEN-1] = '\0';
ctrlp[MAX_STR_LEN-1] = '\0';
ctrln[MAX_STR_LEN-1] = '\0';
if (!(*CellStackPtr)) {
CellDef(fname, filenum);
PushStack(fname, CellStackPtr);
}
strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline();
strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(pos, nexttok, 99); SpiceTokNoNewline();
strncpy(pos, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(neg, nexttok, 99); SpiceTokNoNewline();
strncpy(neg, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(ctrlp, nexttok, 99); SpiceTokNoNewline();
strncpy(ctrlp, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
if (nexttok == NULL) goto baddevice;
strncpy(ctrln, nexttok, 99); SpiceTokNoNewline();
strncpy(ctrln, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
/* make sure all the nodes exist */
if (LookupObject(pos, CurrentCell) == NULL) Node(pos);
@ -1601,11 +1701,11 @@ skip_ends:
}
else if (toupper(nexttok[0]) == 'X') { /* subcircuit instances */
char instancename[100], subcktname[100];
char instancename[MAX_STR_LEN], subcktname[MAX_STR_LEN];
int itype, in_props;
instancename[99] = '\0';
subcktname[99] = '\0';
instancename[MAX_STR_LEN-1] = '\0';
subcktname[MAX_STR_LEN-1] = '\0';
struct portelement {
char *name;
@ -1615,8 +1715,8 @@ skip_ends:
struct portelement *head, *tail, *scan, *scannext;
struct objlist *obptr;
snprintf(instancename, 99, "%s", nexttok + 1);
strncpy(instancename, nexttok + 1, 99);
snprintf(instancename, MAX_STR_LEN-1, "%s", nexttok + 1);
strncpy(instancename, nexttok + 1, MAX_STR_LEN-1);
if (!(*CellStackPtr)) {
CellDef(fname, filenum);
PushStack(fname, CellStackPtr);
@ -1683,10 +1783,19 @@ skip_ends:
if (scan->next != NULL) scan = scan->next;
tail->next = NULL;
/* Check for class defined inside itself (self-referential loop) */
if (!strcasecmp(model, scan->name)) {
Fprintf(stderr, "Fatal: Class \"%s\" is instanced inside of itself!\n",
scan->name);
InputParseError(stderr);
return;
}
/* Check for ignored class */
if ((itype = IsIgnored(subcktname, filenum)) == IGNORE_CLASS) {
Printf("Class '%s' instanced in input but is being ignored.\n", model);
if ((itype = IsIgnored(scan->name, filenum)) == IGNORE_CLASS) {
Printf("Class '%s' instanced in input but is being ignored.\n", scan->name);
return;
}
@ -1701,7 +1810,7 @@ skip_ends:
break;
}
if (shorted == (unsigned char)1) {
Printf("Instance of '%s' is shorted, ignoring.\n", subcktname);
Printf("Instance of '%s' is shorted, ignoring.\n", scan->name);
while (head) {
p = head->next;
FREE(head);
@ -1724,14 +1833,14 @@ skip_ends:
/* names. */
if (strncmp(instancename, scan->name, strlen(scan->name))) {
snprintf(subcktname, 99, "%s%s", scan->name, instancename);
snprintf(subcktname, MAX_STR_LEN-1, "%s:%s", scan->name, instancename);
strcpy(instancename, subcktname);
}
else {
snprintf(subcktname, 99, "/%s", instancename);
snprintf(subcktname, MAX_STR_LEN-1, "/%s", instancename);
strcpy(instancename, subcktname);
}
snprintf(subcktname, 99, "%s", scan->name);
snprintf(subcktname, MAX_STR_LEN-1, "%s", scan->name);
if (scan == head) {
head = NULL;
@ -1765,6 +1874,18 @@ skip_ends:
ReopenCellDef((*CellStackPtr)->cellname, filenum); /* Reopen */
update = 1;
}
else if (tp->flags & CELL_VERILOG) {
if (tp->flags & CELL_PLACEHOLDER) {
/* Flag this as an error. To do: Rearrange the verilog instance pins to */
/* match the SPICE subcircuit pin order. */
Fprintf(stderr, "Error: SPICE subcircuit %s should be read before verilog "
"module using it, or pins may not match!\n", subcktname);
}
else {
Fprintf(stderr, "Error: SPICE subcircuit %s redefines a verilog module!\n",
subcktname);
}
}
/* nexttok is now NULL, scan->name points to class */
@ -1883,20 +2004,36 @@ char *ReadSpiceTop(char *fname, int *fnum, int blackbox)
CurrentCell = NULL;
if ((filenum = OpenParseFile(fname, *fnum)) < 0) {
char name[100];
SetExtension(name, fname, SPICE_EXTENSION);
if ((filenum = OpenParseFile(name, *fnum)) < 0) {
Fprintf(stderr,"Error in SPICE file read: No file %s\n",name);
if (strrchr(fname, '.') == NULL) {
char name[1024];
SetExtension(name, fname, SPICE_EXTENSION);
if ((filenum = OpenParseFile(name, *fnum)) < 0) {
Fprintf(stderr, "Error in SPICE file read: No file %s\n", name);
*fnum = filenum;
return NULL;
}
}
else {
Fprintf(stderr, "Error in SPICE file read: No file %s\n", fname);
*fnum = filenum;
return NULL;
}
}
}
/* Make sure all SPICE file reading is case insensitive */
matchfunc = matchnocase;
matchintfunc = matchfilenocase;
hashfunc = hashnocase;
/* Make sure all SPICE file reading is case insensitive */
/* BUT if a verilog file was read before it, then it will */
/* be forced to be case sensitive, caveat end-user. */
if (matchfunc == match) {
Printf("Warning: A case-sensitive file has been read and so the "
"SPICE netlist must be treated case-sensitive to match.\n");
}
else {
matchfunc = matchnocase;
matchintfunc = matchfilenocase;
hashfunc = hashnocase;
}
InitializeHashTable(&spiceparams, OBJHASHSIZE);
@ -1951,7 +2088,7 @@ void IncludeSpice(char *fname, int parent, struct cellstack **CellStackPtr,
int blackbox)
{
int filenum = -1;
char name[256];
char name[MAX_STR_LEN];
/* If fname does not begin with "/", then assume that it is */
/* in the same relative path as its parent. */
@ -1980,14 +2117,18 @@ void IncludeSpice(char *fname, int parent, struct cellstack **CellStackPtr,
/* helps, if the file didn't have an extension. But */
/* really, we're getting desperate at this point. */
if (strchr(fname, '.') == NULL) {
if (strrchr(fname, '.') == NULL) {
SetExtension(name, fname, SPICE_EXTENSION);
filenum = OpenParseFile(name, parent);
}
if (filenum < 0) {
Fprintf(stderr,"Error in SPICE file include: No file %s\n",name);
return;
if (filenum < 0) {
Fprintf(stderr, "Error in SPICE file include: No file %s\n", name);
return;
}
}
else {
Fprintf(stderr, "Error in SPICE file include: No file %s\n", fname);
return;
}
}
}
ReadSpiceFile(fname, parent, CellStackPtr, blackbox);

8
base/tech.h Normal file
View File

@ -0,0 +1,8 @@
#ifndef _TECH_H
#define _TECH_H
extern int ActelLibPresent(void);
extern void ActelLib(void);
extern void VerilogTop(char *name, int fnum, char *filename);
#endif /* _TECH_H */

View File

@ -34,6 +34,8 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
#include "print.h"
#endif
extern void Finsert(FILE *f);
void test_entry(void)
{

File diff suppressed because it is too large Load Diff

View File

@ -23,6 +23,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
#include <stdio.h>
#include <stdarg.h>
#include <ctype.h>
#include <time.h>
#ifdef IBMPC
#include <stdlib.h> /* for strtol on PC */
@ -33,6 +34,8 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
#include "netfile.h"
#include "hash.h"
#include "print.h"
#include "xilinx.h"
#include "flatten.h"
#define XILINXHASHSIZE 99
static long xilinxhashbase = 0xA00;
@ -132,10 +135,8 @@ char *xilinx_class(model)
}
return(model);
}
void
Xilinx(cellname, filename)
char *cellname;
char *filename;
void Xilinx(char *cellname, char *filename)
{
char Path[500];
char FileName[500];
@ -163,8 +164,7 @@ Xilinx(cellname, filename)
CloseFile(FileName);
}
xilinxCell(cell)
char *cell;
int xilinxCell(char *cell)
{
struct nlist *nl;
struct objlist *ob;
@ -252,9 +252,7 @@ struct objlist *xilinx_gate(ob,nl)
return(nob);
}
xilinx_sym(nl,gob)
struct nlist *nl;
struct objlist *gob;
void xilinx_sym(struct nlist *nl, struct objlist *gob)
{
struct objlist *ob;
char *cp,*rindex();

10
base/xilinx.h Normal file
View File

@ -0,0 +1,10 @@
#ifndef _XILINX_H
#define _XILINX_H
extern void xilinx_sym(struct nlist *nl, struct objlist *gob);
extern void Xilinx(char *cellname, char *filename);
extern int xilinxCell(char *cell);
extern int XilinxLibPresent(void);
extern void XilinxLib(void);
#endif /* _XILINX_H */

View File

@ -65,10 +65,10 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
Widget toplevel = NULL;
char GlobalFileName[100],
GlobalCellName[100],
GlobalOtherName[100],
GlobalDataName[100];
char GlobalFileName[MAX_STR_LEN],
GlobalCellName[MAX_STR_LEN],
GlobalOtherName[MAX_STR_LEN],
GlobalDataName[MAX_STR_LEN];
/*********************************************************
* Menu structure: attaches label string to a function,
@ -1708,7 +1708,7 @@ void X_main_loop(int argc, char *argv[])
XmStringCharSet cs = "ISOLatin1";
static char prompt_response[100];
static char prompt_response[MAX_STR_LEN];
int prompt_done;
int calling_editor; /* which string are we trying to get ? */
#define FILE_NAME 1

4
configure vendored
View File

@ -4,4 +4,6 @@
# all of its config scripts in a different directory than the configure
# script itself.
( CFLAGS="-g" ; export CFLAGS ; cd scripts ; ./configure "$@" )
export CFLAGS="$CFLAGS -g"
cd scripts
exec ./configure "$@"

View File

@ -1,85 +0,0 @@
# defs.mak.in --
# source file for autoconf-generated "defs.mak" for netgen
# defs.mak. Generated from defs.mak.in by configure.
# Feel free to change the values in here to suit your needs.
# Be aware that running scripts/configure again will overwrite
# any changes!
SHELL = /bin/sh
prefix = ${BUILDROOT}/usr/local
exec_prefix = ${prefix}
bindir = ${exec_prefix}/bin
libdir = ${exec_prefix}/lib
mandir = ${prefix}/share/man
VERSION =
SCRIPTS = ${NETGENDIR}/scripts
INSTALL = /bin/install -c
INSTALL_PROGRAM = ${INSTALL}
INSTALL_DATA = ${INSTALL} -m 644
INSTALL_SCRIPT = ${INSTALL}
# Override standard "make" target when compiling under TCL
ALL_TARGET = tcl
INSTALL_TARGET = install-tcl
# Change CADDIR to install in a different place
BINDIR = ${bindir}
MANDIR = ${mandir}
LIBDIR = ${libdir}
DOCDIR = ${libdir}/netgen/doc
TCLDIR = ${libdir}/netgen/tcl
PYDIR = ${libdir}/netgen/python
MAIN_EXTRA_LIBS = ${NETGENDIR}/tcltk/libtcltk.o
LD_EXTRA_LIBS =
LD_SHARED =
TOP_EXTRA_LIBS =
SUB_EXTRA_LIBS =
MODULES += tcltk
UNUSED_MODULES +=
PROGRAMS += tcltk
INSTALL_CAD_DIRS += tcltk
RM = rm -f
CP = cp
AR = @AR@
ARFLAGS = crv
LINK = /bin/ld -r
LD = /bin/ld
M4 = /bin/m4
RANLIB = ranlib
SHDLIB_EXT = .so
LDDL_FLAGS = -shared -Wl,-soname,$@ -Wl,--version-script=${NETGENDIR}/netgen/symbol.map
LD_RUN_PATH =
LIB_SPECS = -L/usr/lib64 -ltkstub8.6 -L/usr/lib64 -ltclstub8.6
LIB_SPECS_NOSTUB = -L/usr/lib64 -ltk8.6 -L/usr/lib64 -ltcl8.6
WISH_EXE = /usr/bin/wish
TCL_LIB_DIR = /usr/lib
CC = gcc
CPP = gcc -E -x c
CXX = @CXX@
CPPFLAGS = -I. -I${NETGENDIR}
DFLAGS = -DCAD_DIR=\"${LIBDIR}\" -DTCL_DIR=\"${TCLDIR}\" -DUSE_TCL_STUBS -DUSE_TK_STUBS -DPACKAGE_NAME=\"netgen\" -DPACKAGE_TARNAME=\"netgen\" -DPACKAGE_VERSION=\"1.3\" -DPACKAGE_STRING=\"netgen\ 1.3\" -DPACKAGE_BUGREPORT=\"eda-dev@opencircuitdesign.com\" -DPACKAGE_URL=\"\" -DNETGEN_VERSION=\"1.5\" -DNETGEN_REVISION=\"112\" -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DSIZEOF_VOID_P=8 -DSIZEOF_UNSIGNED_INT=4 -DSIZEOF_UNSIGNED_LONG=8 -DSIZEOF_UNSIGNED_LONG_LONG=8 -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DHAVE_DIRENT_H=1 -DHAVE_LIMITS_H=1 -DHAVE_VA_COPY=1 -DHAVE___VA_COPY=1 -DDBUG_OFF=1 -DTCL_NETGEN=1 -Dlinux=1 -DSYSV=1 -DISC=1 -DSHDLIB_EXT=\".so\" -DNDEBUG
DFLAGS_NOSTUB = -DCAD_DIR=\"${LIBDIR}\" -DTCL_DIR=\"${TCLDIR}\" -DPACKAGE_NAME=\"netgen\" -DPACKAGE_TARNAME=\"netgen\" -DPACKAGE_VERSION=\"1.3\" -DPACKAGE_STRING=\"netgen\ 1.3\" -DPACKAGE_BUGREPORT=\"eda-dev@opencircuitdesign.com\" -DPACKAGE_URL=\"\" -DNETGEN_VERSION=\"1.5\" -DNETGEN_REVISION=\"112\" -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DSIZEOF_VOID_P=8 -DSIZEOF_UNSIGNED_INT=4 -DSIZEOF_UNSIGNED_LONG=8 -DSIZEOF_UNSIGNED_LONG_LONG=8 -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DHAVE_DIRENT_H=1 -DHAVE_LIMITS_H=1 -DHAVE_VA_COPY=1 -DHAVE___VA_COPY=1 -DDBUG_OFF=1 -DTCL_NETGEN=1 -Dlinux=1 -DSYSV=1 -DISC=1 -DSHDLIB_EXT=\".so\" -DNDEBUG
CFLAGS = -g -m64 -fPIC -fPIC
DEPEND_FILE = Depend
DEPEND_FLAG = -MM
EXEEXT =
GR_CFLAGS =
GR_DFLAGS = -DX11 -DXLIB -DNDEBUG
GR_LIBS = -lX11
GR_SRCS = ${TK_SRCS}
OBJS = ${SRCS:.c=.o}
LIB_OBJS = ${LIB_SRCS:.c=.o}
CLEANS = ${OBJS} ${LIB_OBJS} lib${MODULE}.a lib${MODULE}.o ${MODULE}

View File

@ -2,11 +2,11 @@ NETGENDIR = ..
include ${NETGENDIR}/defs.mak
MANDIRS = $(DESTDIR)${MANDIR} $(DESTDIR)${MANDIR}/man1
DOCDIRS = $(DESTDIR)${DOCDIR}
MANDIRS = $(DESTDIR)${INSTALL_MANDIR} $(DESTDIR)${INSTALL_MANDIR}/man1
DOCDIRS = $(DESTDIR)${INSTALL_DOCDIR}
MANFILES =
DOCFILES = $(DESTDIR)${DOCDIR}/netgen.doc
DOCFILES = $(DESTDIR)${INSTALL_DOCDIR}/netgen.doc
install-tcl: ${DOCDIRS} ${DOCFILES}
@ -23,8 +23,8 @@ make-doc-dirs:
${SCRIPTS}/mkdirs ${DOCDIRS}
# This file does not actually exist. . .
$(DESTDIR)${MANDIR}/man1/netgen.1: netgen.1 ${MANDIRS}
${CP} netgen.1 $(DESTDIR)${MANDIR}/man1/netgen.1
$(DESTDIR)${INSTALL_MANDIR}/man1/netgen.1: netgen.1 ${MANDIRS}
${CP} netgen.1 $(DESTDIR)${INSTALL_MANDIR}/man1/netgen.1
$(DESTDIR)${DOCDIR}/netgen.doc: netgen.doc ${DOCDIRS}
${CP} netgen.doc $(DESTDIR)${DOCDIR}/netgen.doc
$(DESTDIR)${INSTALL_DOCDIR}/netgen.doc: netgen.doc ${DOCDIRS}
${CP} netgen.doc $(DESTDIR)${INSTALL_DOCDIR}/netgen.doc

View File

@ -4,14 +4,14 @@ include ${NETGENDIR}/defs.mak
LIB_FILES = ntk2adl.sh spice spice.bot spice.top
LIB_INST_FILES= $(LIB_FILES:%=$(DESTDIR)${LIBDIR}/netgen/%)
BIN_INST_FILES= $(BIN_FILES:%=$(DESTDIR)${BINDIR}/%)
LIB_INST_FILES= $(LIB_FILES:%=$(DESTDIR)${INSTALL_LIBDIR}/netgen/%)
BIN_INST_FILES= $(BIN_FILES:%=$(DESTDIR)${INSTALL_BINDIR}/%)
install-tcl: ${LIB_INST_FILES}
install: ${LIB_INST_FILES}
$(DESTDIR)${LIBDIR}/netgen/%: %
../scripts/mkdirs $(DESTDIR)${LIBDIR}/netgen
${RM} $(DESTDIR)${LIBDIR}/netgen/$*
${CP} $* $(DESTDIR)${LIBDIR}/netgen/$*
$(DESTDIR)${INSTALL_LIBDIR}/netgen/%: %
../scripts/mkdirs $(DESTDIR)${INSTALL_LIBDIR}/netgen
${RM} $(DESTDIR)${INSTALL_LIBDIR}/netgen/$*
${CP} $* $(DESTDIR)${INSTALL_LIBDIR}/netgen/$*

View File

@ -25,23 +25,23 @@ tclnetgen${SHDLIB_EXT}: ${EXTRA_LIBS}
${LD_RUN_PATH} ${EXTRA_LIBS} ${LD_EXTRA_LIBS} \
-lc ${LIBS} ${LIB_SPECS} ${LDFLAGS}
$(DESTDIR)${BINDIR}/netgen:
$(DESTDIR)${INSTALL_BINDIR}/netgen:
${RM} $@
${CP} netgen $@
$(DESTDIR)${BINDIR}/ntk2adl:
$(DESTDIR)${INSTALL_BINDIR}/ntk2adl:
${RM} $@
${CP} ntk2adl $@
$(DESTDIR)${BINDIR}/ntk2xnf:
$(DESTDIR)${INSTALL_BINDIR}/ntk2xnf:
${RM} $@
${CP} ntk2xnf $@
$(DESTDIR)${BINDIR}/netcomp:
$(DESTDIR)${INSTALL_BINDIR}/netcomp:
${RM} $@
${CP} netcomp $@
$(DESTDIR)${BINDIR}/inetcomp:
$(DESTDIR)${INSTALL_BINDIR}/inetcomp:
${RM} $@
${CP} inetcomp $@
@ -61,14 +61,14 @@ ntk2xnf: ntk2xnf.c
${CC} ${CFLAGS} ${CPPFLAGS} ${DFLAGS} ntk2xnf.c -o $@ ${EXTRA_LIBS} \
${LIBS} ${LDFLAGS}
install: $(DESTDIR)${BINDIR}/netgen $(DESTDIR)${BINDIR}/netcomp \
$(DESTDIR)${BINDIR}/inetcomp $(DESTDIR)${BINDIR}/ntk2adl \
$(DESTDIR)${BINDIR}/ntk2xnf
install: $(DESTDIR)${INSTALL_BINDIR}/netgen $(DESTDIR)${INSTALL_BINDIR}/netcomp \
$(DESTDIR)${INSTALL_BINDIR}/inetcomp $(DESTDIR)${INSTALL_BINDIR}/ntk2adl \
$(DESTDIR)${INSTALL_BINDIR}/ntk2xnf
install-tcl: $(DESTDIR)${TCLDIR} $(DESTDIR)${TCLDIR}/tclnetgen${SHDLIB_EXT}
install-tcl: $(DESTDIR)${INSTALL_TCLDIR} $(DESTDIR)${INSTALL_TCLDIR}/tclnetgen${SHDLIB_EXT}
$(DESTDIR)${TCLDIR}/tclnetgen${SHDLIB_EXT}: tclnetgen${SHDLIB_EXT}
${RM} $(DESTDIR)${TCLDIR}/tclnetgen${SHDLIB_EXT}
${CP} tclnetgen${SHDLIB_EXT} $(DESTDIR)${TCLDIR}/tclnetgen${SHDLIB_EXT}
$(DESTDIR)${INSTALL_TCLDIR}/tclnetgen${SHDLIB_EXT}: tclnetgen${SHDLIB_EXT}
${RM} $(DESTDIR)${INSTALL_TCLDIR}/tclnetgen${SHDLIB_EXT}
${CP} tclnetgen${SHDLIB_EXT} $(DESTDIR)${INSTALL_TCLDIR}/tclnetgen${SHDLIB_EXT}
include ${NETGENDIR}/rules.mak

View File

@ -17,6 +17,7 @@ along with this program; see the file copying. If not, write to
the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
/* inetcomp.c -- a simple wrapper to the NETCOMP() function */
#include "config.h"
#include <stdio.h>
#include "netgen.h"
@ -33,7 +34,7 @@ void STRCPY(char *dest, char *source)
int main(int argc, char *argv[])
{
char cell1[200], cell2[200];
char cell1[MAX_STR_LEN], cell2[MAX_STR_LEN];
Debug = 0;
if (argc != 1) {

View File

@ -17,6 +17,7 @@ along with this program; see the file copying. If not, write to
the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
/* netcomp.c -- a simple wrapper to provide netlist comparison functionality */
#include "config.h"
#include <stdio.h>
#include "netgen.h"
@ -51,7 +52,7 @@ void STRCPY(char *dest, char *source)
int main(int argc, char *argv[])
{
#ifndef HAVE_GETOPT
char cell1[200], cell2[200];
char cell1[MAX_STR_LEN], cell2[MAX_STR_LEN];
int filenum = -1;
Debug = 0;
@ -67,7 +68,7 @@ int main(int argc, char *argv[])
STRCPY(cell2, ReadNetlist(argv[2], &filenum));
if (argc == 5) STRCPY(cell2, argv[4]); /* if explicit cell name specified */
#else
char cell1[200], cell2[200];
char cell1[MAX_STR_LEN], cell2[MAX_STR_LEN];
int usage = 0;
int args;
int c;

View File

@ -23,6 +23,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
#include <stdlib.h> /* for getenv */
#endif
#include "netgen.h"
#include "print.h"
int main(int argc, char **argv)
{

View File

@ -20,9 +20,11 @@ along with this program; see the file copying. If not, write to
the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
/* ntk2xnf.c -- a simple wrapper to translate .ntk to Xilinx XNF format */
#include "config.h"
#include <stdio.h>
#include "netgen.h"
#include "xilinx.h"
#ifdef HAVE_X11
/* the following two X procedures are to permit linking
@ -47,7 +49,7 @@ void STRCPY(char *dest, char *source)
int main(int argc, char *argv[])
{
char cellname[200];
char cellname[MAX_STR_LEN];
int filenum = -1;
Debug = 0;

View File

@ -4,19 +4,21 @@ SRCS =
SCRIPTS = consoletext.py helpwindow.py lvs_manager.py treeviewsplit.py
SCRIPTS += tksimpledialog.py tooltip.py lvs_help.txt
SCRIPTINSTALL = $(DESTDIR)${PYDIR}
SCRIPTINSTALL = $(DESTDIR)${INSTALL_PYDIR}
include ${NETGENDIR}/defs.mak
CLEANS += lvs_manager.py
main: lvs_manager.py
tcl-main: lvs_manager.py
$(DESTDIR)${PYDIR}/consoletext.py:
$(DESTDIR)${INSTALL_PYDIR}/consoletext.py:
${RM} $@
${CP} consoletext.py $@
$(DESTDIR)${PYDIR}/helpwindow.py:
$(DESTDIR)${INSTALL_PYDIR}/helpwindow.py:
${RM} $@
${CP} helpwindow.py $@
@ -24,31 +26,32 @@ lvs_manager.py: lvs_manager.py.in
sed -e '/SUBST_SCRIPT_DIR/s#SUBST_SCRIPT_DIR#$(SCRIPTINSTALL)#' \
lvs_manager.py.in > lvs_manager.py
$(DESTDIR)${PYDIR}/lvs_manager.py: lvs_manager.py
$(DESTDIR)${INSTALL_PYDIR}/lvs_manager.py: lvs_manager.py
${RM} $@
${CP} lvs_manager.py $@
chmod a+x $@
$(DESTDIR)${PYDIR}/treeviewsplit.py: treeviewsplit.py
$(DESTDIR)${INSTALL_PYDIR}/treeviewsplit.py: treeviewsplit.py
${RM} $@
${CP} treeviewsplit.py $@
$(DESTDIR)${PYDIR}/tksimpledialog.py: tksimpledialog.py
$(DESTDIR)${INSTALL_PYDIR}/tksimpledialog.py: tksimpledialog.py
${RM} $@
${CP} tksimpledialog.py $@
$(DESTDIR)${PYDIR}/tooltip.py: tooltip.py
$(DESTDIR)${INSTALL_PYDIR}/tooltip.py: tooltip.py
${RM} $@
${CP} tooltip.py $@
$(DESTDIR)${PYDIR}/lvs_help.txt: lvs_help.txt
$(DESTDIR)${INSTALL_PYDIR}/lvs_help.txt: lvs_help.txt
${RM} $@
${CP} lvs_help.txt $@
install: install-tcl
install-tcl: $(DESTDIR)${PYDIR} $(DESTDIR)${PYDIR}/consoletext.py \
$(DESTDIR)${PYDIR}/helpwindow.py $(DESTDIR)${PYDIR}/lvs_manager.py \
$(DESTDIR)${PYDIR}/treeviewsplit.py $(DESTDIR)${PYDIR}/tksimpledialog.py \
$(DESTDIR)${PYDIR}/tooltip.py $(DESTDIR)${PYDIR}/lvs_help.txt
install-tcl: $(DESTDIR)${INSTALL_PYDIR} $(DESTDIR)${INSTALL_PYDIR}/consoletext.py \
$(DESTDIR)${INSTALL_PYDIR}/helpwindow.py $(DESTDIR)${INSTALL_PYDIR}/lvs_manager.py \
$(DESTDIR)${INSTALL_PYDIR}/treeviewsplit.py $(DESTDIR)${INSTALL_PYDIR}/tksimpledialog.py \
$(DESTDIR)${INSTALL_PYDIR}/tooltip.py $(DESTDIR)${INSTALL_PYDIR}/lvs_help.txt
include ${NETGENDIR}/rules.mak

View File

@ -1,819 +0,0 @@
#!/bin/env python3
#
#--------------------------------------------------------
# LVS Manager GUI.
#
# This is a Python tkinter script that handles the
# process of running LVS and interpreting results.
#
#--------------------------------------------------------
# Written by Tim Edwards
# efabless, inc.
# Version 1. November 30, 2016
# Version 2. March 6, 2017. Reads JSON format output
# Version 3. April 25, 2018. Handles layout vs. verilog
#--------------------------------------------------------
import io
import os
import re
import sys
import json
import shutil
import signal
import socket
import select
import datetime
import contextlib
import subprocess
import tkinter
from tkinter import ttk
from tkinter import filedialog
import tksimpledialog
import tooltip
from consoletext import ConsoleText
from helpwindow import HelpWindow
from treeviewsplit import TreeViewSplit
# User preferences file (if it exists)
prefsfile = '~/.profile/prefs.json'
netgen_script_dir = '/usr/local/lib/netgen/python'
#------------------------------------------------------
# Simple dialog for confirming quit
#------------------------------------------------------
class ConfirmDialog(tksimpledialog.Dialog):
def body(self, master, warning, seed):
if warning:
ttk.Label(master, text=warning, wraplength=500).grid(row = 0, columnspan = 2, sticky = 'wns')
return self
def apply(self):
return 'okay'
#------------------------------------------------------
# Main class for this application
#------------------------------------------------------
class LVSManager(ttk.Frame):
"""LVS Manager GUI."""
def __init__(self, parent, *args, **kwargs):
ttk.Frame.__init__(self, parent, *args, **kwargs)
self.root = parent
self.init_gui()
parent.protocol("WM_DELETE_WINDOW", self.on_quit)
def on_quit(self):
"""Exits program."""
if self.msock:
self.msock.close()
quit()
def init_gui(self):
"""Builds GUI."""
global prefsfile
message = []
fontsize = 11
# Read user preferences file, get default font size from it.
prefspath = os.path.expanduser(prefsfile)
if os.path.exists(prefspath):
with open(prefspath, 'r') as f:
self.prefs = json.load(f)
if 'fontsize' in self.prefs:
fontsize = self.prefs['fontsize']
else:
self.prefs = {}
s = ttk.Style()
available_themes = s.theme_names()
s.theme_use(available_themes[0])
s.configure('bg.TFrame', background='gray40')
s.configure('italic.TLabel', font=('Helvetica', fontsize, 'italic'))
s.configure('title.TLabel', font=('Helvetica', fontsize, 'bold italic'),
foreground = 'brown', anchor = 'center')
s.configure('normal.TLabel', font=('Helvetica', fontsize))
s.configure('red.TLabel', font=('Helvetica', fontsize), foreground = 'red')
s.configure('green.TLabel', font=('Helvetica', fontsize), foreground = 'green3')
s.configure('blue.TLabel', font=('Helvetica', fontsize), foreground = 'blue')
s.configure('normal.TButton', font=('Helvetica', fontsize),
border = 3, relief = 'raised')
s.configure('red.TButton', font=('Helvetica', fontsize), foreground = 'red',
border = 3, relief = 'raised')
s.configure('green.TButton', font=('Helvetica', fontsize), foreground = 'green3',
border = 3, relief = 'raised')
s.configure('blue.TButton', font=('Helvetica', fontsize), foreground = 'blue',
border = 3, relief = 'raised')
s.configure('redtitle.TButton', font=('Helvetica', fontsize, 'bold italic'),
foreground = 'red', border = 3, relief = 'raised')
s.configure('bluetitle.TButton', font=('Helvetica', fontsize, 'bold italic'),
foreground = 'blue', border = 3, relief = 'raised')
# These values to be overridden from arguments
self.rootpath = None
self.project = None
self.logfile = None
self.msock = None
self.help = None
# Create the help window
if os.path.exists(netgen_script_dir + '/netgen_help.txt'):
self.help = HelpWindow(self, fontsize = fontsize)
with io.StringIO() as buf, contextlib.redirect_stdout(buf):
self.help.add_pages_from_file('lvs_help.txt')
message = buf.getvalue()
# Set the help display to the first page
self.help.page(0)
# Variables used by option menus and other stuff
self.project = "(no selection)"
self.layout = "(default)"
self.schematic = "(default)"
self.tech = "(none)"
self.lvs_setup = ''
self.lvsdata = {}
# Root window title
self.root.title('LVS Manager')
self.root.option_add('*tearOff', 'FALSE')
self.pack(side = 'top', fill = 'both', expand = 'true')
pane = tkinter.PanedWindow(self, orient = 'vertical', sashrelief='groove', sashwidth=6)
pane.pack(side = 'top', fill = 'both', expand = 'true')
self.toppane = ttk.Frame(pane)
self.botpane = ttk.Frame(pane)
# Get username
if 'username' in self.prefs:
username = self.prefs['username']
else:
username = os.environ['USER']
# Label with the user
self.toppane.title_frame = ttk.Frame(self.toppane)
self.toppane.title_frame.pack(side = 'top', fill = 'x')
self.toppane.title_frame.title = ttk.Label(self.toppane.title_frame, text='User:', style = 'red.TLabel')
self.toppane.title_frame.user = ttk.Label(self.toppane.title_frame, text=username, style = 'blue.TLabel')
self.toppane.title_frame.title.grid(column=0, row=0, ipadx = 5)
self.toppane.title_frame.user.grid(column=1, row=0, ipadx = 5)
self.toppane.title2_frame = ttk.Frame(self.toppane)
self.toppane.title2_frame.pack(side = 'top', fill = 'x')
self.toppane.title2_frame.project_label = ttk.Label(self.toppane.title2_frame, text="Project:",
style = 'title.TLabel')
self.toppane.title2_frame.project_label.grid(column=0, row=0, ipadx = 5)
# New project select button
self.toppane.title2_frame.project_select = ttk.Button(self.toppane.title2_frame,
text=self.project, style='normal.TButton', command=self.choose_project)
self.toppane.title2_frame.project_select.grid(column=1, row=0, ipadx = 5)
tooltip.ToolTip(self.toppane.title2_frame.project_select,
text = "Select new project")
# Show path to project
self.toppane.title2_frame.path_label = ttk.Label(self.toppane.title2_frame, text=self.project,
style = 'normal.TLabel')
self.toppane.title2_frame.path_label.grid(column=2, row=0, ipadx = 5, padx = 10)
# Show top-level layout cellname with select button. Initial cell name is the top-level cell.
self.toppane.title2_frame.tech_label = ttk.Label(self.toppane.title2_frame, text="Technology setup:",
style = 'title.TLabel')
self.toppane.title2_frame.tech_label.grid(column=3, row=0, ipadx = 5)
self.toppane.title2_frame.tech_select = ttk.Button(self.toppane.title2_frame,
text=self.tech, style='normal.TButton', command=self.choose_tech)
self.toppane.title2_frame.tech_select.grid(column=4, row=0, ipadx = 3, padx = 3)
self.toppane.title2_frame.layout_label = ttk.Label(self.toppane.title2_frame, text="Layout:",
style = 'title.TLabel')
self.toppane.title2_frame.layout_label.grid(column=0, row=1, ipadx = 5)
self.toppane.title2_frame.layout_select = ttk.Button(self.toppane.title2_frame,
text=self.layout, style='normal.TButton', command=self.choose_layout)
self.toppane.title2_frame.layout_select.grid(column=1, row=1, ipadx = 3, padx = 3)
# Show top-level schematic cellname with select button. Initial cell name is the top-level cell.
self.toppane.title2_frame.schem_label = ttk.Label(self.toppane.title2_frame, text="Schematic:",
style = 'title.TLabel')
self.toppane.title2_frame.schem_label.grid(column=3, row=1, ipadx = 5)
self.toppane.title2_frame.schem_select = ttk.Button(self.toppane.title2_frame,
text=self.schematic, style='normal.TButton', command=self.choose_netlist)
self.toppane.title2_frame.schem_select.grid(column=4, row=1, ipadx = 3, padx = 3)
tooltip.ToolTip(self.toppane.title2_frame.project_select,
text = "Select new project")
tooltip.ToolTip(self.toppane.title2_frame.layout_select,
text = "Select a layout subcirucit to compare")
tooltip.ToolTip(self.toppane.title2_frame.schem_select,
text = "Select a schematic subcirucit to compare")
#---------------------------------------------
ttk.Separator(self.toppane, orient='horizontal').pack(side = 'top', fill = 'x')
#---------------------------------------------
# Create listbox of Circuit1 vs. Circuit2 results
height = 10
self.toppane.lvsreport = TreeViewSplit(self.toppane, fontsize = fontsize)
self.toppane.lvsreport.populate("Layout:", [], "Schematic:", [],
[["Run", True, self.run_lvs],
# ["Find", True, self.findrecord]
], height = height)
self.toppane.lvsreport.set_title("Line")
self.toppane.lvsreport.pack(side = 'top', fill = 'both', expand = 'true')
tooltip.ToolTip(self.toppane.lvsreport.get_button(0), text="Run LVS")
#---------------------------------------------
# ttk.Separator(self, orient='horizontal').grid(column=0, row=3, sticky='ew')
#---------------------------------------------
# Add a text window below the project name to capture output. Redirect
# print statements to it.
self.botpane.console = ttk.Frame(self.botpane)
self.botpane.console.pack(side = 'top', fill = 'both', expand = 'true')
self.text_box = ConsoleText(self.botpane.console, wrap='word', height = 4)
self.text_box.pack(side='left', fill='both', expand='true')
console_scrollbar = ttk.Scrollbar(self.botpane.console)
console_scrollbar.pack(side='right', fill='y')
# attach console to scrollbar
self.text_box.config(yscrollcommand = console_scrollbar.set)
console_scrollbar.config(command = self.text_box.yview)
# Add button bar at the bottom of the window
self.botpane.bbar = ttk.Frame(self.botpane)
self.botpane.bbar.pack(side = 'top', fill = 'x')
# Define the "quit" button and action
self.botpane.bbar.quit_button = ttk.Button(self.botpane.bbar, text='Quit', command=self.on_quit,
style = 'normal.TButton')
self.botpane.bbar.quit_button.grid(column=0, row=0, padx = 5)
# Define help button
if self.help:
self.botpane.bbar.help_button = ttk.Button(self.botpane.bbar, text='Help',
command=self.help.open, style = 'normal.TButton')
self.botpane.bbar.help_button.grid(column = 2, row = 0, padx = 5)
tooltip.ToolTip(self.botpane.bbar.help_button, text = "Show help window")
# Add the panes once the internal geometry is known.
pane.add(self.toppane)
pane.add(self.botpane)
pane.paneconfig(self.toppane, stretch='first')
# Redirect stdout and stderr to the console as the last thing to do. . .
# Otherwise errors in the GUI get sucked into the void.
self.stdout = sys.stdout
self.stderr = sys.stderr
sys.stdout = ConsoleText.StdoutRedirector(self.text_box)
sys.stderr = ConsoleText.StderrRedirector(self.text_box)
if message:
print(message)
def logprint(self, message, doflush=False):
if self.logfile:
self.logfile.buffer.write(message.encode('utf-8'))
self.logfile.buffer.write('\n'.encode('utf-8'))
if doflush:
self.logfile.flush()
def printout(self, output):
# Generate output
if not output:
return
outlines = output.splitlines()
for line in outlines:
try:
print(line)
except TypeError:
line = line.decode('utf-8')
pritn(line)
def printwarn(self, output):
# Check output for warning or error
if not output:
return 0
warnrex = re.compile('.*warning', re.IGNORECASE)
errrex = re.compile('.*error', re.IGNORECASE)
errors = 0
outlines = output.splitlines()
for line in outlines:
try:
wmatch = warnrex.match(line)
except TypeError:
line = line.decode('utf-8')
wmatch = warnrex.match(line)
ematch = errrex.match(line)
if ematch:
errors += 1
if ematch or wmatch:
print(line)
return errors
def choose_tech(self):
try:
project_path = self.rootpath
initdirname = self.rootpath + '/tech',
except:
print('Must choose a project first.')
return
techname = filedialog.askopenfilename(multiple=False,
initialdir = initdirname,
filetypes = (("Tcl script", "*.tcl"),("All Files","*.*")),
title = "Choose a netgen technology setup script.")
if techname != '':
print("Selected technology setup script " + techname)
techbase = os.path.split(techname)[1]
self.tech = os.path.splitext(techbase)[0]
self.lvs_setup = techname
self.toppane.title2_frame.layout_select.config(text = self.tech)
def choose_layout(self):
try:
project_path = self.rootpath
initdirname = self.rootpath + '/layout',
except:
print('Must choose a project first.')
return
cellname = filedialog.askopenfilename(multiple=False,
initialdir = initdirname,
filetypes = (("Magic layout", "*.mag"),("All Files","*.*")),
title = "Choose a layout cell to compare.")
if cellname != '':
print("Selected compare cell " + cellname)
cellbase = os.path.split(cellname)[1]
self.layout = os.path.splitext(cellbase)[0]
self.toppane.title2_frame.layout_select.config(text = self.layout)
def choose_netlist(self):
try:
project_path = self.rootpath
initdirname = self.rootpath + '/netlist/' + self.project + '.spi'
except:
print('Must choose a project first.')
return
cellname = filedialog.askopenfilename(multiple=False,
initialdir = initdirname,
filetypes = (("Spice netlist", "*.spi"),("Verilog netlist", "*.v")),
title = "Choose a netlist to compare.")
if cellname != '':
print("Selected compare cell " + cellname)
cellbase = os.path.split(cellname)[1]
self.schematic = os.path.splitext(cellbase)[0]
self.toppane.title2_frame.schem_select.config(text = self.schematic)
fileext = os.path.splitext(cellbase)[1]
if fileext == '.v':
self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
elif fileext == '.sp' or fileext == '.spi' or fileext == '.spice' or fileext == '.spc' or fileext == '.ckt':
self.toppane.title2_frame.schem_label.config(text = 'SPICE netlist:')
elif fileext == '.cdl':
self.toppane.title2_frame.schem_label.config(text = 'CDL netlist:')
else:
self.toppane.title2_frame.schem_label.config(text = 'Unknown netlist:')
def choose_project(self):
project = filedialog.askdirectory(initialdir = os.getcwd(),
title = "Find a project.")
if project != '':
print("Selected project " + str(project))
result = self.set_project(project)
def set_project(self, rootpath, project_name=None):
# Check if rootpath is valid. For LVS, there should be subdirectories
# "layout/" and "netlist/" or "verilog/".
haslay = os.path.isdir(rootpath + '/layout')
hasvlog = os.path.isdir(rootpath + '/verilog')
hasnet = os.path.isdir(rootpath + '/netlist')
if not haslay or not (hasvlog or hasnet):
if not haslay:
print("Project path has no layout (/layout) subdirectory.")
if not (hasvlog or hasnet):
print("Project path has no verilog (/verilog), or netlist (/netlist) subdirectory.")
# Continue anyway; assume that netlists will be selected manually
if self.logfile:
self.logfile.close()
self.logfile = None
if not project_name:
project = os.path.split(rootpath)[1]
else:
project = project_name
if self.project != project:
self.rootpath = rootpath
self.project = project
# Clear out old project data
self.toppane.lvsreport.repopulate([], [])
# Close any open logfile.
if self.logfile:
self.logfile.close()
self.logfile = None
# Put new log file called 'lvs.log' in the mag/ subdirectory
self.logfile = open(rootpath + '/layout/lvs.log', 'w')
# Print some initial information to the logfile.
self.logprint('Starting new log file ' + datetime.datetime.now().strftime('%c'),
doflush=True)
# Update project button
self.toppane.title2_frame.project_select.config(text = self.project)
self.toppane.title2_frame.path_label.config(text = self.rootpath)
# Cell name is the same as project name initially
self.layout = self.project
self.schematic = self.project
self.toppane.title2_frame.layout_select.config(text = self.layout)
self.toppane.title2_frame.schem_select.config(text = self.schematic)
# Update schematic button
if os.path.isfile(rootpath + '/verilog/' + self.schematic + '.v'):
self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
else:
self.toppane.title2_frame.schem_label.config(text = 'Schematic netlist:')
# If there is a comparison file that post-dates both netlists, load it.
self.check_lvs()
return True
def check_layout_out_of_date(self, spipath, layoutpath):
# Check if a netlist (spipath) is out-of-date relative to the layouts
# (layoutpath). Need to read the netlist and check all of the subcells.
need_capture = False
if not os.path.isfile(spipath):
return True
if os.path.isfile(layoutpath):
spi_statbuf = os.stat(spipath)
lay_statbuf = os.stat(layoutpath)
if spi_statbuf.st_mtime < lay_statbuf.st_mtime:
# netlist exists but is out-of-date
need_capture = True
else:
# only found that the top-level-layout is older than the
# netlist. Now need to read the netlist, find all subcircuits,
# and check those dates, too.
layoutdir = os.path.split(layoutpath)[0]
subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
with open(spipath, 'r') as ifile:
duttext = ifile.read()
dutlines = duttext.replace('\n+', ' ').splitlines()
for line in dutlines:
lmatch = subrex.match(line)
if lmatch:
subname = lmatch.group(1)
sublayout = layoutdir + '/' + subname + '.mag'
# subcircuits that cannot be found in the current directory are
# assumed to be library components and therefore never out-of-date.
if os.path.exists(sublayout):
sub_statbuf = os.stat(sublayout)
if spi_statbuf.st_mtime < lay_statbuf.st_mtime:
# netlist exists but is out-of-date
need_capture = True
break
return need_capture
def check_schematic_out_of_date(self, spipath, schempath):
# Check if a netlist (spipath) is out-of-date relative to the schematics
# (schempath). Need to read the netlist and check all of the subcells.
need_capture = False
if not os.path.isfile(spipath):
return True
if os.path.isfile(schempath):
spi_statbuf = os.stat(spipath)
sch_statbuf = os.stat(schempath)
if spi_statbuf.st_mtime < sch_statbuf.st_mtime:
# netlist exists but is out-of-date
need_capture = True
else:
# only found that the top-level-schematic is older than the
# netlist. Now need to read the netlist, find all subcircuits,
# and check those dates, too.
schemdir = os.path.split(schempath)[0]
subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
with open(spipath, 'r') as ifile:
duttext = ifile.read()
dutlines = duttext.replace('\n+', ' ').splitlines()
for line in dutlines:
lmatch = subrex.match(line)
if lmatch:
subname = lmatch.group(1)
# NOTE: Electric uses library:cell internally to track libraries,
# and maps the ":" to "__" in the netlist. Not entirely certain that
# the double-underscore uniquely identifies the library:cell. . .
librex = re.compile('(.*)__(.*)', re.IGNORECASE)
lmatch = librex.match(subname)
if lmatch:
elecpath = os.path.split(os.path.split(schempath)[0])[0]
libname = lmatch.group(1)
subschem = elecpath + '/' + libname + '.delib/' + lmatch.group(2) + '.sch'
else:
libname = {}
subschem = schemdir + '/' + subname + '.sch'
# subcircuits that cannot be found in the current directory are
# assumed to be library components and therefore never out-of-date.
if os.path.exists(subschem):
sub_statbuf = os.stat(subschem)
if spi_statbuf.st_mtime < sub_statbuf.st_mtime:
# netlist exists but is out-of-date
need_capture = True
break
# mapping of characters to what's allowed in SPICE makes finding
# the associated schematic file a bit difficult. Requires wild-card
# searching.
elif libname:
restr = lmatch.group(2) + '.sch'
restr = restr.replace('.', '\.')
restr = restr.replace('_', '.')
schrex = re.compile(restr, re.IGNORECASE)
libpath = elecpath + '/' + libname + '.delib'
if os.path.exists(libpath):
liblist = os.listdir(libpath)
for file in liblist:
lmatch = schrex.match(file)
if lmatch:
subschem = libpath + '/' + file
sub_statbuf = os.stat(subschem)
if spi_statbuf.st_mtime < sch_statbuf.st_mtime:
# netlist exists but is out-of-date
need_capture = True
break
return need_capture
def check_lvs(self):
# If both netlists exist, and comp.json is more recent than both, then
# load LVS results from comp.json
project_path = self.rootpath
project_name = self.project
layout_path = project_path + '/layout/' + project_name + '.spc'
net_path = project_path + '/netlist/' + project_name + '.spi'
comp_path = project_path + '/layout/comp.json'
if os.path.exists(layout_path) and os.path.exists(net_path) and os.path.exists(comp_path):
magtime = os.stat(layout_path).st_mtime
schemtime = os.stat(net_path).st_mtime
comptime = os.stat(comp_path).st_mtime
if comptime > magtime and comptime > schemtime:
print("Loading LVS results from file.")
self.generate(comp_path)
def generate_layout_netlist(self, layout_path, layout_src, project_path):
# Does layout netlist exist and is it current?
if self.check_layout_out_of_date(layout_path, layout_src):
print('Generating layout netlist.')
self.update_idletasks()
mproc = subprocess.Popen(['magic', '-dnull', '-noconsole',
self.layout], stdin = subprocess.PIPE, stdout = subprocess.PIPE,
stderr = subprocess.PIPE, cwd = project_path + '/layout',
universal_newlines = True)
mproc.stdin.write("select top cell\n")
mproc.stdin.write("expand\n")
mproc.stdin.write("extract all\n")
mproc.stdin.write("ext2spice hierarchy on\n")
mproc.stdin.write("ext2spice format ngspice\n")
mproc.stdin.write("ext2spice scale off\n")
mproc.stdin.write("ext2spice renumber off\n")
mproc.stdin.write("ext2spice subcircuit top auto\n")
mproc.stdin.write("ext2spice cthresh infinite\n")
mproc.stdin.write("ext2spice rthresh infinite\n")
mproc.stdin.write("ext2spice blackbox on\n")
mproc.stdin.write("ext2spice -o " + self.layout + ".spi\n")
mproc.stdin.write("quit -noprompt\n")
magicout = mproc.communicate()[0]
self.printwarn(magicout)
if mproc.returncode != 0:
print('Failure to generate new layout netlist.')
return False
# Move .spi netlist to project_dir/netlist/lvs/
shutil.move(project_path + '/layout/' + self.layout + '.spi', layout_path)
# Remove extraction files
for file in os.listdir(project_path + '/layout'):
if os.path.splitext(file)[1] == '.ext':
os.remove(project_path + '/layout/' + file)
else:
print('Layout netlist is up-to-date, not regenerating.')
return True
def run_lvs(self, value):
# "value" is ignored (?)
# Check if netlists exist and are current; otherwise create them.
# Then run LVS.
project_path = self.rootpath
project_name = self.project
comp_path = project_path + '/layout/comp.json'
has_vlog = False
vlog_path = project_path + '/verilog/' + project_name + '.v'
layout_path = project_path + '/netlist/lvs/' + self.layout + '.spi'
net_path = project_path + '/netlist/schem/' + self.schematic + '.spi'
layout_src = project_path + '/layout/' + self.layout + '.mag'
# Does the setup file exist (this is optional)?
if self.lvs_setup != '' and not os.path.isfile('setup.tcl'):
print('No technology setup file selected.')
# Does schematic netlist exist?
if not os.path.isfile(vlog_path) and not os.path.isfile(net_path):
print('Error: No schematic netlist or verilog netlist.')
return
# Does LVS netlist subdirectory exist?
if not os.path.exists(project_path + '/netlist/lvs'):
os.makedirs(project_path + '/netlist/lvs')
# Does layout netlist exist and is it current?
if not self.generate_layout_netlist(layout_path, layout_src, project_path):
return False
# Final check
if not os.path.isfile(layout_path):
print('Error: No netlist generated from magic.')
return
else:
# Read in netlist and convert commas from [X,Y] arrays to vertical bars
# as something that can be converted back as necessary. ngspice treats
# commas as special characters for some reason.
with open(layout_path) as ifile:
spitext = ifile.read()
# spilines = spitext.replace(',', '|')
# with open(layout_path, 'w') as ofile:
# ofile.write(spilines)
# Check the netlist to see if the cell to match is a subcircuit. If
# not, then assume it is the top level.
is_subckt = False
subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
dutlines = spitext.replace('\n+', ' ').splitlines()
for line in dutlines:
lmatch = subrex.match(line)
if lmatch:
subname = lmatch.group(1)
if subname == self.layout:
is_subckt = True
break
if is_subckt:
layout_arg = layout_path + ' ' + self.layout
layout_text = '"' + layout_arg + '"'
else:
layout_arg = layout_path
layout_text = layout_arg
if has_vlog:
schem_arg = vlog_path + ' ' + self.schematic
else:
schem_arg = net_path + ' ' + self.schematic
schem_text = '"' + schem_arg + '"'
# Remove any previous comparison output file
comp_out_path = os.path.splitext(comp_path)[0] + '.out'
if os.path.exists(comp_out_path):
os.remove(comp_out_path)
# Run netgen as subprocess
print('Running: netgen -batch lvs ' + layout_text +
' ' + schem_text + ' ' + self.lvs_setup + ' ' + comp_out_path +
' -json -blackbox')
# Note: Because arguments to subprocess are list items, the {filename cell}
# pair does *not* have to be quoted or braced. Doing so causes a parse
# error.
self.lvsproc = subprocess.Popen(['netgen', '-batch', 'lvs',
layout_arg, schem_arg,
self.lvs_setup, comp_out_path, '-json', '-blackbox'],
cwd=project_path + '/layout',
stdout=subprocess.PIPE, stderr=subprocess.PIPE, bufsize=0)
# This is largely unnecessary as netgen usually runs to completion very quickly.
self.watchclock(comp_path)
def watchclock(self, filename):
if self.lvsproc == None:
return
lvs_status = self.lvsproc.poll()
sresult = select.select([self.lvsproc.stdout, self.lvsproc.stderr], [], [], 0)[0]
if self.lvsproc.stdout in sresult:
outstring = self.lvsproc.stdout.readline().decode().strip()
self.logprint(outstring, doflush=True)
print(outstring)
elif self.lvsproc.stderr in sresult:
errstring = self.lvsproc.stderr.readline().decode().strip()
self.logprint(errstring, doflush = True)
print(errstring, file=sys.stderr)
if lvs_status != None:
print("netgen LVS exited with status " + str(lvs_status))
self.lvsproc = None
if lvs_status != 0:
print('Errors encountered in LVS.')
self.logprint('Errors in LVS, lvs status = ' + str(lvs_status), doflush=True)
# Done; now read comp.json and fill the treeview listbox.
self.generate(filename)
else:
self.after(500, lambda: self.watchclock(filename))
# Generate display from "comp.out" file (json file now preferred)
def generate_orig(self, lvspath):
lefttext = []
righttext = []
print("Reading LVS output file " + lvspath)
if os.path.exists(lvspath):
with open(lvspath, 'r') as ifile:
lvslines = ifile.read().splitlines()
for line in lvslines:
if '|' in line:
# parts = line.split('|')
# lefttext.append(parts[0])
# righttext.append(parts[1])
lefttext.append(line[0:42].strip())
righttext.append(line[44:].strip())
else:
lefttext.append(line)
righttext.append('')
# Populate treeview with text
self.toppane.lvsreport.repopulate(lefttext, righttext)
else:
print("Error: No output file generated from LVS.")
# Generate output from LVS report JSON file comp.json
def generate(self, lvspath):
lefttext = []
righttext = []
print("Reading LVS output file " + lvspath)
if os.path.exists(lvspath):
with open(lvspath, 'r') as ifile:
self.lvsdata = json.load(ifile)
# Populate treeview with text
self.toppane.lvsreport.json_repopulate(self.lvsdata)
else:
print("Error: No output file generated from LVS.")
def findrecord(self, value):
print("Unimplemented function")
def findrecord_test(self, value):
# Check if socket is defined; if not, attempt to open one
if not self.msock:
try:
self.msock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
except:
print("No response from layout tool.")
if self.msock:
self.msock.connect(("0.0.0.0", 12946))
self.msock.setblocking(False)
if self.msock:
# Pull name of net or device from 'value'
# This is a test:
self.msock.sendall(b'box 0 0 100 100\r\n')
if __name__ == '__main__':
options = []
arguments = []
for item in sys.argv[1:]:
if item.find('-', 0) == 0:
options.append(item)
else:
arguments.append(item)
root = tkinter.Tk()
app = LVSManager(root)
if arguments:
if len(arguments) >= 2:
app.set_project(arguments[0], project_name=arguments[1])
else:
app.set_project(arguments[0])
root.mainloop()

View File

@ -343,7 +343,7 @@ class LVSManager(ttk.Frame):
techbase = os.path.split(techname)[1]
self.tech = os.path.splitext(techbase)[0]
self.lvs_setup = techname
self.toppane.title2_frame.layout_select.config(text = self.tech)
self.toppane.title2_frame.tech_select.config(text = self.tech)
def choose_layout(self):
try:
@ -358,30 +358,37 @@ class LVSManager(ttk.Frame):
title = "Choose a layout cell to compare.")
if cellname != '':
print("Selected compare cell " + cellname)
self.layout = cellname
cellbase = os.path.split(cellname)[1]
self.layout = os.path.splitext(cellbase)[0]
self.toppane.title2_frame.layout_select.config(text = self.layout)
layoutname = os.path.splitext(cellbase)[0]
self.toppane.title2_frame.layout_select.config(text = layoutname)
fileext = os.path.splitext(cellbase)[1]
if fileext == '.mag':
self.toppane.title2_frame.layout_label.config(text = 'Layout:')
else:
self.toppane.title2_frame.layout_label.config(text = 'Layout netlist:')
def choose_netlist(self):
try:
project_path = self.rootpath
initdirname = self.rootpath + '/netlist/' + self.project + '.spi'
initdirname = self.rootpath + '/netlist/' + self.project + '.spice'
except:
print('Must choose a project first.')
return
cellname = filedialog.askopenfilename(multiple=False,
initialdir = initdirname,
filetypes = (("Spice netlist", "*.spi"),("Verilog netlist", "*.v")),
filetypes = (("Spice netlist", "*.spice"),("Verilog netlist", "*.v"),("All Files","*.*")),
title = "Choose a netlist to compare.")
if cellname != '':
print("Selected compare cell " + cellname)
self.schematic = cellname
cellbase = os.path.split(cellname)[1]
self.schematic = os.path.splitext(cellbase)[0]
self.toppane.title2_frame.schem_select.config(text = self.schematic)
schematic_name = os.path.splitext(cellbase)[0]
self.toppane.title2_frame.schem_select.config(text = schematic_name)
fileext = os.path.splitext(cellbase)[1]
if fileext == '.v':
self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
elif fileext == '.sp' or fileext == '.spi' or fileext == '.spice' or fileext == '.spc' or fileext == '.ckt':
elif fileext == '.sp' or fileext == '.spice' or fileext == '.spi' or fileext == '.spc' or fileext == '.ckt':
self.toppane.title2_frame.schem_label.config(text = 'SPICE netlist:')
elif fileext == '.cdl':
self.toppane.title2_frame.schem_label.config(text = 'CDL netlist:')
@ -433,7 +440,10 @@ class LVSManager(ttk.Frame):
self.logfile = None
# Put new log file called 'lvs.log' in the mag/ subdirectory
self.logfile = open(rootpath + '/layout/lvs.log', 'w')
if os.path.exists(rootpath + '/layout'):
self.logfile = open(rootpath + '/layout/lvs.log', 'w')
else:
self.logfile = open(rootpath + '/lvs.log', 'w')
# Print some initial information to the logfile.
self.logprint('Starting new log file ' + datetime.datetime.now().strftime('%c'),
doflush=True)
@ -444,15 +454,23 @@ class LVSManager(ttk.Frame):
# Cell name is the same as project name initially
self.layout = self.project
self.schematic = self.project
self.toppane.title2_frame.layout_select.config(text = self.layout)
self.toppane.title2_frame.schem_select.config(text = self.schematic)
layname = os.path.splitext(os.path.split(self.layout)[1])[0]
self.toppane.title2_frame.layout_select.config(text = layname)
schemname = os.path.splitext(os.path.split(self.schematic)[1])[0]
self.toppane.title2_frame.schem_select.config(text = schemname)
# Update schematic button
if os.path.isfile(rootpath + '/verilog/' + self.schematic + '.v'):
if os.path.splitext(self.schematic)[1] == '.v':
self.toppane.title2_frame.schem_label.config(text = 'Verilog netlist:')
else:
self.toppane.title2_frame.schem_label.config(text = 'Schematic netlist:')
# Update layout button
if os.path.splitext(self.layout)[1] == '.mag':
self.toppane.title2_frame.schem_label.config(text = 'Layout:')
else:
self.toppane.title2_frame.schem_label.config(text = 'Layout netlist:')
# If there is a comparison file that post-dates both netlists, load it.
self.check_lvs()
return True
@ -567,8 +585,8 @@ class LVSManager(ttk.Frame):
# load LVS results from comp.json
project_path = self.rootpath
project_name = self.project
layout_path = project_path + '/layout/' + project_name + '.spc'
net_path = project_path + '/netlist/' + project_name + '.spi'
layout_path = project_path + '/layout/' + project_name + '.spice'
net_path = project_path + '/netlist/' + project_name + '.spice'
comp_path = project_path + '/layout/comp.json'
if os.path.exists(layout_path) and os.path.exists(net_path) and os.path.exists(comp_path):
@ -599,7 +617,7 @@ class LVSManager(ttk.Frame):
mproc.stdin.write("ext2spice cthresh infinite\n")
mproc.stdin.write("ext2spice rthresh infinite\n")
mproc.stdin.write("ext2spice blackbox on\n")
mproc.stdin.write("ext2spice -o " + self.layout + ".spi\n")
mproc.stdin.write("ext2spice -o " + self.layout + ".spice\n")
mproc.stdin.write("quit -noprompt\n")
magicout = mproc.communicate()[0]
self.printwarn(magicout)
@ -607,8 +625,8 @@ class LVSManager(ttk.Frame):
print('Failure to generate new layout netlist.')
return False
# Move .spi netlist to project_dir/netlist/lvs/
shutil.move(project_path + '/layout/' + self.layout + '.spi', layout_path)
# Move .spice netlist to project_dir/netlist/lvs/
shutil.move(project_path + '/layout/' + self.layout + '.spice', layout_path)
# Remove extraction files
for file in os.listdir(project_path + '/layout'):
if os.path.splitext(file)[1] == '.ext':
@ -625,17 +643,37 @@ class LVSManager(ttk.Frame):
project_path = self.rootpath
project_name = self.project
comp_path = project_path + '/layout/comp.json'
# Diagnostic:
print('project_name is ' + project_name)
print('project_path is ' + project_path)
print('self.layout is ' + self.layout)
print('self.schematic is ' + self.schematic)
print('self.lvs_setup is ' + self.lvs_setup)
has_vlog = False
vlog_path = project_path + '/verilog/' + project_name + '.v'
layout_path = project_path + '/netlist/lvs/' + self.layout + '.spi'
net_path = project_path + '/netlist/schem/' + self.schematic + '.spi'
layout_src = project_path + '/layout/' + self.layout + '.mag'
if os.path.isfile(self.layout):
layout_path = self.layout
layout_src = None
else:
layout_path = project_path + '/netlist/lvs/' + self.layout + '.spice'
layout_src = project_path + '/layout/' + self.layout + '.mag'
comp_dir = os.path.split(layout_path)[0]
comp_path = comp_dir + '/comp.json'
if os.path.isfile(self.schematic):
net_path = self.schematic
else:
net_path = project_path + '/netlist/schem/' + self.schematic + '.spice'
# Does the setup file exist (this is optional)?
if self.lvs_setup != '' and not os.path.isfile('setup.tcl'):
if self.lvs_setup == '' and not os.path.isfile('setup.tcl'):
print('No technology setup file selected.')
elif not os.path.isfile(self.lvs_setup):
print("Can't find technology setup file " + self.lvs_setup)
# Does schematic netlist exist?
if not os.path.isfile(vlog_path) and not os.path.isfile(net_path):
@ -643,14 +681,16 @@ class LVSManager(ttk.Frame):
return
# Does LVS netlist subdirectory exist?
if not os.path.exists(project_path + '/netlist/lvs'):
os.makedirs(project_path + '/netlist/lvs')
if os.path.exists(project_path + '/netlist'):
if not os.path.exists(project_path + '/netlist/lvs'):
os.makedirs(project_path + '/netlist/lvs')
# Does layout netlist exist and is it current?
if not self.generate_layout_netlist(layout_path, layout_src, project_path):
return False
if layout_src:
if not self.generate_layout_netlist(layout_path, layout_src, project_path):
return False
# Final check
# Final checks
if not os.path.isfile(layout_path):
print('Error: No netlist generated from magic.')
return
@ -662,26 +702,27 @@ class LVSManager(ttk.Frame):
with open(layout_path) as ifile:
spitext = ifile.read()
# spilines = spitext.replace(',', '|')
# with open(layout_path, 'w') as ofile:
# ofile.write(spilines)
# Check the netlist to see if the cell to match is a subcircuit. If
# not, then assume it is the top level.
layoutcell = os.path.splitext(os.path.split(self.layout)[1])[0]
is_subckt = False
subname = None
subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
dutlines = spitext.replace('\n+', ' ').splitlines()
for line in dutlines:
lmatch = subrex.match(line)
if lmatch:
subname = lmatch.group(1)
if subname == self.layout:
if subname == layoutcell:
is_subckt = True
break
if is_subckt:
layout_arg = layout_path + ' ' + self.layout
layout_arg = self.layout + ' ' + layoutcell
layout_text = '"' + layout_arg + '"'
elif subname:
layout_arg = self.layout + ' ' + subname
layout_text = '"' + layout_arg + '"'
else:
layout_arg = layout_path
@ -690,8 +731,39 @@ class LVSManager(ttk.Frame):
if has_vlog:
schem_arg = vlog_path + ' ' + self.schematic
else:
schem_arg = net_path + ' ' + self.schematic
schem_text = '"' + schem_arg + '"'
# Final checks
if not os.path.isfile(net_path):
print('Error: No netlist from schematic.')
return
with open(net_path) as ifile:
spitext = ifile.read()
# Check the netlist to see if the cell to match is a subcircuit. If
# not, then assume it is the top level.
schemcell = os.path.splitext(os.path.split(self.schematic)[1])[0]
subname = None
is_subckt = False
subrex = re.compile('^[^\*]*[ \t]*.subckt[ \t]+([^ \t]+).*$', re.IGNORECASE)
dutlines = spitext.replace('\n+', ' ').splitlines()
for line in dutlines:
lmatch = subrex.match(line)
if lmatch:
subname = lmatch.group(1)
if subname == schemcell:
is_subckt = True
break
if is_subckt:
schem_arg = self.schematic + ' ' + schemcell
schem_text = '"' + schem_arg + '"'
elif subname:
schem_arg = self.schematic + ' ' + subname
schem_text = '"' + schem_arg + '"'
else:
schem_arg = net_path
schem_text = schem_arg
# Remove any previous comparison output file
comp_out_path = os.path.splitext(comp_path)[0] + '.out'
@ -708,7 +780,7 @@ class LVSManager(ttk.Frame):
self.lvsproc = subprocess.Popen(['netgen', '-batch', 'lvs',
layout_arg, schem_arg,
self.lvs_setup, comp_out_path, '-json', '-blackbox'],
cwd=project_path + '/layout',
cwd=comp_dir,
stdout=subprocess.PIPE, stderr=subprocess.PIPE, bufsize=0)
# This is largely unnecessary as netgen usually runs to completion very quickly.
self.watchclock(comp_path)

1117
scripts/config.guess vendored

File diff suppressed because it is too large Load Diff

View File

@ -1,772 +0,0 @@
This file contains any messages produced by compilers while
running configure, to aid debugging if configure makes a mistake.
It was created by netgen configure 1.3, which was
generated by GNU Autoconf 2.69. Invocation command line was
$ ./configure
## --------- ##
## Platform. ##
## --------- ##
hostname = stravinsky
uname -m = x86_64
uname -r = 4.1.13-100.fc21.x86_64
uname -s = Linux
uname -v = #1 SMP Tue Nov 10 13:13:20 UTC 2015
/usr/bin/uname -p = x86_64
/bin/uname -X = unknown
/bin/arch = x86_64
/usr/bin/arch -k = unknown
/usr/convex/getsysinfo = unknown
/usr/bin/hostinfo = unknown
/bin/machine = unknown
/usr/bin/oslevel = unknown
/bin/universe = unknown
PATH: .
PATH: /bin
PATH: /sbin
PATH: /usr/bin
PATH: /usr/sbin
PATH: /usr/local/bin
## ----------- ##
## Core tests. ##
## ----------- ##
configure:2398: checking build system type
configure:2412: result: x86_64-unknown-linux-gnu
configure:2432: checking host system type
configure:2445: result: x86_64-unknown-linux-gnu
configure:2465: checking target system type
configure:2478: result: x86_64-unknown-linux-gnu
configure:2569: checking for gcc
configure:2585: found /bin/gcc
configure:2596: result: gcc
configure:2825: checking for C compiler version
configure:2834: gcc --version >&5
gcc (GCC) 4.9.2 20150212 (Red Hat 4.9.2-6)
Copyright (C) 2014 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
configure:2845: $? = 0
configure:2834: gcc -v >&5
Using built-in specs.
COLLECT_GCC=gcc
COLLECT_LTO_WRAPPER=/usr/libexec/gcc/x86_64-redhat-linux/4.9.2/lto-wrapper
Target: x86_64-redhat-linux
Configured with: ../configure --prefix=/usr --mandir=/usr/share/man --infodir=/usr/share/info --with-bugurl=http://bugzilla.redhat.com/bugzilla --enable-bootstrap --enable-shared --enable-threads=posix --enable-checking=release --enable-multilib --with-system-zlib --enable-__cxa_atexit --disable-libunwind-exceptions --enable-gnu-unique-object --enable-linker-build-id --with-linker-hash-style=gnu --enable-languages=c,c++,objc,obj-c++,fortran,ada,go,lto --enable-plugin --enable-initfini-array --disable-libgcj --with-isl=/builddir/build/BUILD/gcc-4.9.2-20150212/obj-x86_64-redhat-linux/isl-install --with-cloog=/builddir/build/BUILD/gcc-4.9.2-20150212/obj-x86_64-redhat-linux/cloog-install --enable-gnu-indirect-function --with-tune=generic --with-arch_32=i686 --build=x86_64-redhat-linux
Thread model: posix
gcc version 4.9.2 20150212 (Red Hat 4.9.2-6) (GCC)
configure:2845: $? = 0
configure:2834: gcc -V >&5
gcc: error: unrecognized command line option '-V'
gcc: fatal error: no input files
compilation terminated.
configure:2845: $? = 4
configure:2834: gcc -qversion >&5
gcc: error: unrecognized command line option '-qversion'
gcc: fatal error: no input files
compilation terminated.
configure:2845: $? = 4
configure:2865: checking whether the C compiler works
configure:2887: gcc -g conftest.c >&5
configure:2891: $? = 0
configure:2939: result: yes
configure:2942: checking for C compiler default output file name
configure:2944: result: a.out
configure:2950: checking for suffix of executables
configure:2957: gcc -o conftest -g conftest.c >&5
configure:2961: $? = 0
configure:2983: result:
configure:3005: checking whether we are cross compiling
configure:3013: gcc -o conftest -g conftest.c >&5
configure:3017: $? = 0
configure:3024: ./conftest
configure:3028: $? = 0
configure:3043: result: no
configure:3048: checking for suffix of object files
configure:3070: gcc -c -g conftest.c >&5
configure:3074: $? = 0
configure:3095: result: o
configure:3099: checking whether we are using the GNU C compiler
configure:3118: gcc -c -g conftest.c >&5
configure:3118: $? = 0
configure:3127: result: yes
configure:3136: checking whether gcc accepts -g
configure:3156: gcc -c -g conftest.c >&5
configure:3156: $? = 0
configure:3197: result: yes
configure:3214: checking for gcc option to accept ISO C89
configure:3277: gcc -c -g conftest.c >&5
configure:3277: $? = 0
configure:3290: result: none needed
configure:3315: checking how to run the C preprocessor
configure:3346: gcc -E conftest.c
configure:3346: $? = 0
configure:3360: gcc -E conftest.c
conftest.c:11:28: fatal error: ac_nonexistent.h: No such file or directory
#include <ac_nonexistent.h>
^
compilation terminated.
configure:3360: $? = 1
configure: failed program was:
| /* confdefs.h */
| #define PACKAGE_NAME "netgen"
| #define PACKAGE_TARNAME "netgen"
| #define PACKAGE_VERSION "1.3"
| #define PACKAGE_STRING "netgen 1.3"
| #define PACKAGE_BUGREPORT "eda-dev@opencircuitdesign.com"
| #define PACKAGE_URL ""
| #define NETGEN_VERSION "1.5"
| #define NETGEN_REVISION "112"
| /* end confdefs.h. */
| #include <ac_nonexistent.h>
configure:3385: result: gcc -E
configure:3405: gcc -E conftest.c
configure:3405: $? = 0
configure:3419: gcc -E conftest.c
conftest.c:11:28: fatal error: ac_nonexistent.h: No such file or directory
#include <ac_nonexistent.h>
^
compilation terminated.
configure:3419: $? = 1
configure: failed program was:
| /* confdefs.h */
| #define PACKAGE_NAME "netgen"
| #define PACKAGE_TARNAME "netgen"
| #define PACKAGE_VERSION "1.3"
| #define PACKAGE_STRING "netgen 1.3"
| #define PACKAGE_BUGREPORT "eda-dev@opencircuitdesign.com"
| #define PACKAGE_URL ""
| #define NETGEN_VERSION "1.5"
| #define NETGEN_REVISION "112"
| /* end confdefs.h. */
| #include <ac_nonexistent.h>
configure:3448: checking for library containing strerror
configure:3479: gcc -o conftest -g conftest.c >&5
configure:3479: $? = 0
configure:3496: result: none required
configure:3518: checking for a BSD-compatible install
configure:3586: result: /bin/install -c
configure:3640: checking for ranlib
configure:3656: found /bin/ranlib
configure:3667: result: ranlib
configure:3694: checking for gm4
configure:3727: result: no
configure:3694: checking for gnum4
configure:3727: result: no
configure:3694: checking for m4
configure:3712: found /bin/m4
configure:3724: result: /bin/m4
configure:3765: checking for ld used by GCC
configure:3828: result: /bin/ld
configure:3835: checking if the linker (/bin/ld) is GNU ld
GNU ld version 2.24
configure:3847: result: yes
configure:3854: checking for grep that handles long lines and -e
configure:3912: result: /bin/grep
configure:3917: checking for egrep
configure:3979: result: /bin/grep -E
configure:3984: checking for ANSI C header files
configure:4004: gcc -c -g conftest.c >&5
configure:4004: $? = 0
configure:4077: gcc -o conftest -g conftest.c >&5
configure:4077: $? = 0
configure:4077: ./conftest
configure:4077: $? = 0
configure:4088: result: yes
configure:4101: checking for sys/types.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4101: checking for sys/stat.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4101: checking for stdlib.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4101: checking for string.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4101: checking for memory.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4101: checking for strings.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4101: checking for inttypes.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4101: checking for stdint.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4101: checking for unistd.h
configure:4101: gcc -c -g conftest.c >&5
configure:4101: $? = 0
configure:4101: result: yes
configure:4117: checking size of void *
configure:4122: gcc -o conftest -g conftest.c >&5
configure:4122: $? = 0
configure:4122: ./conftest
configure:4122: $? = 0
configure:4136: result: 8
configure:4150: checking size of unsigned int
configure:4155: gcc -o conftest -g conftest.c >&5
configure:4155: $? = 0
configure:4155: ./conftest
configure:4155: $? = 0
configure:4169: result: 4
configure:4183: checking size of unsigned long
configure:4188: gcc -o conftest -g conftest.c >&5
configure:4188: $? = 0
configure:4188: ./conftest
configure:4188: $? = 0
configure:4202: result: 8
configure:4216: checking size of unsigned long long
configure:4221: gcc -o conftest -g conftest.c >&5
configure:4221: $? = 0
configure:4221: ./conftest
configure:4221: $? = 0
configure:4235: result: 8
configure:4246: checking whether byte ordering is bigendian
configure:4261: gcc -c -g conftest.c >&5
conftest.c:26:9: error: unknown type name 'not'
not a universal capable compiler
^
conftest.c:26:15: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'universal'
not a universal capable compiler
^
conftest.c:26:15: error: unknown type name 'universal'
configure:4261: $? = 1
configure: failed program was:
| /* confdefs.h */
| #define PACKAGE_NAME "netgen"
| #define PACKAGE_TARNAME "netgen"
| #define PACKAGE_VERSION "1.3"
| #define PACKAGE_STRING "netgen 1.3"
| #define PACKAGE_BUGREPORT "eda-dev@opencircuitdesign.com"
| #define PACKAGE_URL ""
| #define NETGEN_VERSION "1.5"
| #define NETGEN_REVISION "112"
| #define STDC_HEADERS 1
| #define HAVE_SYS_TYPES_H 1
| #define HAVE_SYS_STAT_H 1
| #define HAVE_STDLIB_H 1
| #define HAVE_STRING_H 1
| #define HAVE_MEMORY_H 1
| #define HAVE_STRINGS_H 1
| #define HAVE_INTTYPES_H 1
| #define HAVE_STDINT_H 1
| #define HAVE_UNISTD_H 1
| #define SIZEOF_VOID_P 8
| #define SIZEOF_UNSIGNED_INT 4
| #define SIZEOF_UNSIGNED_LONG 8
| #define SIZEOF_UNSIGNED_LONG_LONG 8
| /* end confdefs.h. */
| #ifndef __APPLE_CC__
| not a universal capable compiler
| #endif
| typedef int dummy;
|
configure:4306: gcc -c -g conftest.c >&5
configure:4306: $? = 0
configure:4324: gcc -c -g conftest.c >&5
conftest.c: In function 'main':
conftest.c:32:4: error: unknown type name 'not'
not big endian
^
conftest.c:32:12: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'endian'
not big endian
^
configure:4324: $? = 1
configure: failed program was:
| /* confdefs.h */
| #define PACKAGE_NAME "netgen"
| #define PACKAGE_TARNAME "netgen"
| #define PACKAGE_VERSION "1.3"
| #define PACKAGE_STRING "netgen 1.3"
| #define PACKAGE_BUGREPORT "eda-dev@opencircuitdesign.com"
| #define PACKAGE_URL ""
| #define NETGEN_VERSION "1.5"
| #define NETGEN_REVISION "112"
| #define STDC_HEADERS 1
| #define HAVE_SYS_TYPES_H 1
| #define HAVE_SYS_STAT_H 1
| #define HAVE_STDLIB_H 1
| #define HAVE_STRING_H 1
| #define HAVE_MEMORY_H 1
| #define HAVE_STRINGS_H 1
| #define HAVE_INTTYPES_H 1
| #define HAVE_STDINT_H 1
| #define HAVE_UNISTD_H 1
| #define SIZEOF_VOID_P 8
| #define SIZEOF_UNSIGNED_INT 4
| #define SIZEOF_UNSIGNED_LONG 8
| #define SIZEOF_UNSIGNED_LONG_LONG 8
| /* end confdefs.h. */
| #include <sys/types.h>
| #include <sys/param.h>
|
| int
| main ()
| {
| #if BYTE_ORDER != BIG_ENDIAN
| not big endian
| #endif
|
| ;
| return 0;
| }
configure:4452: result: no
configure:4471: checking for ANSI C header files
configure:4575: result: yes
configure:4587: checking for setenv
configure:4587: gcc -o conftest -g conftest.c >&5
configure:4587: $? = 0
configure:4587: result: yes
configure:4587: checking for putenv
configure:4587: gcc -o conftest -g conftest.c >&5
configure:4587: $? = 0
configure:4587: result: yes
configure:4597: checking for vfork
configure:4597: gcc -o conftest -g conftest.c >&5
configure:4597: $? = 0
configure:4597: result: yes
configure:4605: checking dirent.h usability
configure:4605: gcc -c -g conftest.c >&5
configure:4605: $? = 0
configure:4605: result: yes
configure:4605: checking dirent.h presence
configure:4605: gcc -E -x c conftest.c
configure:4605: $? = 0
configure:4605: result: yes
configure:4605: checking for dirent.h
configure:4605: result: yes
configure:4618: checking limits.h usability
configure:4618: gcc -c -g conftest.c >&5
configure:4618: $? = 0
configure:4618: result: yes
configure:4618: checking limits.h presence
configure:4618: gcc -E -x c conftest.c
configure:4618: $? = 0
configure:4618: result: yes
configure:4618: checking for limits.h
configure:4618: result: yes
configure:4631: checking param.h usability
configure:4631: gcc -c -g conftest.c >&5
conftest.c:63:19: fatal error: param.h: No such file or directory
#include <param.h>
^
compilation terminated.
configure:4631: $? = 1
configure: failed program was:
| /* confdefs.h */
| #define PACKAGE_NAME "netgen"
| #define PACKAGE_TARNAME "netgen"
| #define PACKAGE_VERSION "1.3"
| #define PACKAGE_STRING "netgen 1.3"
| #define PACKAGE_BUGREPORT "eda-dev@opencircuitdesign.com"
| #define PACKAGE_URL ""
| #define NETGEN_VERSION "1.5"
| #define NETGEN_REVISION "112"
| #define STDC_HEADERS 1
| #define HAVE_SYS_TYPES_H 1
| #define HAVE_SYS_STAT_H 1
| #define HAVE_STDLIB_H 1
| #define HAVE_STRING_H 1
| #define HAVE_MEMORY_H 1
| #define HAVE_STRINGS_H 1
| #define HAVE_INTTYPES_H 1
| #define HAVE_STDINT_H 1
| #define HAVE_UNISTD_H 1
| #define SIZEOF_VOID_P 8
| #define SIZEOF_UNSIGNED_INT 4
| #define SIZEOF_UNSIGNED_LONG 8
| #define SIZEOF_UNSIGNED_LONG_LONG 8
| #define STDC_HEADERS 1
| #define HAVE_SETENV 1
| #define HAVE_PUTENV 1
| #define HAVE_DIRENT_H 1
| #define HAVE_LIMITS_H 1
| /* end confdefs.h. */
| #include <stdio.h>
| #ifdef HAVE_SYS_TYPES_H
| # include <sys/types.h>
| #endif
| #ifdef HAVE_SYS_STAT_H
| # include <sys/stat.h>
| #endif
| #ifdef STDC_HEADERS
| # include <stdlib.h>
| # include <stddef.h>
| #else
| # ifdef HAVE_STDLIB_H
| # include <stdlib.h>
| # endif
| #endif
| #ifdef HAVE_STRING_H
| # if !defined STDC_HEADERS && defined HAVE_MEMORY_H
| # include <memory.h>
| # endif
| # include <string.h>
| #endif
| #ifdef HAVE_STRINGS_H
| # include <strings.h>
| #endif
| #ifdef HAVE_INTTYPES_H
| # include <inttypes.h>
| #endif
| #ifdef HAVE_STDINT_H
| # include <stdint.h>
| #endif
| #ifdef HAVE_UNISTD_H
| # include <unistd.h>
| #endif
| #include <param.h>
configure:4631: result: no
configure:4631: checking param.h presence
configure:4631: gcc -E -x c conftest.c
conftest.c:30:19: fatal error: param.h: No such file or directory
#include <param.h>
^
compilation terminated.
configure:4631: $? = 1
configure: failed program was:
| /* confdefs.h */
| #define PACKAGE_NAME "netgen"
| #define PACKAGE_TARNAME "netgen"
| #define PACKAGE_VERSION "1.3"
| #define PACKAGE_STRING "netgen 1.3"
| #define PACKAGE_BUGREPORT "eda-dev@opencircuitdesign.com"
| #define PACKAGE_URL ""
| #define NETGEN_VERSION "1.5"
| #define NETGEN_REVISION "112"
| #define STDC_HEADERS 1
| #define HAVE_SYS_TYPES_H 1
| #define HAVE_SYS_STAT_H 1
| #define HAVE_STDLIB_H 1
| #define HAVE_STRING_H 1
| #define HAVE_MEMORY_H 1
| #define HAVE_STRINGS_H 1
| #define HAVE_INTTYPES_H 1
| #define HAVE_STDINT_H 1
| #define HAVE_UNISTD_H 1
| #define SIZEOF_VOID_P 8
| #define SIZEOF_UNSIGNED_INT 4
| #define SIZEOF_UNSIGNED_LONG 8
| #define SIZEOF_UNSIGNED_LONG_LONG 8
| #define STDC_HEADERS 1
| #define HAVE_SETENV 1
| #define HAVE_PUTENV 1
| #define HAVE_DIRENT_H 1
| #define HAVE_LIMITS_H 1
| /* end confdefs.h. */
| #include <param.h>
configure:4631: result: no
configure:4631: checking for param.h
configure:4631: result: no
configure:4644: checking for python3
configure:4660: found /bin/python3
configure:4672: result: yes
configure:4681: checking for va_copy
configure:4699: gcc -o conftest -g conftest.c >&5
configure:4699: $? = 0
configure:4708: result: yes
configure:4716: checking for __va_copy
configure:4734: gcc -o conftest -g conftest.c >&5
configure:4734: $? = 0
configure:4743: result: yes
configure:4874: checking for tclConfig.sh
configure:4946: result: /usr/lib64/tclConfig.sh
configure:4962: checking for tkConfig.sh
configure:5035: result: /usr/lib64/tkConfig.sh
configure:5168: checking for wish executable
configure:5195: result: /usr/bin/wish
configure:5201: checking for tclsh executable
configure:5227: result: /usr/bin/tclsh
configure:5350: checking for X
configure:5489: gcc -o conftest -g conftest.c -lX11 >&5
configure:5489: $? = 0
configure:5539: result: libraries , headers
configure:5638: gcc -o conftest -g conftest.c -lX11 >&5
configure:5638: $? = 0
configure:5736: checking for gethostbyname
configure:5736: gcc -o conftest -g conftest.c >&5
configure:5736: $? = 0
configure:5736: result: yes
configure:5833: checking for connect
configure:5833: gcc -o conftest -g conftest.c >&5
configure:5833: $? = 0
configure:5833: result: yes
configure:5882: checking for remove
configure:5882: gcc -o conftest -g conftest.c >&5
configure:5882: $? = 0
configure:5882: result: yes
configure:5931: checking for shmat
configure:5931: gcc -o conftest -g conftest.c >&5
configure:5931: $? = 0
configure:5931: result: yes
configure:5989: checking for IceConnectionNumber in -lICE
configure:6014: gcc -o conftest -g conftest.c -lICE >&5
configure:6014: $? = 0
configure:6023: result: yes
configure:6745: creating ./config.status
## ---------------------- ##
## Running config.status. ##
## ---------------------- ##
This file was extended by netgen config.status 1.3, which was
generated by GNU Autoconf 2.69. Invocation command line was
CONFIG_FILES =
CONFIG_HEADERS =
CONFIG_LINKS =
CONFIG_COMMANDS =
$ ./config.status
on stravinsky
config.status:784: creating defs.mak
config.status:887: WARNING: 'defs.mak.in' seems to ignore the --datarootdir setting
## ---------------- ##
## Cache variables. ##
## ---------------- ##
ac_cv_build=x86_64-unknown-linux-gnu
ac_cv_c___va_copy=yes
ac_cv_c_bigendian=no
ac_cv_c_compiler_gnu=yes
ac_cv_c_va_copy=yes
ac_cv_env_CC_set=
ac_cv_env_CC_value=
ac_cv_env_CFLAGS_set=set
ac_cv_env_CFLAGS_value=-g
ac_cv_env_CPPFLAGS_set=
ac_cv_env_CPPFLAGS_value=
ac_cv_env_CPP_set=
ac_cv_env_CPP_value=
ac_cv_env_LDFLAGS_set=
ac_cv_env_LDFLAGS_value=
ac_cv_env_LIBS_set=
ac_cv_env_LIBS_value=
ac_cv_env_XMKMF_set=
ac_cv_env_XMKMF_value=
ac_cv_env_build_alias_set=
ac_cv_env_build_alias_value=
ac_cv_env_host_alias_set=
ac_cv_env_host_alias_value=
ac_cv_env_target_alias_set=
ac_cv_env_target_alias_value=
ac_cv_func_connect=yes
ac_cv_func_gethostbyname=yes
ac_cv_func_putenv=yes
ac_cv_func_remove=yes
ac_cv_func_setenv=yes
ac_cv_func_shmat=yes
ac_cv_func_vfork=yes
ac_cv_have_x='have_x=yes ac_x_includes='\'''\'' ac_x_libraries='\'''\'''
ac_cv_header_dirent_h=yes
ac_cv_header_inttypes_h=yes
ac_cv_header_limits_h=yes
ac_cv_header_memory_h=yes
ac_cv_header_param_h=no
ac_cv_header_stdc=yes
ac_cv_header_stdint_h=yes
ac_cv_header_stdlib_h=yes
ac_cv_header_string_h=yes
ac_cv_header_strings_h=yes
ac_cv_header_sys_stat_h=yes
ac_cv_header_sys_types_h=yes
ac_cv_header_unistd_h=yes
ac_cv_host=x86_64-unknown-linux-gnu
ac_cv_lib_ICE_IceConnectionNumber=yes
ac_cv_objext=o
ac_cv_path_EGREP='/bin/grep -E'
ac_cv_path_GREP=/bin/grep
ac_cv_path_LD=/bin/ld
ac_cv_path_M4=/bin/m4
ac_cv_path_install='/bin/install -c'
ac_cv_prog_CPP='gcc -E'
ac_cv_prog_HAVE_PYTHON3=yes
ac_cv_prog_ac_ct_CC=gcc
ac_cv_prog_ac_ct_RANLIB=ranlib
ac_cv_prog_cc_c89=
ac_cv_prog_cc_g=yes
ac_cv_prog_gnu_ld=yes
ac_cv_search_strerror='none required'
ac_cv_sizeof_unsigned_int=4
ac_cv_sizeof_unsigned_long=8
ac_cv_sizeof_unsigned_long_long=8
ac_cv_sizeof_void_p=8
ac_cv_target=x86_64-unknown-linux-gnu
## ----------------- ##
## Output variables. ##
## ----------------- ##
ALL_TARGET='tcl'
CC='gcc'
CFLAGS='-g -m64 -fPIC'
CPP='gcc -E -x c'
CPPFLAGS=''
DEFS='-DPACKAGE_NAME=\"netgen\" -DPACKAGE_TARNAME=\"netgen\" -DPACKAGE_VERSION=\"1.3\" -DPACKAGE_STRING=\"netgen\ 1.3\" -DPACKAGE_BUGREPORT=\"eda-dev@opencircuitdesign.com\" -DPACKAGE_URL=\"\" -DNETGEN_VERSION=\"1.5\" -DNETGEN_REVISION=\"112\" -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DSIZEOF_VOID_P=8 -DSIZEOF_UNSIGNED_INT=4 -DSIZEOF_UNSIGNED_LONG=8 -DSIZEOF_UNSIGNED_LONG_LONG=8 -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DHAVE_DIRENT_H=1 -DHAVE_LIMITS_H=1 -DHAVE_VA_COPY=1 -DHAVE___VA_COPY=1 -DDBUG_OFF=1 -DTCL_NETGEN=1 -Dlinux=1 -DSYSV=1 -DISC=1'
DEPEND_FLAG='-MM'
ECHO_C=''
ECHO_N='printf'
ECHO_T=''
EGREP='/bin/grep -E'
EXEEXT=''
EXTRA_LIB_SPECS='-ldl'
GREP='/bin/grep'
HAVE_PYTHON3='yes'
INC_SPECS=''
INSTALL_DATA='${INSTALL} -m 644'
INSTALL_PROGRAM='${INSTALL}'
INSTALL_SCRIPT='${INSTALL}'
INSTALL_TARGET='install-tcl'
LD='/bin/ld'
LDDL_FLAGS=' -shared -Wl,-soname,$@ -Wl,--version-script=${NETGENDIR}/netgen/symbol.map'
LDFLAGS=''
LD_RUN_PATH=''
LIBOBJS=''
LIBS=''
LIB_SPECS=' -L/usr/lib64 -ltkstub8.6 -L/usr/lib64 -ltclstub8.6'
LIB_SPECS_NOSTUB=' -L/usr/lib64 -ltk8.6 -L/usr/lib64 -ltcl8.6'
LTLIBOBJS=''
M4='/bin/m4'
OBJEXT='o'
PACKAGE='netgen'
PACKAGE_BUGREPORT='eda-dev@opencircuitdesign.com'
PACKAGE_NAME='netgen'
PACKAGE_STRING='netgen 1.3'
PACKAGE_TARNAME='netgen'
PACKAGE_URL=''
PACKAGE_VERSION='1.3'
PATH_SEPARATOR=':'
RANLIB='ranlib'
SCRIPTS=''
SHDLIB_EXT='.so'
SHELL='/bin/sh'
SHLIB_CFLAGS='-fPIC'
SHLIB_LD=''
SHLIB_LIB_SPECS=''
TCLSH_EXE='/usr/bin/tclsh'
TCL_LIB_DIR='/usr/lib'
VERSION=''
WISH_EXE='/usr/bin/wish'
XMKMF=''
X_CFLAGS=''
X_EXTRA_LIBS=''
X_LIBS=''
X_PRE_LIBS=' -lSM -lICE'
ac_ct_CC='gcc'
bindir='${exec_prefix}/bin'
build='x86_64-unknown-linux-gnu'
build_alias=''
build_cpu='x86_64'
build_os='linux-gnu'
build_vendor='unknown'
cadinstall=' tcltk'
datadir='${datarootdir}'
datarootdir='${prefix}/share'
docdir='${datarootdir}/doc/${PACKAGE_TARNAME}'
dvidir='${docdir}'
exec_prefix='${prefix}'
extra_defs=' -DCAD_DIR=\"${LIBDIR}\" -DTCL_DIR=\"${TCLDIR}\"'
extra_libs=' ${NETGENDIR}/tcltk/libtcltk.o'
gr_cflags=''
gr_dflags=' -DX11 -DXLIB'
gr_libs=' -lX11'
gr_srcs=' ${TK_SRCS}'
host='x86_64-unknown-linux-gnu'
host_alias=''
host_cpu='x86_64'
host_os='linux-gnu'
host_vendor='unknown'
htmldir='${docdir}'
includedir='${prefix}/include'
infodir='${datarootdir}/info'
ld_extra_libs=''
ld_extra_objs=''
libdir='${exec_prefix}/lib'
libexecdir='${exec_prefix}/libexec'
localedir='${datarootdir}/locale'
localstatedir='${prefix}/var'
mandir='${datarootdir}/man'
modules=' tcltk'
oldincludedir='/usr/include'
pdfdir='${docdir}'
prefix='/usr/local'
program_transform_name='s,x,x,'
programs=' tcltk'
psdir='${docdir}'
sbindir='${exec_prefix}/sbin'
sharedstatedir='${prefix}/com'
stub_defs=' -DUSE_TCL_STUBS -DUSE_TK_STUBS'
sub_extra_libs=''
sysconfdir='${prefix}/etc'
target='x86_64-unknown-linux-gnu'
target_alias=''
target_cpu='x86_64'
target_os='linux-gnu'
target_vendor='unknown'
top_extra_libs=''
unused=''
## ----------- ##
## confdefs.h. ##
## ----------- ##
/* confdefs.h */
#define PACKAGE_NAME "netgen"
#define PACKAGE_TARNAME "netgen"
#define PACKAGE_VERSION "1.3"
#define PACKAGE_STRING "netgen 1.3"
#define PACKAGE_BUGREPORT "eda-dev@opencircuitdesign.com"
#define PACKAGE_URL ""
#define NETGEN_VERSION "1.5"
#define NETGEN_REVISION "112"
#define STDC_HEADERS 1
#define HAVE_SYS_TYPES_H 1
#define HAVE_SYS_STAT_H 1
#define HAVE_STDLIB_H 1
#define HAVE_STRING_H 1
#define HAVE_MEMORY_H 1
#define HAVE_STRINGS_H 1
#define HAVE_INTTYPES_H 1
#define HAVE_STDINT_H 1
#define HAVE_UNISTD_H 1
#define SIZEOF_VOID_P 8
#define SIZEOF_UNSIGNED_INT 4
#define SIZEOF_UNSIGNED_LONG 8
#define SIZEOF_UNSIGNED_LONG_LONG 8
#define STDC_HEADERS 1
#define HAVE_SETENV 1
#define HAVE_PUTENV 1
#define HAVE_DIRENT_H 1
#define HAVE_LIMITS_H 1
#define HAVE_VA_COPY 1
#define HAVE___VA_COPY 1
#define DBUG_OFF 1
#define TCL_NETGEN 1
#define linux 1
#define SYSV 1
#define ISC 1
configure: exit 0

View File

@ -1,941 +0,0 @@
#! /bin/sh
# Generated by configure.
# Run this file to recreate the current configuration.
# Compiler output produced by configure, useful for debugging
# configure, is in config.log if it exists.
debug=false
ac_cs_recheck=false
ac_cs_silent=false
SHELL=${CONFIG_SHELL-/bin/sh}
export SHELL
## -------------------- ##
## M4sh Initialization. ##
## -------------------- ##
# Be more Bourne compatible
DUALCASE=1; export DUALCASE # for MKS sh
if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then :
emulate sh
NULLCMD=:
# Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
# is contrary to our usage. Disable this feature.
alias -g '${1+"$@"}'='"$@"'
setopt NO_GLOB_SUBST
else
case `(set -o) 2>/dev/null` in #(
*posix*) :
set -o posix ;; #(
*) :
;;
esac
fi
as_nl='
'
export as_nl
# Printing a long string crashes Solaris 7 /usr/bin/printf.
as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo
as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo
# Prefer a ksh shell builtin over an external printf program on Solaris,
# but without wasting forks for bash or zsh.
if test -z "$BASH_VERSION$ZSH_VERSION" \
&& (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then
as_echo='print -r --'
as_echo_n='print -rn --'
elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then
as_echo='printf %s\n'
as_echo_n='printf %s'
else
if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then
as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"'
as_echo_n='/usr/ucb/echo -n'
else
as_echo_body='eval expr "X$1" : "X\\(.*\\)"'
as_echo_n_body='eval
arg=$1;
case $arg in #(
*"$as_nl"*)
expr "X$arg" : "X\\(.*\\)$as_nl";
arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;;
esac;
expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl"
'
export as_echo_n_body
as_echo_n='sh -c $as_echo_n_body as_echo'
fi
export as_echo_body
as_echo='sh -c $as_echo_body as_echo'
fi
# The user is always right.
if test "${PATH_SEPARATOR+set}" != set; then
PATH_SEPARATOR=:
(PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && {
(PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 ||
PATH_SEPARATOR=';'
}
fi
# IFS
# We need space, tab and new line, in precisely that order. Quoting is
# there to prevent editors from complaining about space-tab.
# (If _AS_PATH_WALK were called with IFS unset, it would disable word
# splitting by setting IFS to empty value.)
IFS=" "" $as_nl"
# Find who we are. Look in the path if we contain no directory separator.
as_myself=
case $0 in #((
*[\\/]* ) as_myself=$0 ;;
*) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
for as_dir in $PATH
do
IFS=$as_save_IFS
test -z "$as_dir" && as_dir=.
test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
done
IFS=$as_save_IFS
;;
esac
# We did not find ourselves, most probably we were run as `sh COMMAND'
# in which case we are not to be found in the path.
if test "x$as_myself" = x; then
as_myself=$0
fi
if test ! -f "$as_myself"; then
$as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
exit 1
fi
# Unset variables that we do not need and which cause bugs (e.g. in
# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1"
# suppresses any "Segmentation fault" message there. '((' could
# trigger a bug in pdksh 5.2.14.
for as_var in BASH_ENV ENV MAIL MAILPATH
do eval test x\${$as_var+set} = xset \
&& ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || :
done
PS1='$ '
PS2='> '
PS4='+ '
# NLS nuisances.
LC_ALL=C
export LC_ALL
LANGUAGE=C
export LANGUAGE
# CDPATH.
(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
# as_fn_error STATUS ERROR [LINENO LOG_FD]
# ----------------------------------------
# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
# provided, also output the error to LOG_FD, referencing LINENO. Then exit the
# script with STATUS, using 1 if that was 0.
as_fn_error ()
{
as_status=$1; test $as_status -eq 0 && as_status=1
if test "$4"; then
as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
$as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4
fi
$as_echo "$as_me: error: $2" >&2
as_fn_exit $as_status
} # as_fn_error
# as_fn_set_status STATUS
# -----------------------
# Set $? to STATUS, without forking.
as_fn_set_status ()
{
return $1
} # as_fn_set_status
# as_fn_exit STATUS
# -----------------
# Exit the shell with STATUS, even in a "trap 0" or "set -e" context.
as_fn_exit ()
{
set +e
as_fn_set_status $1
exit $1
} # as_fn_exit
# as_fn_unset VAR
# ---------------
# Portably unset VAR.
as_fn_unset ()
{
{ eval $1=; unset $1;}
}
as_unset=as_fn_unset
# as_fn_append VAR VALUE
# ----------------------
# Append the text in VALUE to the end of the definition contained in VAR. Take
# advantage of any shell optimizations that allow amortized linear growth over
# repeated appends, instead of the typical quadratic growth present in naive
# implementations.
if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then :
eval 'as_fn_append ()
{
eval $1+=\$2
}'
else
as_fn_append ()
{
eval $1=\$$1\$2
}
fi # as_fn_append
# as_fn_arith ARG...
# ------------------
# Perform arithmetic evaluation on the ARGs, and store the result in the
# global $as_val. Take advantage of shells that can avoid forks. The arguments
# must be portable across $(()) and expr.
if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then :
eval 'as_fn_arith ()
{
as_val=$(( $* ))
}'
else
as_fn_arith ()
{
as_val=`expr "$@" || test $? -eq 1`
}
fi # as_fn_arith
if expr a : '\(a\)' >/dev/null 2>&1 &&
test "X`expr 00001 : '.*\(...\)'`" = X001; then
as_expr=expr
else
as_expr=false
fi
if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then
as_basename=basename
else
as_basename=false
fi
if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then
as_dirname=dirname
else
as_dirname=false
fi
as_me=`$as_basename -- "$0" ||
$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
X"$0" : 'X\(//\)$' \| \
X"$0" : 'X\(/\)' \| . 2>/dev/null ||
$as_echo X/"$0" |
sed '/^.*\/\([^/][^/]*\)\/*$/{
s//\1/
q
}
/^X\/\(\/\/\)$/{
s//\1/
q
}
/^X\/\(\/\).*/{
s//\1/
q
}
s/.*/./; q'`
# Avoid depending upon Character Ranges.
as_cr_letters='abcdefghijklmnopqrstuvwxyz'
as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
as_cr_Letters=$as_cr_letters$as_cr_LETTERS
as_cr_digits='0123456789'
as_cr_alnum=$as_cr_Letters$as_cr_digits
ECHO_C= ECHO_N= ECHO_T=
case `echo -n x` in #(((((
-n*)
case `echo 'xy\c'` in
*c*) ECHO_T=' ';; # ECHO_T is single tab character.
xy) ECHO_C='\c';;
*) echo `echo ksh88 bug on AIX 6.1` > /dev/null
ECHO_T=' ';;
esac;;
*)
ECHO_N='-n';;
esac
rm -f conf$$ conf$$.exe conf$$.file
if test -d conf$$.dir; then
rm -f conf$$.dir/conf$$.file
else
rm -f conf$$.dir
mkdir conf$$.dir 2>/dev/null
fi
if (echo >conf$$.file) 2>/dev/null; then
if ln -s conf$$.file conf$$ 2>/dev/null; then
as_ln_s='ln -s'
# ... but there are two gotchas:
# 1) On MSYS, both `ln -s file dir' and `ln file dir' fail.
# 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable.
# In both cases, we have to default to `cp -pR'.
ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe ||
as_ln_s='cp -pR'
elif ln conf$$.file conf$$ 2>/dev/null; then
as_ln_s=ln
else
as_ln_s='cp -pR'
fi
else
as_ln_s='cp -pR'
fi
rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file
rmdir conf$$.dir 2>/dev/null
# as_fn_mkdir_p
# -------------
# Create "$as_dir" as a directory, including parents if necessary.
as_fn_mkdir_p ()
{
case $as_dir in #(
-*) as_dir=./$as_dir;;
esac
test -d "$as_dir" || eval $as_mkdir_p || {
as_dirs=
while :; do
case $as_dir in #(
*\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'(
*) as_qdir=$as_dir;;
esac
as_dirs="'$as_qdir' $as_dirs"
as_dir=`$as_dirname -- "$as_dir" ||
$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
X"$as_dir" : 'X\(//\)[^/]' \| \
X"$as_dir" : 'X\(//\)$' \| \
X"$as_dir" : 'X\(/\)' \| . 2>/dev/null ||
$as_echo X"$as_dir" |
sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
s//\1/
q
}
/^X\(\/\/\)[^/].*/{
s//\1/
q
}
/^X\(\/\/\)$/{
s//\1/
q
}
/^X\(\/\).*/{
s//\1/
q
}
s/.*/./; q'`
test -d "$as_dir" && break
done
test -z "$as_dirs" || eval "mkdir $as_dirs"
} || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir"
} # as_fn_mkdir_p
if mkdir -p . 2>/dev/null; then
as_mkdir_p='mkdir -p "$as_dir"'
else
test -d ./-p && rmdir ./-p
as_mkdir_p=false
fi
# as_fn_executable_p FILE
# -----------------------
# Test if FILE is an executable regular file.
as_fn_executable_p ()
{
test -f "$1" && test -x "$1"
} # as_fn_executable_p
as_test_x='test -x'
as_executable_p=as_fn_executable_p
# Sed expression to map a string onto a valid CPP name.
as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
# Sed expression to map a string onto a valid variable name.
as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
exec 6>&1
## ----------------------------------- ##
## Main body of $CONFIG_STATUS script. ##
## ----------------------------------- ##
# Save the log message, to keep $0 and so on meaningful, and to
# report actual input values of CONFIG_FILES etc. instead of their
# values after options handling.
ac_log="
This file was extended by netgen $as_me 1.3, which was
generated by GNU Autoconf 2.69. Invocation command line was
CONFIG_FILES = $CONFIG_FILES
CONFIG_HEADERS = $CONFIG_HEADERS
CONFIG_LINKS = $CONFIG_LINKS
CONFIG_COMMANDS = $CONFIG_COMMANDS
$ $0 $@
on `(hostname || uname -n) 2>/dev/null | sed 1q`
"
# Files that config.status was made for.
config_files=" defs.mak"
ac_cs_usage="\
\`$as_me' instantiates files and other configuration actions
from templates according to the current configuration. Unless the files
and actions are specified as TAGs, all are instantiated by default.
Usage: $0 [OPTION]... [TAG]...
-h, --help print this help, then exit
-V, --version print version number and configuration settings, then exit
--config print configuration, then exit
-q, --quiet, --silent
do not print progress messages
-d, --debug don't remove temporary files
--recheck update $as_me by reconfiguring in the same conditions
--file=FILE[:TEMPLATE]
instantiate the configuration file FILE
Configuration files:
$config_files
Report bugs to <eda-dev@opencircuitdesign.com>."
ac_cs_config="'CFLAGS=-g'"
ac_cs_version="\
netgen config.status 1.3
configured by ./configure, generated by GNU Autoconf 2.69,
with options \"$ac_cs_config\"
Copyright (C) 2012 Free Software Foundation, Inc.
This config.status script is free software; the Free Software Foundation
gives unlimited permission to copy, distribute and modify it."
ac_pwd='/home/tim/gitsrc/netgen-1.5/scripts'
srcdir='..'
INSTALL='/bin/install -c'
test -n "$AWK" || AWK=awk
# The default lists apply if the user does not specify any file.
ac_need_defaults=:
while test $# != 0
do
case $1 in
--*=?*)
ac_option=`expr "X$1" : 'X\([^=]*\)='`
ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'`
ac_shift=:
;;
--*=)
ac_option=`expr "X$1" : 'X\([^=]*\)='`
ac_optarg=
ac_shift=:
;;
*)
ac_option=$1
ac_optarg=$2
ac_shift=shift
;;
esac
case $ac_option in
# Handling of the options.
-recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
ac_cs_recheck=: ;;
--version | --versio | --versi | --vers | --ver | --ve | --v | -V )
$as_echo "$ac_cs_version"; exit ;;
--config | --confi | --conf | --con | --co | --c )
$as_echo "$ac_cs_config"; exit ;;
--debug | --debu | --deb | --de | --d | -d )
debug=: ;;
--file | --fil | --fi | --f )
$ac_shift
case $ac_optarg in
*\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;;
'') as_fn_error $? "missing file argument" ;;
esac
as_fn_append CONFIG_FILES " '$ac_optarg'"
ac_need_defaults=false;;
--he | --h | --help | --hel | -h )
$as_echo "$ac_cs_usage"; exit ;;
-q | -quiet | --quiet | --quie | --qui | --qu | --q \
| -silent | --silent | --silen | --sile | --sil | --si | --s)
ac_cs_silent=: ;;
# This is an error.
-*) as_fn_error $? "unrecognized option: \`$1'
Try \`$0 --help' for more information." ;;
*) as_fn_append ac_config_targets " $1"
ac_need_defaults=false ;;
esac
shift
done
ac_configure_extra_args=
if $ac_cs_silent; then
exec 6>/dev/null
ac_configure_extra_args="$ac_configure_extra_args --silent"
fi
if $ac_cs_recheck; then
set X /bin/sh './configure' 'CFLAGS=-g' $ac_configure_extra_args --no-create --no-recursion
shift
$as_echo "running CONFIG_SHELL=/bin/sh $*" >&6
CONFIG_SHELL='/bin/sh'
export CONFIG_SHELL
exec "$@"
fi
exec 5>>config.log
{
echo
sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX
## Running $as_me. ##
_ASBOX
$as_echo "$ac_log"
} >&5
# Handling of arguments.
for ac_config_target in $ac_config_targets
do
case $ac_config_target in
"defs.mak") CONFIG_FILES="$CONFIG_FILES defs.mak" ;;
*) as_fn_error $? "invalid argument: \`$ac_config_target'" "$LINENO" 5;;
esac
done
# If the user did not use the arguments to specify the items to instantiate,
# then the envvar interface is used. Set only those that are not.
# We use the long form for the default assignment because of an extremely
# bizarre bug on SunOS 4.1.3.
if $ac_need_defaults; then
test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files
fi
# Have a temporary directory for convenience. Make it in the build tree
# simply because there is no reason against having it here, and in addition,
# creating and moving files from /tmp can sometimes cause problems.
# Hook for its removal unless debugging.
# Note that there is a small window in which the directory will not be cleaned:
# after its creation but before its name has been assigned to `$tmp'.
$debug ||
{
tmp= ac_tmp=
trap 'exit_status=$?
: "${ac_tmp:=$tmp}"
{ test ! -d "$ac_tmp" || rm -fr "$ac_tmp"; } && exit $exit_status
' 0
trap 'as_fn_exit 1' 1 2 13 15
}
# Create a (secure) tmp directory for tmp files.
{
tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` &&
test -d "$tmp"
} ||
{
tmp=./conf$$-$RANDOM
(umask 077 && mkdir "$tmp")
} || as_fn_error $? "cannot create a temporary directory in ." "$LINENO" 5
ac_tmp=$tmp
# Set up the scripts for CONFIG_FILES section.
# No need to generate them if there are no CONFIG_FILES.
# This happens for instance with `./config.status config.h'.
if test -n "$CONFIG_FILES"; then
ac_cr=`echo X | tr X '\015'`
# On cygwin, bash can eat \r inside `` if the user requested igncr.
# But we know of no other shell where ac_cr would be empty at this
# point, so we can use a bashism as a fallback.
if test "x$ac_cr" = x; then
eval ac_cr=\$\'\\r\'
fi
ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' </dev/null 2>/dev/null`
if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then
ac_cs_awk_cr='\\r'
else
ac_cs_awk_cr=$ac_cr
fi
echo 'BEGIN {' >"$ac_tmp/subs1.awk" &&
cat >>"$ac_tmp/subs1.awk" <<\_ACAWK &&
S["LTLIBOBJS"]=""
S["LIBOBJS"]=""
S["INSTALL_TARGET"]="install-tcl"
S["ALL_TARGET"]="tcl"
S["LD_RUN_PATH"]=""
S["SHLIB_CFLAGS"]="-fPIC"
S["DEPEND_FLAG"]="-MM"
S["gr_srcs"]=" ${TK_SRCS}"
S["gr_libs"]=" -lX11"
S["gr_dflags"]=" -DX11 -DXLIB"
S["gr_cflags"]=""
S["cadinstall"]=" tcltk"
S["programs"]=" tcltk"
S["unused"]=""
S["modules"]=" tcltk"
S["sub_extra_libs"]=""
S["top_extra_libs"]=""
S["ld_extra_objs"]=""
S["ld_extra_libs"]=""
S["stub_defs"]=" -DUSE_TCL_STUBS -DUSE_TK_STUBS"
S["extra_defs"]=" -DCAD_DIR=\\\"${LIBDIR}\\\" -DTCL_DIR=\\\"${TCLDIR}\\\""
S["extra_libs"]=" ${NETGENDIR}/tcltk/libtcltk.o"
S["SCRIPTS"]=""
S["PACKAGE"]="netgen"
S["VERSION"]=""
S["TCL_LIB_DIR"]="/usr/lib"
S["TCLSH_EXE"]="/usr/bin/tclsh"
S["WISH_EXE"]="/usr/bin/wish"
S["LIB_SPECS_NOSTUB"]=" -L/usr/lib64 -ltk8.6 -L/usr/lib64 -ltcl8.6"
S["LIB_SPECS"]=" -L/usr/lib64 -ltkstub8.6 -L/usr/lib64 -ltclstub8.6"
S["INC_SPECS"]=""
S["EXTRA_LIB_SPECS"]="-ldl"
S["SHLIB_LIB_SPECS"]=""
S["LDDL_FLAGS"]=" -shared -Wl,-soname,$@ -Wl,--version-script=${NETGENDIR}/netgen/symbol.map"
S["LD"]="/bin/ld"
S["SHLIB_LD"]=""
S["SHDLIB_EXT"]=".so"
S["X_EXTRA_LIBS"]=""
S["X_LIBS"]=""
S["X_PRE_LIBS"]=" -lSM -lICE"
S["X_CFLAGS"]=""
S["XMKMF"]=""
S["HAVE_PYTHON3"]="yes"
S["EGREP"]="/bin/grep -E"
S["GREP"]="/bin/grep"
S["M4"]="/bin/m4"
S["RANLIB"]="ranlib"
S["INSTALL_DATA"]="${INSTALL} -m 644"
S["INSTALL_SCRIPT"]="${INSTALL}"
S["INSTALL_PROGRAM"]="${INSTALL}"
S["CPP"]="gcc -E -x c"
S["OBJEXT"]="o"
S["EXEEXT"]=""
S["ac_ct_CC"]="gcc"
S["CPPFLAGS"]=""
S["LDFLAGS"]=""
S["CFLAGS"]="-g -m64 -fPIC"
S["CC"]="gcc"
S["target_os"]="linux-gnu"
S["target_vendor"]="unknown"
S["target_cpu"]="x86_64"
S["target"]="x86_64-unknown-linux-gnu"
S["host_os"]="linux-gnu"
S["host_vendor"]="unknown"
S["host_cpu"]="x86_64"
S["host"]="x86_64-unknown-linux-gnu"
S["build_os"]="linux-gnu"
S["build_vendor"]="unknown"
S["build_cpu"]="x86_64"
S["build"]="x86_64-unknown-linux-gnu"
S["target_alias"]=""
S["host_alias"]=""
S["build_alias"]=""
S["LIBS"]=""
S["ECHO_T"]=""
S["ECHO_N"]="-n"
S["ECHO_C"]=""
S["DEFS"]="-DPACKAGE_NAME=\\\"netgen\\\" -DPACKAGE_TARNAME=\\\"netgen\\\" -DPACKAGE_VERSION=\\\"1.3\\\" -DPACKAGE_STRING=\\\"netgen\\ 1.3\\\" -DPACKAGE_BUGREPORT=\\\"eda-dev@open"\
"circuitdesign.com\\\" -DPACKAGE_URL=\\\"\\\" -DNETGEN_VERSION=\\\"1.5\\\" -DNETGEN_REVISION=\\\"112\\\" -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 "\
"-DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DSIZEOF_VOID_P=8 -"\
"DSIZEOF_UNSIGNED_INT=4 -DSIZEOF_UNSIGNED_LONG=8 -DSIZEOF_UNSIGNED_LONG_LONG=8 -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DHAVE_DIRENT_H=1 -DH"\
"AVE_LIMITS_H=1 -DHAVE_VA_COPY=1 -DHAVE___VA_COPY=1 -DDBUG_OFF=1 -DTCL_NETGEN=1 -Dlinux=1 -DSYSV=1 -DISC=1"
S["mandir"]="${datarootdir}/man"
S["localedir"]="${datarootdir}/locale"
S["libdir"]="${exec_prefix}/lib"
S["psdir"]="${docdir}"
S["pdfdir"]="${docdir}"
S["dvidir"]="${docdir}"
S["htmldir"]="${docdir}"
S["infodir"]="${datarootdir}/info"
S["docdir"]="${datarootdir}/doc/${PACKAGE_TARNAME}"
S["oldincludedir"]="/usr/include"
S["includedir"]="${prefix}/include"
S["localstatedir"]="${prefix}/var"
S["sharedstatedir"]="${prefix}/com"
S["sysconfdir"]="${prefix}/etc"
S["datadir"]="${datarootdir}"
S["datarootdir"]="${prefix}/share"
S["libexecdir"]="${exec_prefix}/libexec"
S["sbindir"]="${exec_prefix}/sbin"
S["bindir"]="${exec_prefix}/bin"
S["program_transform_name"]="s,x,x,"
S["prefix"]="/usr/local"
S["exec_prefix"]="${prefix}"
S["PACKAGE_URL"]=""
S["PACKAGE_BUGREPORT"]="eda-dev@opencircuitdesign.com"
S["PACKAGE_STRING"]="netgen 1.3"
S["PACKAGE_VERSION"]="1.3"
S["PACKAGE_TARNAME"]="netgen"
S["PACKAGE_NAME"]="netgen"
S["PATH_SEPARATOR"]=":"
S["SHELL"]="/bin/sh"
_ACAWK
cat >>"$ac_tmp/subs1.awk" <<_ACAWK &&
for (key in S) S_is_set[key] = 1
FS = ""
}
{
line = $ 0
nfields = split(line, field, "@")
substed = 0
len = length(field[1])
for (i = 2; i < nfields; i++) {
key = field[i]
keylen = length(key)
if (S_is_set[key]) {
value = S[key]
line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3)
len += length(value) + length(field[++i])
substed = 1
} else
len += 1 + keylen
}
print line
}
_ACAWK
if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then
sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g"
else
cat
fi < "$ac_tmp/subs1.awk" > "$ac_tmp/subs.awk" \
|| as_fn_error $? "could not setup config files machinery" "$LINENO" 5
fi # test -n "$CONFIG_FILES"
eval set X " :F $CONFIG_FILES "
shift
for ac_tag
do
case $ac_tag in
:[FHLC]) ac_mode=$ac_tag; continue;;
esac
case $ac_mode$ac_tag in
:[FHL]*:*);;
:L* | :C*:*) as_fn_error $? "invalid tag \`$ac_tag'" "$LINENO" 5;;
:[FH]-) ac_tag=-:-;;
:[FH]*) ac_tag=$ac_tag:$ac_tag.in;;
esac
ac_save_IFS=$IFS
IFS=:
set x $ac_tag
IFS=$ac_save_IFS
shift
ac_file=$1
shift
case $ac_mode in
:L) ac_source=$1;;
:[FH])
ac_file_inputs=
for ac_f
do
case $ac_f in
-) ac_f="$ac_tmp/stdin";;
*) # Look for the file first in the build tree, then in the source tree
# (if the path is not absolute). The absolute path cannot be DOS-style,
# because $ac_f cannot contain `:'.
test -f "$ac_f" ||
case $ac_f in
[\\/$]*) false;;
*) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";;
esac ||
as_fn_error 1 "cannot find input file: \`$ac_f'" "$LINENO" 5;;
esac
case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac
as_fn_append ac_file_inputs " '$ac_f'"
done
# Let's still pretend it is `configure' which instantiates (i.e., don't
# use $as_me), people would be surprised to read:
# /* config.h. Generated by config.status. */
configure_input='Generated from '`
$as_echo "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g'
`' by configure.'
if test x"$ac_file" != x-; then
configure_input="$ac_file. $configure_input"
{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $ac_file" >&5
$as_echo "$as_me: creating $ac_file" >&6;}
fi
# Neutralize special characters interpreted by sed in replacement strings.
case $configure_input in #(
*\&* | *\|* | *\\* )
ac_sed_conf_input=`$as_echo "$configure_input" |
sed 's/[\\\\&|]/\\\\&/g'`;; #(
*) ac_sed_conf_input=$configure_input;;
esac
case $ac_tag in
*:-:* | *:-) cat >"$ac_tmp/stdin" \
|| as_fn_error $? "could not create $ac_file" "$LINENO" 5 ;;
esac
;;
esac
ac_dir=`$as_dirname -- "$ac_file" ||
$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
X"$ac_file" : 'X\(//\)[^/]' \| \
X"$ac_file" : 'X\(//\)$' \| \
X"$ac_file" : 'X\(/\)' \| . 2>/dev/null ||
$as_echo X"$ac_file" |
sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
s//\1/
q
}
/^X\(\/\/\)[^/].*/{
s//\1/
q
}
/^X\(\/\/\)$/{
s//\1/
q
}
/^X\(\/\).*/{
s//\1/
q
}
s/.*/./; q'`
as_dir="$ac_dir"; as_fn_mkdir_p
ac_builddir=.
case "$ac_dir" in
.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;;
*)
ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'`
# A ".." for each directory in $ac_dir_suffix.
ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'`
case $ac_top_builddir_sub in
"") ac_top_builddir_sub=. ac_top_build_prefix= ;;
*) ac_top_build_prefix=$ac_top_builddir_sub/ ;;
esac ;;
esac
ac_abs_top_builddir=$ac_pwd
ac_abs_builddir=$ac_pwd$ac_dir_suffix
# for backward compatibility:
ac_top_builddir=$ac_top_build_prefix
case $srcdir in
.) # We are building in place.
ac_srcdir=.
ac_top_srcdir=$ac_top_builddir_sub
ac_abs_top_srcdir=$ac_pwd ;;
[\\/]* | ?:[\\/]* ) # Absolute name.
ac_srcdir=$srcdir$ac_dir_suffix;
ac_top_srcdir=$srcdir
ac_abs_top_srcdir=$srcdir ;;
*) # Relative name.
ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix
ac_top_srcdir=$ac_top_build_prefix$srcdir
ac_abs_top_srcdir=$ac_pwd/$srcdir ;;
esac
ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix
case $ac_mode in
:F)
#
# CONFIG_FILE
#
case $INSTALL in
[\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;;
*) ac_INSTALL=$ac_top_build_prefix$INSTALL ;;
esac
# If the template does not know about datarootdir, expand it.
# FIXME: This hack should be removed a few years after 2.60.
ac_datarootdir_hack=; ac_datarootdir_seen=
ac_sed_dataroot='
/datarootdir/ {
p
q
}
/@datadir@/p
/@docdir@/p
/@infodir@/p
/@localedir@/p
/@mandir@/p'
case `eval "sed -n \"\$ac_sed_dataroot\" $ac_file_inputs"` in
*datarootdir*) ac_datarootdir_seen=yes;;
*@datadir@*|*@docdir@*|*@infodir@*|*@localedir@*|*@mandir@*)
{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5
$as_echo "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;}
ac_datarootdir_hack='
s&@datadir@&${datarootdir}&g
s&@docdir@&${datarootdir}/doc/${PACKAGE_TARNAME}&g
s&@infodir@&${datarootdir}/info&g
s&@localedir@&${datarootdir}/locale&g
s&@mandir@&${datarootdir}/man&g
s&\${datarootdir}&${prefix}/share&g' ;;
esac
ac_sed_extra="
:t
/@[a-zA-Z_][a-zA-Z_0-9]*@/!b
s|@configure_input@|$ac_sed_conf_input|;t t
s&@top_builddir@&$ac_top_builddir_sub&;t t
s&@top_build_prefix@&$ac_top_build_prefix&;t t
s&@srcdir@&$ac_srcdir&;t t
s&@abs_srcdir@&$ac_abs_srcdir&;t t
s&@top_srcdir@&$ac_top_srcdir&;t t
s&@abs_top_srcdir@&$ac_abs_top_srcdir&;t t
s&@builddir@&$ac_builddir&;t t
s&@abs_builddir@&$ac_abs_builddir&;t t
s&@abs_top_builddir@&$ac_abs_top_builddir&;t t
s&@INSTALL@&$ac_INSTALL&;t t
$ac_datarootdir_hack
"
eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | $AWK -f "$ac_tmp/subs.awk" \
>$ac_tmp/out || as_fn_error $? "could not create $ac_file" "$LINENO" 5
test -z "$ac_datarootdir_hack$ac_datarootdir_seen" &&
{ ac_out=`sed -n '/\${datarootdir}/p' "$ac_tmp/out"`; test -n "$ac_out"; } &&
{ ac_out=`sed -n '/^[ ]*datarootdir[ ]*:*=/p' \
"$ac_tmp/out"`; test -z "$ac_out"; } &&
{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir'
which seems to be undefined. Please make sure it is defined" >&5
$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir'
which seems to be undefined. Please make sure it is defined" >&2;}
rm -f "$ac_tmp/stdin"
case $ac_file in
-) cat "$ac_tmp/out" && rm -f "$ac_tmp/out";;
*) rm -f "$ac_file" && mv "$ac_tmp/out" "$ac_file";;
esac \
|| as_fn_error $? "could not create $ac_file" "$LINENO" 5
;;
esac
done # for ac_tag
as_fn_exit 0

2917
scripts/config.sub vendored

File diff suppressed because it is too large Load Diff

100
scripts/configure vendored
View File

@ -633,6 +633,7 @@ gr_srcs
gr_libs
gr_dflags
gr_cflags
DIST_DIR
cadinstall
programs
unused
@ -667,7 +668,6 @@ XMKMF
HAVE_PYTHON3
EGREP
GREP
M4
RANLIB
INSTALL_DATA
INSTALL_SCRIPT
@ -711,6 +711,7 @@ infodir
docdir
oldincludedir
includedir
runstatedir
localstatedir
sharedstatedir
sysconfdir
@ -734,6 +735,7 @@ ac_subst_files=''
ac_user_opts='
enable_option_checking
with_gnu_ld
with_distdir
with_interpreter
with_tcl
with_tk
@ -792,6 +794,7 @@ datadir='${datarootdir}'
sysconfdir='${prefix}/etc'
sharedstatedir='${prefix}/com'
localstatedir='${prefix}/var'
runstatedir='${localstatedir}/run'
includedir='${prefix}/include'
oldincludedir='/usr/include'
docdir='${datarootdir}/doc/${PACKAGE_TARNAME}'
@ -1044,6 +1047,15 @@ do
| -silent | --silent | --silen | --sile | --sil)
silent=yes ;;
-runstatedir | --runstatedir | --runstatedi | --runstated \
| --runstate | --runstat | --runsta | --runst | --runs \
| --run | --ru | --r)
ac_prev=runstatedir ;;
-runstatedir=* | --runstatedir=* | --runstatedi=* | --runstated=* \
| --runstate=* | --runstat=* | --runsta=* | --runst=* | --runs=* \
| --run=* | --ru=* | --r=*)
runstatedir=$ac_optarg ;;
-sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
ac_prev=sbindir ;;
-sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
@ -1181,7 +1193,7 @@ fi
for ac_var in exec_prefix prefix bindir sbindir libexecdir datarootdir \
datadir sysconfdir sharedstatedir localstatedir includedir \
oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
libdir localedir mandir
libdir localedir mandir runstatedir
do
eval ac_val=\$$ac_var
# Remove trailing slashes.
@ -1334,6 +1346,7 @@ Fine tuning of the installation directories:
--sysconfdir=DIR read-only single-machine data [PREFIX/etc]
--sharedstatedir=DIR modifiable architecture-independent data [PREFIX/com]
--localstatedir=DIR modifiable single-machine data [PREFIX/var]
--runstatedir=DIR modifiable per-process data [LOCALSTATEDIR/run]
--libdir=DIR object code libraries [EPREFIX/lib]
--includedir=DIR C header files [PREFIX/include]
--oldincludedir=DIR C header files for non-gcc [/usr/include]
@ -1372,6 +1385,7 @@ Optional Packages:
--with-PACKAGE[=ARG] use PACKAGE [ARG=yes]
--without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no)
--with-gnu-ld assume the C compiler uses GNU ld [default=no]
--with-distdir=DIR install into location DIR for distribution
--with-interpreter=arg enable interpreter
--with-tcl=DIR Find tclConfig.sh in DIR
--with-tk=DIR Find tkConfig.sh in DIR
@ -3687,56 +3701,6 @@ else
fi
for ac_prog in gm4 gnum4 m4
do
# Extract the first word of "$ac_prog", so it can be a program name with args.
set dummy $ac_prog; ac_word=$2
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
$as_echo_n "checking for $ac_word... " >&6; }
if ${ac_cv_path_M4+:} false; then :
$as_echo_n "(cached) " >&6
else
case $M4 in
[\\/]* | ?:[\\/]*)
ac_cv_path_M4="$M4" # Let the user override the test with a path.
;;
*)
as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
for as_dir in $PATH
do
IFS=$as_save_IFS
test -z "$as_dir" && as_dir=.
for ac_exec_ext in '' $ac_executable_extensions; do
if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
ac_cv_path_M4="$as_dir/$ac_word$ac_exec_ext"
$as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
break 2
fi
done
done
IFS=$as_save_IFS
;;
esac
fi
M4=$ac_cv_path_M4
if test -n "$M4"; then
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $M4" >&5
$as_echo "$M4" >&6; }
else
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
$as_echo "no" >&6; }
fi
test -n "$M4" && break
done
test -n "$M4" || M4="no"
if test x$M4 = xno; then
as_fn_error $? "M4 is required" "$LINENO" 5
fi
if test "$CPP" = "$CC -E" ; then
CPP="$CPP -x c"
@ -4798,6 +4762,24 @@ usingTcl=1
usingX11=
# For distributed installs, where the run-time files are installed in a
# place that is a temporary staging area, like DESTDIR, but unlike DESTDIR,
# the prefix is replaced by the destination directory, rather than appended
# to it.
DIST_DIR="\${exec_prefix}"
# Check whether --with-distdir was given.
if test "${with_distdir+set}" = set; then :
withval=$with_distdir;
if test "$withval" = "no" -o "$withval" = "NO" ; then
DIST_DIR="\${exec_prefix}"
else
DIST_DIR=${withval}
fi
fi
# Check whether --with-interpreter was given.
if test "${with_interpreter+set}" = set; then :
@ -6044,7 +6026,6 @@ fi
if test $usingTcl ; then
usingX11=1
cadinstall="$cadinstall tcltk"
modules="$modules tcltk"
programs="$programs tcltk"
@ -6054,7 +6035,11 @@ if test $usingTcl ; then
extra_libs="$extra_libs \${NETGENDIR}/tcltk/libtcltk.o"
extra_defs="$extra_defs -DTCL_DIR=\\\"\${TCLDIR}\\\""
stub_defs="$stub_defs -DUSE_TCL_STUBS -DUSE_TK_STUBS"
if test $usingX11 ; then
stub_defs="$stub_defs -DUSE_TCL_STUBS"
else
stub_defs="$stub_defs -DUSE_TCL_STUBS -DUSE_TK_STUBS"
fi
else
programs="$programs netgen"
unused="$unused tcltk"
@ -6139,6 +6124,7 @@ if test $usingTcl ; then
# Tk libraries and header files
#
# -----------------------------------------------------------------------
if test $usingX11 ; then
if test "${TK_INC_DIR}" != "/usr/include" ; then
INC_SPECS="${INC_SPECS} -I${TK_INC_DIR}"
fi
@ -6155,6 +6141,7 @@ if test $usingTcl ; then
loader_run_path="${TK_LIB_DIR}:${loader_run_path}"
fi
fi
fi
# -----------------------------------------------------------------------
#
@ -6264,7 +6251,7 @@ if test $usingTcl ; then
*darwin*)
SHDLIB_EXT=".dylib"
LDDL_FLAGS="-dynamiclib -flat_namespace -undefined suppress -noprebind"
LDDL_FLAGS="-dynamiclib -undefined dynamic_lookup"
LDFLAGS="${LDFLAGS} ${LIB_SPECS}"
CFLAGS="${CFLAGS} ${X_CFLAGS} ${INC_SPECS} -I/sw/include -fno-common"
;;
@ -6413,7 +6400,7 @@ fi
# Not available on all versions: check for include file.
SHLIB_CFLAGS="-fpic"
LDDL_FLAGS="-shared ${LIB_SPECS}"
CFLAGS="${CFLAGS} -l/usr/X11R6/include"
CFLAGS="${CFLAGS} -L/usr/X11R6/include"
;;
*-netbsd*|*-openbsd*)
@ -6587,6 +6574,7 @@ fi
ac_config_files="$ac_config_files defs.mak"

View File

@ -26,12 +26,6 @@ AC_ISC_POSIX
AC_PROG_INSTALL
AC_PROG_RANLIB
dnl GNU M4 is preferred due to some of the option switches.
AC_PATH_PROGS([M4], [gm4 gnum4 m4], [no])
if test x$M4 = xno; then
AC_MSG_ERROR([M4 is required])
fi
dnl check size of pointer for correct behavior on 64-bit systems
dnl If the C preprocessor is GCC, we need to force the flag to
dnl assert that input files are of type C, or else the preprocessing
@ -249,6 +243,20 @@ usingX11=
dnl Compile-time options below. . .
# For distributed installs, where the run-time files are installed in a
# place that is a temporary staging area, like DESTDIR, but unlike DESTDIR,
# the prefix is replaced by the destination directory, rather than appended
# to it.
DIST_DIR="\${exec_prefix}"
AC_ARG_WITH(distdir,
[ --with-distdir=DIR install into location DIR for distribution], [
if test "$withval" = "no" -o "$withval" = "NO" ; then
DIST_DIR="\${exec_prefix}"
else
DIST_DIR=${withval}
fi
], )
AC_ARG_WITH(interpreter,
[ --with-interpreter=[arg] enable interpreter], [
if test "$withval" = "no" -o "$withval" = "NO"; then
@ -793,7 +801,6 @@ dnl "make" instead of requiring "make tcl"
dnl ----------------------------------------------------------------
if test $usingTcl ; then
usingX11=1
cadinstall="$cadinstall tcltk"
modules="$modules tcltk"
programs="$programs tcltk"
@ -802,7 +809,11 @@ if test $usingTcl ; then
AC_DEFINE(TCL_NETGEN)
extra_libs="$extra_libs \${NETGENDIR}/tcltk/libtcltk.o"
extra_defs="$extra_defs -DTCL_DIR=\\\"\${TCLDIR}\\\""
stub_defs="$stub_defs -DUSE_TCL_STUBS -DUSE_TK_STUBS"
if test $usingX11 ; then
stub_defs="$stub_defs -DUSE_TCL_STUBS"
else
stub_defs="$stub_defs -DUSE_TCL_STUBS -DUSE_TK_STUBS"
fi
else
programs="$programs netgen"
unused="$unused tcltk"
@ -889,6 +900,7 @@ if test $usingTcl ; then
# Tk libraries and header files
#
# -----------------------------------------------------------------------
if test $usingX11 ; then
if test "${TK_INC_DIR}" != "/usr/include" ; then
INC_SPECS="${INC_SPECS} -I${TK_INC_DIR}"
fi
@ -905,6 +917,7 @@ if test $usingTcl ; then
loader_run_path="${TK_LIB_DIR}:${loader_run_path}"
fi
fi
fi
# -----------------------------------------------------------------------
#
@ -1014,7 +1027,7 @@ if test $usingTcl ; then
*darwin*)
SHDLIB_EXT=".dylib"
LDDL_FLAGS="-dynamiclib -flat_namespace -undefined suppress -noprebind"
LDDL_FLAGS="-dynamiclib -undefined dynamic_lookup"
LDFLAGS="${LDFLAGS} ${LIB_SPECS}"
CFLAGS="${CFLAGS} ${X_CFLAGS} ${INC_SPECS} -I/sw/include -fno-common"
;;
@ -1120,7 +1133,7 @@ if test $usingTcl ; then
# Not available on all versions: check for include file.
SHLIB_CFLAGS="-fpic"
LDDL_FLAGS="-shared ${LIB_SPECS}"
CFLAGS="${CFLAGS} -l/usr/X11R6/include"
CFLAGS="${CFLAGS} -L/usr/X11R6/include"
;;
*-netbsd*|*-openbsd*)
@ -1272,6 +1285,7 @@ AC_SUBST(modules)
AC_SUBST(unused)
AC_SUBST(programs)
AC_SUBST(cadinstall)
AC_SUBST(DIST_DIR)
AC_SUBST(gr_cflags)
AC_SUBST(gr_dflags)

View File

@ -1,7 +1,7 @@
dnl Process this file with autoconf to produce a configure script.
dnl Use autoconf 2.52 or newer.
AC_INIT(netgen, 1.3, magic-hackers@csl.cornell.edu)
AC_INIT(netgen, 1.3, eda-dev@opencircuitdesign.com)
AC_PREREQ(2.52)
AC_CONFIG_SRCDIR(rules.mak)
AC_CONFIG_AUX_DIR(.)
@ -38,7 +38,7 @@ dnl assert that input files are of type C, or else the preprocessing
dnl stage will not execute correctly on the ".in" files in the scmos
dnl directory.
if test "$CPP" = "gcc -E" ; then
if test "$CPP" = "$CC -E" ; then
CPP="$CPP -x c"
fi
@ -163,6 +163,9 @@ AC_CHECK_HEADERS(limits.h)
dnl Check for <param.h>
AC_CHECK_HEADERS(param.h)
dnl Check for Python3
AC_CHECK_PROG(HAVE_PYTHON3, python3, yes, no)
dnl Check for va_copy
AC_CACHE_CHECK([for va_copy], ac_cv_c_va_copy,
AC_TRY_LINK(
@ -195,6 +198,7 @@ fi
# not ANSI-compliant and won't compile without quite a bit of work.
AC_DEFINE(DBUG_OFF)
stub_defs=""
extra_defs="$extra_defs -DCAD_DIR=\\\"\${LIBDIR}\\\""
X_LIBS=
X_CFLAGS=
@ -245,6 +249,20 @@ usingX11=
dnl Compile-time options below. . .
# For distributed installs, where the run-time files are installed in a
# place that is a temporary staging area, like DESTDIR, but unlike DESTDIR,
# the prefix is replaced by the destination directory, rather than appended
# to it.
DIST_DIR="\${exec_prefix}"
AC_ARG_WITH(distdir,
[ --with-distdir=DIR install into location DIR for distribution], [
if test "$withval" = "no" -o "$withval" = "NO" ; then
DIST_DIR="\${exec_prefix}"
else
DIST_DIR=${withval}
fi
], )
AC_ARG_WITH(interpreter,
[ --with-interpreter=[arg] enable interpreter], [
if test "$withval" = "no" -o "$withval" = "NO"; then
@ -329,7 +347,7 @@ if test $usingTcl ; then
# 1. Search previously named locations.
for dir in \
$prefix \
$ac_default_prefix \
$exec_prefix
do
if test -r "$dir/tclConfig.sh" ; then
@ -351,11 +369,10 @@ if test $usingTcl ; then
`ls -dr /usr/local/tcl/tcl[[7-9]].[[0-9]]* 2>/dev/null` \
/usr/local/tcl \
/usr/local/lib \
/usr/lib64 \
/usr/local \
`ls -dr /usr/lib/tcl[[7-9]].[[0-9]]* 2>/dev/null` \
/sw/lib \
/usr/lib \
/usr/lib64 \
/usr
do
if test -r "$dir/tclConfig.sh" ; then
@ -415,7 +432,7 @@ if test $usingTcl ; then
# 1. Search previously named locations.
#
for dir in \
$prefix \
$ac_default_prefix \
$exec_prefix
do
if test -r "$dir/tkConfig.sh" ; then
@ -434,21 +451,17 @@ if test $usingTcl ; then
#
if test "x$tk_config_sh" = "x" ; then
for dir in \
/usr/local \
/usr \
`ls -dr /usr/local/lib/tk[[7-9]].[[0-9]]* 2>/dev/null` \
`ls -dr /usr/lib/tk[[7-9]].[[0-9]]* 2>/dev/null` \
`ls -dr /usr/local/tk/tk[[7-9]].[[0-9]]* 2>/dev/null` \
`ls -dr /usr/local/tk[[7-9]].[[0-9]]* 2>/dev/null` \
/usr/local/tk \
`ls -dr /usr/local/lib/tcl[[7-9]].[[0-9]]* 2>/dev/null` \
`ls -dr /usr/lib/tcl/tk[[7-9]].[[0-9]]* 2>/dev/null` \
`ls -dr /usr/local/tcl/tcl[[7-9]].[[0-9]]* 2>/dev/null` \
`ls -dr /usr/share/tcltk/tk[[7-9]].[[0-9]]* 2>/dev/null` \
/sw/lib \
/usr/lib \
`ls -dr /usr/local/tk/tk[[7-9]].[[0-9]]* 2>/dev/null` \
/usr/local/tcl \
/usr/local/lib \
/usr/lib64 \
${x_libraries}
/usr/local \
`ls -dr /usr/lib/tcl[[7-9]].[[0-9]]* 2>/dev/null` \
`ls -dr /usr/lib/tk[[7-9]].[[0-9]]* 2>/dev/null` \
/sw/lib \
${x_libraries} \
/usr
do
if test -r "$dir/tkConfig.sh" ; then
tk_config_sh="$dir/tkConfig.sh"
@ -477,6 +490,25 @@ if test $usingTcl ; then
. $tcl_config_sh
. $tk_config_sh
# Should probably trust the config file contents, but this configure
# file checks the Tcl and Tk include and lib directories. Since
# the config file doesn't separate out the libraries from the strings
# passed to the compiler/linker, do it manually here.
#
# Extract TCL_LIB_DIR from TCL_LIB_SPEC
# Extract TK_LIB_DIR from TK_LIB_SPEC
# Extract TCL_INC_DIR from TCL_INCLUDE_SPEC
# Extract TK_INC_DIR from TK_INCLUDE_SPEC
#
# These will be the defaults unless overridden by configure command line
tmpstr=${TCL_LIB_SPEC#*-L}
TCL_LIB_DIR=${tmpstr% -l*}
tmpstr=${TK_LIB_SPEC#*-L}
TK_LIB_DIR=${tmpstr% -l*}
TCL_INC_DIR=${TCL_INCLUDE_SPEC#*-I}
TK_INC_DIR=${TK_INCLUDE_SPEC#*-I}
if test "$TCL_VERSION" = "7.6" -a "$TK_VERSION" = "4.2" ; then
:
elif test "$TCL_VERSION" = "7.5" -a "$TK_VERSION" = "4.1" ; then
@ -620,7 +652,7 @@ if test $usingTcl ; then
fi
done
if test "x${TCLSH_EXE}" != "x" ; then
break;
break
fi
done
if test "x${TCLSH_EXE}" = "x" ; then
@ -670,8 +702,8 @@ if test $usingTcl ; then
else
for libname in \
"${loclib:=${TCL_EXEC_PREFIX}/lib}/lib${TCL_LIB_NAME}${SHDLIB_EXT}" \
"${loclib:=${TCL_EXEC_PREFIX}/lib64}/lib${TCL_LIB_NAME}${SHDLIB_EXT}" \
"${loclib:=${TCL_EXEC_PREFIX}/lib}/lib${TCL_LIB_NAME}${SHDLIB_EXT_ALT}"
"${loclib:=${TCL_EXEC_PREFIX}/lib}/lib${TCL_LIB_NAME}${SHDLIB_EXT_ALT}" \
"${loclib:=${TCL_EXEC_PREFIX}/lib64}/lib${TCL_LIB_NAME}${SHDLIB_EXT}"
do
if test -r "$libname" ; then
TCL_LIB_DIR="${TCL_EXEC_PREFIX}/lib"
@ -784,6 +816,7 @@ if test $usingTcl ; then
AC_DEFINE(TCL_NETGEN)
extra_libs="$extra_libs \${NETGENDIR}/tcltk/libtcltk.o"
extra_defs="$extra_defs -DTCL_DIR=\\\"\${TCLDIR}\\\""
stub_defs="$stub_defs -DUSE_TCL_STUBS -DUSE_TK_STUBS"
else
programs="$programs netgen"
unused="$unused tcltk"
@ -850,10 +883,9 @@ case $target in
*cygwin*)
AC_DEFINE(CYGWIN)
AC_DEFINE(i386)
AC_DEFINE(WIN32)
;;
*darwin*)
AC_DEFINE(macosx)
$as_echo "#define macosx macos" >> confdefs.h
if test "$CPP" = "cc -E" ; then
CPPFLAGS="$CPPFLAGS -no-cpp-precomp"
fi
@ -864,6 +896,7 @@ esac
# -----------------------------------------------------------------------
if test $usingTcl ; then
LIB_SPECS_NOSTUB="${LIB_SPECS}"
# -----------------------------------------------------------------------
#
@ -875,9 +908,11 @@ if test $usingTcl ; then
fi
if test "${TK_LIB_DIR}" = "/usr/lib" -o \
"${TK_LIB_DIR}" = "/usr/lib64" ; then
LIB_SPECS="${LIB_SPECS} ${TK_LIB_SPEC}"
LIB_SPECS_NOSTUB="${LIB_SPECS_NOSTUB} ${TK_LIB_SPEC}"
LIB_SPECS="${LIB_SPECS} ${TK_STUB_LIB_SPEC}"
else
LIB_SPECS="${LIB_SPECS} -L${TK_LIB_DIR} ${TK_LIB_SPEC}"
LIB_SPECS_NOSTUB="${LIB_SPECS_NOSTUB} -L${TK_LIB_DIR} ${TK_LIB_SPEC}"
LIB_SPECS="${LIB_SPECS} -L${TK_LIB_DIR} ${TK_STUB_LIB_SPEC}"
if test "x${loader_run_path}" = "x" ; then
loader_run_path="${TK_LIB_DIR}"
else
@ -899,11 +934,13 @@ if test $usingTcl ; then
fi
if test "${TCL_LIB_DIR}" = "/usr/lib" -o \
"${TCL_LIB_DIR}" = "/usr/lib64" -o \
"${TCL_LIB_DIR}" = "/usr/lib64" -o \
"${TCL_LIB_DIR}" = "${TK_LIB_DIR}" ; then
LIB_SPECS="${LIB_SPECS} ${TCL_LIB_SPEC}"
LIB_SPECS_NOSTUB="${LIB_SPECS_NOSTUB} ${TCL_LIB_SPEC}"
LIB_SPECS="${LIB_SPECS} ${TCL_STUB_LIB_SPEC}"
else
LIB_SPECS="${LIB_SPECS} -L${TCL_LIB_DIR} ${TCL_LIB_SPEC}"
LIB_SPECS_NOSTUB="${LIB_SPECS_NOSTUB} -L${TCL_LIB_DIR} ${TCL_LIB_SPEC}"
LIB_SPECS="${LIB_SPECS} -L${TCL_LIB_DIR} ${TCL_STUB_LIB_SPEC}"
if test "x${loader_run_path}" = "x" ; then
loader_run_path="${TCL_LIB_DIR}"
else
@ -1097,7 +1134,7 @@ if test $usingTcl ; then
# Not available on all versions: check for include file.
SHLIB_CFLAGS="-fpic"
LDDL_FLAGS="-shared ${LIB_SPECS}"
CFLAGS="${CFLAGS} -l/usr/X11R6/include"
CFLAGS="${CFLAGS} -L/usr/X11R6/include"
;;
*-netbsd*|*-openbsd*)
@ -1222,6 +1259,7 @@ if test $usingTcl ; then
AC_SUBST(LDFLAGS)
AC_SUBST(INC_SPECS)
AC_SUBST(LIB_SPECS)
AC_SUBST(LIB_SPECS_NOSTUB)
AC_SUBST(WISH_EXE)
AC_SUBST(TCLSH_EXE)
AC_SUBST(TCL_LIB_DIR)
@ -1239,6 +1277,7 @@ AC_SUBST(PACKAGE)
AC_SUBST(SCRIPTS)
AC_SUBST(extra_libs)
AC_SUBST(extra_defs)
AC_SUBST(stub_defs)
AC_SUBST(ld_extra_libs)
AC_SUBST(ld_extra_objs)
AC_SUBST(top_extra_libs)
@ -1247,11 +1286,13 @@ AC_SUBST(modules)
AC_SUBST(unused)
AC_SUBST(programs)
AC_SUBST(cadinstall)
AC_SUBST(DIST_DIR)
AC_SUBST(gr_cflags)
AC_SUBST(gr_dflags)
AC_SUBST(gr_libs)
AC_SUBST(gr_srcs)
AC_SUBST(HAVE_PYTHON3)
AC_SUBST(X_LIBS)
AC_SUBST(X_CFLAGS)
@ -1292,6 +1333,20 @@ else
echo
fi
${ECHO_N} "Python3: "
if test "${HAVE_PYTHON3}" == "yes"; then
echo "yes"
else
echo "no"
echo
echo " Without Python3, you cannot run the GUI interface to netgen."
echo " This is purely optional, as it contains no features not"
echo " available in the command-line (Tcl/Tk) version. If you want"
echo " python3 support, make sure that you have installed python3"
echo " on your system."
echo
fi
echo "-----------------------------------------------------------"
echo

View File

@ -1,85 +0,0 @@
# defs.mak.in --
# source file for autoconf-generated "defs.mak" for netgen
# defs.mak. Generated from defs.mak.in by configure.
# Feel free to change the values in here to suit your needs.
# Be aware that running scripts/configure again will overwrite
# any changes!
SHELL = /bin/sh
prefix = ${BUILDROOT}/usr/local
exec_prefix = ${prefix}
bindir = ${exec_prefix}/bin
libdir = ${exec_prefix}/lib
mandir = ${prefix}/share/man
VERSION =
SCRIPTS = ${NETGENDIR}/scripts
INSTALL = /bin/install -c
INSTALL_PROGRAM = ${INSTALL}
INSTALL_DATA = ${INSTALL} -m 644
INSTALL_SCRIPT = ${INSTALL}
# Override standard "make" target when compiling under TCL
ALL_TARGET = tcl
INSTALL_TARGET = install-tcl
# Change CADDIR to install in a different place
BINDIR = ${bindir}
MANDIR = ${mandir}
LIBDIR = ${libdir}
DOCDIR = ${libdir}/netgen/doc
TCLDIR = ${libdir}/netgen/tcl
PYDIR = ${libdir}/netgen/python
MAIN_EXTRA_LIBS = ${NETGENDIR}/tcltk/libtcltk.o
LD_EXTRA_LIBS =
LD_SHARED =
TOP_EXTRA_LIBS =
SUB_EXTRA_LIBS =
MODULES += tcltk
UNUSED_MODULES +=
PROGRAMS += tcltk
INSTALL_CAD_DIRS += tcltk
RM = rm -f
CP = cp
AR = @AR@
ARFLAGS = crv
LINK = /bin/ld -r
LD = /bin/ld
M4 = /bin/m4
RANLIB = ranlib
SHDLIB_EXT = .so
LDDL_FLAGS = -shared -Wl,-soname,$@ -Wl,--version-script=${NETGENDIR}/netgen/symbol.map
LD_RUN_PATH =
LIB_SPECS = -L/usr/lib64 -ltkstub8.6 -L/usr/lib64 -ltclstub8.6
LIB_SPECS_NOSTUB = -L/usr/lib64 -ltk8.6 -L/usr/lib64 -ltcl8.6
WISH_EXE = /usr/bin/wish
TCL_LIB_DIR = /usr/lib
CC = gcc
CPP = gcc -E -x c
CXX = @CXX@
CPPFLAGS = -I. -I${NETGENDIR}
DFLAGS = -DCAD_DIR=\"${LIBDIR}\" -DTCL_DIR=\"${TCLDIR}\" -DUSE_TCL_STUBS -DUSE_TK_STUBS -DPACKAGE_NAME=\"netgen\" -DPACKAGE_TARNAME=\"netgen\" -DPACKAGE_VERSION=\"1.3\" -DPACKAGE_STRING=\"netgen\ 1.3\" -DPACKAGE_BUGREPORT=\"eda-dev@opencircuitdesign.com\" -DPACKAGE_URL=\"\" -DNETGEN_VERSION=\"1.5\" -DNETGEN_REVISION=\"112\" -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DSIZEOF_VOID_P=8 -DSIZEOF_UNSIGNED_INT=4 -DSIZEOF_UNSIGNED_LONG=8 -DSIZEOF_UNSIGNED_LONG_LONG=8 -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DHAVE_DIRENT_H=1 -DHAVE_LIMITS_H=1 -DHAVE_VA_COPY=1 -DHAVE___VA_COPY=1 -DDBUG_OFF=1 -DTCL_NETGEN=1 -Dlinux=1 -DSYSV=1 -DISC=1 -DSHDLIB_EXT=\".so\" -DNDEBUG
DFLAGS_NOSTUB = -DCAD_DIR=\"${LIBDIR}\" -DTCL_DIR=\"${TCLDIR}\" -DPACKAGE_NAME=\"netgen\" -DPACKAGE_TARNAME=\"netgen\" -DPACKAGE_VERSION=\"1.3\" -DPACKAGE_STRING=\"netgen\ 1.3\" -DPACKAGE_BUGREPORT=\"eda-dev@opencircuitdesign.com\" -DPACKAGE_URL=\"\" -DNETGEN_VERSION=\"1.5\" -DNETGEN_REVISION=\"112\" -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DSIZEOF_VOID_P=8 -DSIZEOF_UNSIGNED_INT=4 -DSIZEOF_UNSIGNED_LONG=8 -DSIZEOF_UNSIGNED_LONG_LONG=8 -DSTDC_HEADERS=1 -DHAVE_SETENV=1 -DHAVE_PUTENV=1 -DHAVE_DIRENT_H=1 -DHAVE_LIMITS_H=1 -DHAVE_VA_COPY=1 -DHAVE___VA_COPY=1 -DDBUG_OFF=1 -DTCL_NETGEN=1 -Dlinux=1 -DSYSV=1 -DISC=1 -DSHDLIB_EXT=\".so\" -DNDEBUG
CFLAGS = -g -m64 -fPIC -fPIC
DEPEND_FILE = Depend
DEPEND_FLAG = -MM
EXEEXT =
GR_CFLAGS =
GR_DFLAGS = -DX11 -DXLIB -DNDEBUG
GR_LIBS = -lX11
GR_SRCS = ${TK_SRCS}
OBJS = ${SRCS:.c=.o}
LIB_OBJS = ${LIB_SRCS:.c=.o}
CLEANS = ${OBJS} ${LIB_OBJS} lib${MODULE}.a lib${MODULE}.o ${MODULE}

View File

@ -35,6 +35,13 @@ DOCDIR = ${libdir}/netgen/doc
TCLDIR = ${libdir}/netgen/tcl
PYDIR = ${libdir}/netgen/python
INSTALL_BINDIR = @DIST_DIR@/bin
INSTALL_MANDIR = @DIST_DIR@/share/man
INSTALL_LIBDIR = @DIST_DIR@/lib
INSTALL_DOCDIR = ${INSTALL_LIBDIR}/netgen/doc
INSTALL_TCLDIR = ${INSTALL_LIBDIR}/netgen/tcl
INSTALL_PYDIR = ${INSTALL_LIBDIR}/netgen/python
MAIN_EXTRA_LIBS = @extra_libs@
LD_EXTRA_LIBS = @ld_extra_libs@
LD_SHARED = @ld_extra_objs@
@ -61,6 +68,7 @@ LIB_SPECS = @LIB_SPECS@
LIB_SPECS_NOSTUB = @LIB_SPECS_NOSTUB@
WISH_EXE = @WISH_EXE@
TCL_LIB_DIR = @TCL_LIB_DIR@
EXTRA_CFLAGS =
CC = @CC@
CPP = @CPP@
@ -69,7 +77,7 @@ CXX = @CXX@
CPPFLAGS = -I. -I${NETGENDIR} @CPPFLAGS@
DFLAGS = @extra_defs@ @stub_defs@ @DEFS@ -DSHDLIB_EXT=\"@SHDLIB_EXT@\" -DNDEBUG
DFLAGS_NOSTUB = @extra_defs@ @DEFS@ -DSHDLIB_EXT=\"@SHDLIB_EXT@\" -DNDEBUG
CFLAGS = @CFLAGS@ @SHLIB_CFLAGS@ @INC_SPECS@
CFLAGS = @CFLAGS@ @SHLIB_CFLAGS@ @INC_SPECS@ ${EXTRA_CFLAGS}
DEPEND_FILE = Depend
DEPEND_FLAG = @DEPEND_FLAG@

View File

@ -1,187 +0,0 @@
#!/bin/csh -f
#
# makes the "database.h" (1st argument, $1) file from "database.h.in"
# (2nd argument, $2), setting various mask operation definitions
# according to the number of words implied by the value of TT_MAXTYPES
# The following mess grabs the value of TT_MAXTYPES from database.h.in
#
set maxtypes=`sed -n -e '/^#define[[:space:]]*TT_MAXTYPES/s/#define[[:space:]]*TT_MAXTYPES[[:space:]]*//p' < $1 | sed -e 's/\/\*[[:print:]]*\*\/[[:space:]]*//g' `
#
# Alternative method works with outdated versions of sed/ed.
#
if ($maxtypes == "") then
set maxtypes=`sed -n -e '/^#define[ ]*TT_MAXTYPES/s/#define[ ]*TT_MAXTYPES[ ]*//p' < $1 | sed -e 's/\/\*.*\*\/[ ]*//g' `
endif
#
# If we can't generate database.h correctly, nothing is going to compile.
#
if ($maxtypes == "") then
echo "Bad sed script in scripts/makedbh: Cannot generate database/database.h!"
exit
endif
# Find derived values from bits per word
# Note that bits-per-word should be determined from the compiler, but
# 32 bits per word has always been hardwired into magic.
#
set bpw = 32
# @ wordmask=$bpw - 1
# set wordshift=`echo "c=l($bpw); d=l(2); scale=0; c/d" | bc -l`
# @ maskwords=$maxtypes + $bpw - 1
# @ maskwords/=$bpw
@ maskwords=$maxtypes + $bpw - 1
@ maskwords/=$bpw
# Generate the main part of the database.h file from database.h.in
cat $1 > $2
# Generate a list of integers from 0 to the value of "maskwords" - 1
set count=""
@ maskwords--
while (${maskwords} >= 0)
set count=`echo ${count} ${maskwords}`
@ maskwords--
end
# Definitions
echo "#define TTMaskZero(m) ( \" >> $2
foreach i (${count})
echo -n " (m)->tt_words[$i] = 0" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo ", \" >> $2
endif
end
echo "#define TTMaskIsZero(m) ( \" >> $2
foreach i (${count})
echo -n " (m)->tt_words[$i] == 0" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo " && \" >> $2
endif
end
echo "#define TTMaskEqual(m, n) ( \" >> $2
foreach i (${count})
echo -n " (m)->tt_words[$i] == (n)->tt_words[$i]" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo " && \" >> $2
endif
end
echo "#define TTMaskIntersect(m, n) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] & (n)->tt_words[$i])" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo " || \" >> $2
endif
end
echo "#define TTMaskCom(m) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] = ~(m)->tt_words[$i])" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo ", \" >> $2
endif
end
echo "#define TTMaskCom2(m, n) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] = ~(n)->tt_words[$i])" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo ", \" >> $2
endif
end
echo "#define TTMaskSetMask(m, n) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] |= (n)->tt_words[$i])" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo ", \" >> $2
endif
end
echo "#define TTMaskSetMask3(m, n, o) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] |= (n)->tt_words[$i] | (o)->tt_words[$i])" \
>> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo ", \" >> $2
endif
end
echo "#define TTMaskAndMask(m, n) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] &= (n)->tt_words[$i])" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo ", \" >> $2
endif
end
echo "#define TTMaskAndMask3(m, n, o) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] = (n)->tt_words[$i] & (o)->tt_words[$i])" \
>> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo ", \" >> $2
endif
end
echo "#define TTMaskClearMask(m, n) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] &= ~(n)->tt_words[$i])" >> $2
if ($i == 0) then
echo ")" >> $2
echo "" >> $2
else
echo ", \" >> $2
endif
end
echo "#define TTMaskClearMask3(m, n, o) ( \" >> $2
foreach i (${count})
echo -n " ((m)->tt_words[$i] = (n)->tt_words[$i] & ~(o)->tt_words[$i])" \
>> $2
if ($i == 0) then
echo ")" >> $2
else
echo ", \" >> $2
endif
end
echo "" >> $2
echo "#endif /* _DATABASE_H */" >> $2

View File

@ -12,20 +12,20 @@ CLEANS += netgen.sh netgen.tcl netgenexec${EXEEXT}
CFLAGS += -I${NETGENDIR}/base
TCL_FILES = \
$(DESTDIR)${TCLDIR}/tkcon.tcl \
$(DESTDIR)${TCLDIR}/console.tcl \
$(DESTDIR)${TCLDIR}/netgen.tcl
$(DESTDIR)${INSTALL_TCLDIR}/tkcon.tcl \
$(DESTDIR)${INSTALL_TCLDIR}/console.tcl \
$(DESTDIR)${INSTALL_TCLDIR}/netgen.tcl
tcl-main: netgenexec${EXEEXT} netgen.tcl netgen.sh
install-tcl: netgenexec${EXEEXT} $(DESTDIR)${BINDIR}/netgen.sh ${TCL_FILES}
${RM} $(DESTDIR)${TCLDIR}/netgenexec${EXEEXT}
${CP} netgenexec${EXEEXT} $(DESTDIR)${TCLDIR}/netgenexec${EXEEXT}
install-tcl: netgenexec${EXEEXT} $(DESTDIR)${INSTALL_BINDIR}/netgen.sh ${TCL_FILES}
${RM} $(DESTDIR)${INSTALL_TCLDIR}/netgenexec${EXEEXT}
${CP} netgenexec${EXEEXT} $(DESTDIR)${INSTALL_TCLDIR}/netgenexec${EXEEXT}
netgenexec${EXEEXT}: netgenexec.c
${CC} ${CFLAGS} ${CPPFLAGS} ${DFLAGS_NOSTUB} netgenexec.c \
-o netgenexec${EXEEXT} \
${LDFLAGS} ${LIBS} ${LIB_SPECS_NOSTUB}
${LIB_SPECS_NOSTUB} ${LDFLAGS} ${LIBS} ${GR_LIBS}
netgen.tcl: netgen.tcl.in
sed -e 's%TCL_DIR%${TCLDIR}%g' \
@ -39,13 +39,13 @@ netgen.sh: netgen.sh.in
-e 's%WISH_EXE%${WISH_EXE}%g' \
netgen.sh.in > netgen.sh
$(DESTDIR)${TCLDIR}/%: %
${RM} $(DESTDIR)${TCLDIR}/$*
${CP} $* $(DESTDIR)${TCLDIR}/$*
$(DESTDIR)${INSTALL_TCLDIR}/%: %
${RM} $(DESTDIR)${INSTALL_TCLDIR}/$*
${CP} $* $(DESTDIR)${INSTALL_TCLDIR}/$*
$(DESTDIR)${BINDIR}/netgen.sh: netgen.sh
${RM} $(DESTDIR)${BINDIR}/netgen.sh $(DESTDIR)${BINDIR}/netgen
${CP} netgen.sh $(DESTDIR)${BINDIR}/netgen
(cd $(DESTDIR)${BINDIR}; chmod 0755 netgen)
$(DESTDIR)${INSTALL_BINDIR}/netgen.sh: netgen.sh
${RM} $(DESTDIR)${INSTALL_BINDIR}/netgen.sh $(DESTDIR)${INSTALL_BINDIR}/netgen
${CP} netgen.sh $(DESTDIR)${INSTALL_BINDIR}/netgen
(cd $(DESTDIR)${INSTALL_BINDIR}; chmod 0755 netgen)
include ${NETGENDIR}/rules.mak

View File

@ -62,16 +62,18 @@ proc netgen::convert_to_json {filename lvs_final} {
puts $fjson " \["
set cktval [lindex $value 0]
foreach pin [lrange $cktval 0 end-1] {
puts $fjson " \"$pin\","
set pinstr [string map {"\\" "\\\\"} $pin]
puts $fjson " \"$pinstr\","
}
set pin [lindex $cktval end]
set pin [string map {"\\" "\\\\"} [lindex $cktval end]]
puts $fjson " \"$pin\""
puts $fjson " \], \["
set cktval [lindex $value 1]
foreach pin [lrange $cktval 0 end-1] {
puts $fjson " \"$pin\","
set pinstr [string map {"\\" "\\\\"} $pin]
puts $fjson " \"$pinstr\","
}
set pin [lindex $cktval end]
set pin [string map {"\\" "\\\\"} [lindex $cktval end]]
puts $fjson " \"$pin\""
puts $fjson " \]"
if {$kidx == $nkeys} {
@ -138,7 +140,7 @@ proc netgen::convert_to_json {filename lvs_final} {
foreach net $cktval {
incr nidx
puts $fjson " \["
set netname [string map {"\\" ""} [lindex $net 0]]
set netname [string map {"\\" "\\\\"} [lindex $net 0]]
puts $fjson " \"$netname\","
puts $fjson " \["
set netconn [lindex $net 1]
@ -169,7 +171,7 @@ proc netgen::convert_to_json {filename lvs_final} {
foreach net $cktval {
incr nidx
puts $fjson " \["
set netname [string map {"\\" ""} [lindex $net 0]]
set netname [string map {"\\" "\\\\"} [lindex $net 0]]
puts $fjson " \"$netname\","
puts $fjson " \["
set netconn [lindex $net 1]
@ -221,7 +223,7 @@ proc netgen::convert_to_json {filename lvs_final} {
foreach inst $cktval {
incr iidx
puts $fjson " \["
set instname [lindex $inst 0]
set instname [string map {"\\" "\\\\"} [lindex $inst 0]]
puts $fjson " \"$instname\","
puts $fjson " \["
set instpins [lindex $inst 1]
@ -250,7 +252,7 @@ proc netgen::convert_to_json {filename lvs_final} {
foreach inst $cktval {
incr iidx
puts $fjson " \["
set instname [lindex $inst 0]
set instname [string map {"\\" "\\\\"} [lindex $inst 0]]
puts $fjson " \"$instname\","
puts $fjson " \["
set instpins [lindex $inst 1]
@ -292,8 +294,8 @@ proc netgen::convert_to_json {filename lvs_final} {
foreach instance $value {
incr pidx
puts $fjson " \["
set instnames [lindex $instance 0]
set instname0 [lindex $instnames 0]
set instnames [string map {"\\" "\\\\"} [lindex $instance 0]]
set instname0 [string map {"\\" "\\\\"} [lindex $instnames 0]]
puts $fjson " \["
puts $fjson " \"${instname0}\","
puts $fjson " \["
@ -310,7 +312,7 @@ proc netgen::convert_to_json {filename lvs_final} {
puts $fjson " \[\"${propname}\", \"${propval}\"\]"
puts $fjson " \]"
puts $fjson " \],"
set instname1 [lindex $instnames 1]
set instname1 [string map {"\\" "\\\\"} [lindex $instnames 1]]
puts $fjson " \["
puts $fjson " \"${instname1}\","
puts $fjson " \["
@ -352,7 +354,7 @@ proc netgen::convert_to_json {filename lvs_final} {
close $fjson
}
#----------------------------------------------------------------
#-----------------------------------------------------------------------
# Define the "lvs" command as a way of calling the netgen options
# for standard compare, essentially the same as the old "netcomp"
# standalone program.
@ -361,14 +363,20 @@ proc netgen::convert_to_json {filename lvs_final} {
# although if the cells have not been read in yet, then the
# original syntax of filename or {filename cellname} is required.
#
# "args" is passed to verify and may therefore contain only the
# value "-list" or nothing. If "-list", then output is returned
# as a nested list.
#----------------------------------------------------------------
# "args" may be "-list", "-json", or "-blackbox".
# "-list" returns output as a nested list.
# "-json" creates a .json-format output file in addition to stdout.
# "-blackbox" treats empty cells as black-box entries.
# "-noflatten={list}" is a list of cells not to flatten if mismatched.
# i.e., the cells are expected to match and any mismatch cannot be
# expected to be resolved by flattening the contents of the mismatched
# cells.
#-----------------------------------------------------------------------
proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
set dolist 0
set dojson 0
set noflat {}
foreach arg $args {
if {$arg == "-list"} {
puts stdout "Generating list result"
@ -382,6 +390,30 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
} elseif {$arg == "-blackbox"} {
puts stdout "Treating empty subcircuits as black-box cells"
netgen::model blackbox on
} elseif {[string first "-noflatten=" $arg] == 0} {
set value [string range $arg 11 end]
# If argument is a filename then read the list of cells from it;
# otherwise, argument is the list of files itself in quotes or
# braces.
if {[file exists $value]} {
if {![catch {open $value r} fnf]} {
while {[gets $fnf line] >= 0} {
if {[lindex $line 0] != "#"} {
foreach cell $line {
lappend noflat $cell
}
}
}
close $fnf
} else {
puts stderr "Cannot open file $value for reading cell list."
}
} else {
set noflat [string trim $value \"\{\}]
}
if {[llength $noflat] > 0} {
puts stdout "Will not flatten these subcells: $noflat"
}
}
}
@ -397,7 +429,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
set file1 $name1
set cell1 $name1
}
puts stdout "Reading netlist file $file1"
puts stdout "Reading netlist file $file1 for $name1"
set fnum1 [netgen::readnet $file1]
} else {
set cell1 [lindex $flist1 0]
@ -414,7 +446,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
set file2 $name2
set cell2 $name2
}
puts stdout "Reading netlist file $file2"
puts stdout "Reading netlist file $file2 for $name2"
set fnum2 [netgen::readnet $file2]
} else {
set cell2 [lindex $flist2 0]
@ -429,7 +461,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
}
set clist1 [cells list $fnum1]
set cidx [lsearch -regexp $clist1 ^$cell1$]
set cidx [lsearch -exact $clist1 $cell1]
if {$cidx < 0} {
puts stderr "Cannot find cell $cell1 in file $file1"
return
@ -437,7 +469,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
set cell1 [lindex $clist1 $cidx]
}
set clist2 [cells list $fnum2]
set cidx [lsearch -regexp $clist2 ^$cell2$]
set cidx [lsearch -exact $clist2 $cell2]
if {$cidx < 0} {
puts stderr "Cannot find cell $cell2 in file $file2"
return
@ -445,10 +477,26 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
set cell2 [lindex $clist2 $cidx]
}
# The "noflat" list is non-file-specific, so run on each file.
foreach cell $noflat {
set cidx [lsearch -regexp $clist1 ^$cell$]
if {$cidx >= 0} {
netgen::flatten prohibit "$fnum1 $cell"
}
set cidx [lsearch -regexp $clist2 ^$cell$]
if {$cidx >= 0} {
netgen::flatten prohibit "$fnum2 $cell"
}
}
netgen::compare assign "$fnum1 $cell1" "$fnum2 $cell2"
if {[file exists $setupfile]} {
puts stdout "Reading setup file $setupfile"
if {$setupfile == ""} {
puts stdout "\nNo setup file specified. Using trivial default setup.\n"
netgen::permute default ;# transistors and resistors
netgen::property default
} elseif {[file exists $setupfile]} {
puts stdout "\nReading setup file $setupfile\n"
# Instead of sourcing the setup file, run each line so we can
# catch individual errors and not let them halt the LVS process
set perrors 0
@ -468,6 +516,14 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
}
}
close $fsetup
if {$command != {}} {
# Incomplete command. Evaluate it to get a meaningful error message
if {[catch {uplevel 1 [list namespace eval netgen $command]} msg]} {
set msg [string trimright $msg "\n"]
puts stderr "Error $setupfile:$sline (ignoring), $msg"
incr perrors
}
}
} else {
puts stdout "Error: Cannot read the setup file $setupfile"
}
@ -476,8 +532,10 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
puts stdout "Warning: There were errors reading the setup file"
}
} elseif {[string first nosetup $setupfile] < 0} {
netgen::permute default ;# transistors and resistors
netgen::property default
puts stderr "\nError: Setup file $setupfile does not exist.\n"
return
} else {
puts stderr "\nNo setup file specified. Continuing without a setup.\n"
}
if {[string first nolog $logfile] < 0} {
@ -501,13 +559,25 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
return
}
set properr {}
set matcherr {}
set childMismatch 0 ;# 1 indicates black-box child subcircuit mismatch
while {$endval != {}} {
if {$dolist == 1} {
netgen::run -list converge
} else {
netgen::run converge
}
netgen::log echo on
set pinMismatch 0 ;# indicates pin mismatch in top cell
set doCheckFlatten 0
set doFlatten 0
if {[netgen::print queue] == {}} {
set doEquatePins 1 ;# run equate pins on top cell
} else {
set doEquatePins 0 ;# don't run equate pins unless unique match
}
set forceMatch 0 ;# for pin matching
netgen::log echo off
if {[verify equivalent]} {
# Resolve automorphisms by pin and property
if {$dolist == 1} {
@ -516,48 +586,113 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
netgen::run resolve
}
set uresult [verify unique]
# uresult: -3 : unique with property error
# -2 : equivalent with port errors
# -1 : black box
# 0 : equivalent but not unique
# 1 : unique
if {$uresult == 0} {
netgen::log echo on
netgen::log put " Networks match locally but not globally.\n"
netgen::log put " Probably connections are swapped.\n"
netgen::log put " Check the end of logfile ${logfile} for implicated nodes.\n"
netgen::log echo off
if {$dolist == 1} {
verify -list nodes
} else {
verify nodes
}
# Flatten the non-matching subcircuit (but not the top-level cells)
if {[netgen::print queue] != {}} {
netgen::log put " Flattening non-matched subcircuits $endval"
netgen::flatten class "[lindex $endval 0] $fnum1"
netgen::flatten class "[lindex $endval 1] $fnum2"
}
set doCheckFlatten 1
} else {
# Match pins
netgen::log echo off
if {$dolist == 1} {
set result [equate -list pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
} else {
set result [equate pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
}
if {$result != 0} {
equate classes "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"
}
netgen::log echo on
# Equate pins for black boxes, unique matches (possibly with property
# errors), and unique with port errors
set doEquatePins 1
}
if {$uresult == -1} { ;# black box
set forceMatch 1
} elseif {$uresult == -3} { ;# property error
lappend properr [lindex $endval 0]
} elseif {$uresult == -2} { ;# unmatched pins
set doCheckFlatten 1
} elseif {$uresult == -4} { ;# unmatched pins and properties
lappend properr [lindex $endval 0]
set doCheckFlatten 1
}
if {$uresult == 2} {lappend properr [lindex $endval 0]}
} else {
# Flatten the non-matching subcircuit (but not the top-level cells)
if {[netgen::print queue] != {}} {
netgen::log put " Flattening non-matched subcircuits $endval"
netgen::flatten class "[lindex $endval 0] $fnum1"
netgen::flatten class "[lindex $endval 1] $fnum2"
# not equivalent
netgen::log echo on
# netgen::log put " DEBUG: not equivalent $endval\n"
netgen::log echo off
set doCheckFlatten 1
}
if {$doCheckFlatten} {
# Flatten the non-matching subcircuit (but not the top-level cell,
# or cells explicitly prohibited from flattening)
if {[netgen::print queue] != {}} {
if {([lsearch $noflat [lindex $endval 0]] == -1) &&
([lsearch $noflat [lindex $endval 1]] == -1)} {
set doFlatten 1
} else {
netgen::log echo on
netgen::log put " Continuing with black-boxed subcircuits $endval\n"
netgen::log echo off
lappend matcherr [lindex $endval 0]"($fnum1)"
lappend matcherr [lindex $endval 1]"($fnum2)"
netgen::flatten prohibit "[lindex $endval 0] $fnum1"
netgen::flatten prohibit "[lindex $endval 1] $fnum2"
set doEquatePins 1
set childMismatch 1
set forceMatch 1
}
}
}
netgen::log echo off
if {$doEquatePins} {
# Match pins
if {$dolist == 1} {
if {$forceMatch} {
set result [equate -list -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
} else {
set result [equate -list pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
}
} else {
if {$forceMatch} {
set result [equate -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
} else {
set result [equate pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
}
}
if {$result >= 0} {
equate classes "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"
}
# Do not set pinMismatch for black boxes
if {$result < 0} {
if {$result == -1 && [netgen::print queue] != {} && $forceMatch != 1} {
# flatten pin mismatch, but not empty cells (-2) or top cell or
# cells prohibited from flattening.
set doFlatten 1
}
} elseif {[netgen::print queue] == {} && $result == 0} {
set pinMismatch 1
} else {
# This assumes that proxy pins are added correctly. Previously,
# that was not trusted, and so an initial pin mismatch would
# always force subcells to be flattened.
set doFlatten 0
}
}
if {$doFlatten} {
netgen::log echo on
netgen::log put " Flattening non-matched subcircuits $endval\n"
netgen::log echo off
netgen::flatten class "[lindex $endval 0] $fnum1"
netgen::flatten class "[lindex $endval 1] $fnum2"
}
if {$dolist == 1} {
catch {lappend lvs_final $lvs_out}
set lvs_out {}
@ -566,12 +701,23 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
set endval [netgen::compare hierarchical]
}
}
netgen::log echo off
puts stdout "Result: " nonewline
netgen::log echo on
verify only
netgen::log put "\nFinal result: "
if {$pinMismatch || $childMismatch} {
if {$childMismatch} {
netgen::log put "Subcell(s) failed matching.\n"
}
if {$pinMismatch} {
netgen::log put "Top level cell failed pin matching.\n"
}
} else {
verify only
}
if {$properr != {}} {
netgen::log put "The following cells had property errors: $properr\n"
netgen::log put "\nThe following cells had property errors:\n " [regsub -all { } $properr "\n "] "\n"
}
if {$matcherr != {}} {
netgen::log put "\nThe following subcells failed to match:\n " [regsub -all { } $matcherr "\n "] "\n"
}
if {$dolog} {
netgen::log end
@ -623,6 +769,19 @@ set auto_noexec 1 ;# don't EVER call UNIX commands w/o "shell" in front
# Cross-Application section
#----------------------------------------------------------------------
# For use with open_pdks, set PDK_ROOT from the environment. If no
# such environment variable exists, check some common locations.
if {[catch {set PDK_ROOT $::env(PDK_ROOT)}]} {
if {[file isdir /usr/local/share/pdk] == 1} {
set PDK_ROOT /usr/local/share/pdk
} elseif {[file isdir /usr/share/pdk] == 1} {
set PDK_ROOT /usr/share/pdk
} elseif {[file isdir /foss/pdk] == 1} {
set PDK_ROOT /foss/pdk
}
}
# Setup IRSIM assuming that the Tcl version is installed.
# We do not need to rename procedure irsim to NULL because it is
# redefined in a script, which simply overwrites the original.

File diff suppressed because it is too large Load Diff

View File

@ -36,7 +36,7 @@ exec ${NETGEN_WISH:=wish} "$0" ${1+"$@"}
#
# set ::tkcon::PRIV(proxy) {wwwproxy:8080 1}
#
# Or you can set the above variable from within tkcon by calling
# Or you can set the above variable from within tkcon by calling
#
# tkcon master set ::tkcon:PRIV(proxy) wwwproxy:8080
#
@ -44,6 +44,8 @@ exec ${NETGEN_WISH:=wish} "$0" ${1+"$@"}
if {$tcl_version < 8.0} {
return -code error "tkcon requires at least Tcl/Tk8"
} else {
# Prevent breaking on version 8.5.2
# package require -exact Tk $tcl_version
package require Tk $tcl_version
}
@ -59,18 +61,6 @@ foreach pkg [info loaded {}] {
}
catch {unset pkg file name version}
# Tk 8.4 makes previously exposed stuff private.
# FIX: Update tkcon to not rely on the private Tk code.
#
if {![llength [info globals tkPriv]]} {
::tk::unsupported::ExposePrivateVariable tkPriv
}
foreach cmd {SetCursor UpDownLine Transpose ScrollPages} {
if {![llength [info commands tkText$cmd]]} {
::tk::unsupported::ExposePrivateCommand tkText$cmd
}
}
# Initialize the ::tkcon namespace
#
namespace eval ::tkcon {
@ -196,7 +186,7 @@ proc ::tkcon::Init {} {
tkcon_puts tkcon_gets observe observe_var unalias which what
}
version 2.3
RCS {RCS: @(#) $Id: tkcon.tcl,v 1.2 2008/05/23 00:20:17 tim Exp $}
RCS {RCS: @(#) $Id: tkcon.tcl,v 1.2 2008/04/18 16:28:13 tim Exp $}
HEADURL {http://cvs.sourceforge.net/cgi-bin/viewcvs.cgi/tkcon/tkcon/tkcon.tcl?rev=HEAD}
docs "http://tkcon.sourceforge.net/"
email {jeff@hobbs.org}
@ -654,7 +644,7 @@ proc ::tkcon::GarbageCollect {} {
## ::tkcon::EvalCmd) in turn. Any uncompleted command will not be eval'ed.
# ARGS: w - console text widget
# Calls: ::tkcon::CmdGet, ::tkcon::CmdSep, ::tkcon::EvalCmd
##
##
proc ::tkcon::Eval {w} {
set incomplete [CmdSep [CmdGet $w] cmds last]
$w mark set insert end-1c
@ -674,7 +664,7 @@ proc ::tkcon::Eval {w} {
# Calls: ::tkcon::Prompt
# Outputs: result of command to stdout (or stderr if error occured)
# Returns: next event number
##
##
proc ::tkcon::EvalCmd {w cmd} {
variable OPT
variable PRIV
@ -741,11 +731,11 @@ proc ::tkcon::EvalCmd {w cmd} {
set tag [UniqueTag $w]
$w insert output $res [list stderr $tag] \n stderr
$w tag bind $tag <Enter> \
[list $w tag configure $tag -under 1]
[list $w tag configure $tag -underline 1]
$w tag bind $tag <Leave> \
[list $w tag configure $tag -under 0]
[list $w tag configure $tag -underline 0]
$w tag bind $tag <ButtonRelease-1> \
"if {!\[info exists tkPriv(mouseMoved)\] || !\$tkPriv(mouseMoved)} \
"if {!\[info exists ::tk::Priv(mouseMoved)\] || !\$::tk::Priv(mouseMoved)} \
{[list edit -attach [Attach] -type error -- $PRIV(errorInfo)]}"
} else {
$w insert output $res\n stderr
@ -905,7 +895,7 @@ proc ::tkcon::EvalSocketClosed {} {
## ::tkcon::EvalNamespace - evaluates the args in a particular namespace
## This is an override for ::tkcon::EvalAttached for when the user wants
## to attach to a particular namespace of the attached interp
# ARGS: attached
# ARGS: attached
# namespace the namespace to evaluate in
# args the args to evaluate
# RETURNS: the result of the command
@ -933,7 +923,7 @@ proc ::tkcon::Namespaces {{ns ::} {l {}}} {
## ::tkcon::CmdGet - gets the current command from the console widget
# ARGS: w - console text widget
# Returns: text which compromises current command line
##
##
proc ::tkcon::CmdGet w {
if {![llength [$w tag nextrange prompt limit end]]} {
$w tag add stdin limit end-1c
@ -947,7 +937,7 @@ proc ::tkcon::CmdGet w {
# last - varname of any remainder (like an incomplete final command).
# If there is only one command, it's placed in this var.
# Returns: constituent command info in varnames specified by list & rmd.
##
##
proc ::tkcon::CmdSep {cmd list last} {
upvar 1 $list cmds $last inc
set inc {}
@ -974,7 +964,7 @@ proc ::tkcon::CmdSep {cmd list last} {
## ::tkcon::CmdSplit - splits multiple commands into a list
# ARGS: cmd - (possible) multiple command to separate
# Returns: constituent commands in a list
##
##
proc ::tkcon::CmdSplit {cmd} {
set inc {}
set cmds {}
@ -998,7 +988,7 @@ proc ::tkcon::CmdSplit {cmd} {
## Called by ::tkcon::EvalCmd
# ARGS: w - text widget
# Outputs: tag name guaranteed unique in the widget
##
##
proc ::tkcon::UniqueTag {w} {
set tags [$w tag names]
set idx 0
@ -1011,7 +1001,7 @@ proc ::tkcon::UniqueTag {w} {
# ARGS: w - console text widget
# size - # of lines to constrain to
# Outputs: may delete data in console widget
##
##
proc ::tkcon::ConstrainBuffer {w size} {
if {[$w index end] > $size} {
$w delete 1.0 [expr {int([$w index end])-$size}].0
@ -1021,7 +1011,7 @@ proc ::tkcon::ConstrainBuffer {w size} {
## ::tkcon::Prompt - displays the prompt in the console widget
# ARGS: w - console text widget
# Outputs: prompt (specified in ::tkcon::OPT(prompt1)) to console
##
##
proc ::tkcon::Prompt {{pre {}} {post {}} {prompt {}}} {
variable OPT
variable PRIV
@ -1053,7 +1043,7 @@ proc ::tkcon::Prompt {{pre {}} {post {}} {prompt {}}} {
}
## ::tkcon::About - gives about info for tkcon
##
##
proc ::tkcon::About {} {
variable OPT
variable PRIV
@ -1088,7 +1078,7 @@ proc ::tkcon::About {} {
## ::tkcon::InitMenus - inits the menubar and popup for the console
# ARGS: w - console text widget
##
##
proc ::tkcon::InitMenus {w title} {
variable OPT
variable PRIV
@ -1521,7 +1511,7 @@ proc ::tkcon::NamespaceMenu m {
}
}
## Namepaces List
## Namepaces List
##
proc ::tkcon::NamespacesList {names} {
variable PRIV
@ -1894,7 +1884,7 @@ proc ::tkcon::NewSocket {} {
## The file is actually sourced in the currently attached's interp
# ARGS: fn - (optional) filename to source in
# Returns: selected filename ({} if nothing was selected)
##
##
proc ::tkcon::Load { {fn ""} } {
set types {
{{Tcl Files} {.tcl .tk}}
@ -1913,7 +1903,7 @@ proc ::tkcon::Load { {fn ""} } {
## This does not eval in a slave because it's not necessary
# ARGS: w - console text widget
# fn - (optional) filename to save to
##
##
proc ::tkcon::Save { {fn ""} {type ""} {opt ""} {mode w} } {
variable PRIV
@ -1983,7 +1973,7 @@ proc ::tkcon::MainInit {} {
## Creates a slave interpreter and sources in this script.
## All other interpreters also get a command to eval function in the
## new interpreter.
##
##
proc ::tkcon::New {} {
variable PRIV
global argv0 argc argv
@ -2020,7 +2010,7 @@ proc ::tkcon::MainInit {} {
## ::tkcon::Exit - full exit OR destroy slave console
## This proc should only be called in the main interpreter from a slave.
## The master determines whether we do a full exit or just kill the slave.
##
##
proc ::tkcon::Exit {slave args} {
variable PRIV
variable OPT
@ -2043,7 +2033,7 @@ proc ::tkcon::MainInit {} {
## This proc should only be called by the main interpreter. If it is
## called from there, it will ask before exiting tkcon. All others
## (slaves) will just have their slave interpreter deleted, closing them.
##
##
proc ::tkcon::Destroy {{slave {}}} {
variable PRIV
@ -2472,9 +2462,9 @@ proc ::tkcon::ErrorHighlight w {
set tag [UniqueTag $w]
$w tag add $tag $start+${c0}c $start+1c+${c1}c
$w tag configure $tag -foreground $COLOR(stdout)
$w tag bind $tag <Enter> [list $w tag configure $tag -under 1]
$w tag bind $tag <Leave> [list $w tag configure $tag -under 0]
$w tag bind $tag <ButtonRelease-1> "if {!\$tkPriv(mouseMoved)} \
$w tag bind $tag <Enter> [list $w tag configure $tag -underline 1]
$w tag bind $tag <Leave> [list $w tag configure $tag -underline 0]
$w tag bind $tag <ButtonRelease-1> "if {!\$::tk::Priv(mouseMoved)} \
{[list edit -attach $app -type proc -find $what -- $cmd]}"
}
set info [string range $info $c1 end]
@ -2501,9 +2491,9 @@ proc ::tkcon::ErrorHighlight w {
set tag [UniqueTag $w]
$w tag add $tag $ix+1c $start
$w tag configure $tag -foreground $COLOR(proc)
$w tag bind $tag <Enter> [list $w tag configure $tag -under 1]
$w tag bind $tag <Leave> [list $w tag configure $tag -under 0]
$w tag bind $tag <ButtonRelease-1> "if {!\$tkPriv(mouseMoved)} \
$w tag bind $tag <Enter> [list $w tag configure $tag -underline 1]
$w tag bind $tag <Leave> [list $w tag configure $tag -underline 0]
$w tag bind $tag <ButtonRelease-1> "if {!\$::tk::Priv(mouseMoved)} \
{[list edit -attach $app -type proc -- $cmd]}"
}
}
@ -2513,7 +2503,7 @@ proc ::tkcon::ErrorHighlight w {
## This always exists in the main interpreter, and is aliased into
## other connected interpreters
# ARGS: totally variable, see internal comments
##
##
proc tkcon {cmd args} {
global errorInfo
@ -2552,8 +2542,8 @@ proc tkcon {cmd args} {
## 'congets' a replacement for [gets stdin]
# Use the 'gets' alias of 'tkcon_gets' command instead of
# calling the *get* methods directly for best compatability
if {[llength $args]} {
return -code error "wrong # args: must be \"tkcon congets\""
if {[llength $args] > 1} {
return -code error "wrong # args: must be \"tkcon congets [pfix]\""
}
tkcon show
set old [bind TkConsole <<TkCon_Eval>>]
@ -2561,7 +2551,12 @@ proc tkcon {cmd args} {
set w $::tkcon::PRIV(console)
# Make sure to move the limit to get the right data
$w mark set insert end
$w mark set limit insert
if {[llength $args]} {
$w mark set limit insert
$w insert end $args
} else {
$w mark set limit insert
}
$w see end
vwait ::tkcon::PRIV(wait)
set line [::tkcon::CmdGet $w]
@ -2790,21 +2785,27 @@ proc tkcon {cmd args} {
## This allows me to capture all stdout/stderr to the console window
## This will be renamed to 'puts' at the appropriate time during init
##
# ARGS: same as usual
# ARGS: same as usual
# Outputs: the string with a color-coded text tag
##
##
proc tkcon_puts args {
set len [llength $args]
foreach {arg1 arg2 arg3} $args { break }
if {$len == 1} {
tkcon console insert output "$arg1\n" stdout
set sarg $arg1
set nl 1
set farg stdout
} elseif {$len == 2} {
if {![string compare $arg1 -nonewline]} {
tkcon console insert output $arg2 stdout
set sarg $arg2
set farg stdout
set nl 0
} elseif {![string compare $arg1 stdout] \
|| ![string compare $arg1 stderr]} {
tkcon console insert output "$arg2\n" $arg1
set sarg $arg2
set farg $arg1
set nl 1
} else {
set len 0
}
@ -2812,11 +2813,15 @@ proc tkcon_puts args {
if {![string compare $arg1 -nonewline] \
&& (![string compare $arg2 stdout] \
|| ![string compare $arg2 stderr])} {
tkcon console insert output $arg3 $arg2
set sarg $arg3
set farg $arg2
set nl 0
} elseif {(![string compare $arg1 stdout] \
|| ![string compare $arg1 stderr]) \
&& ![string compare $arg3 nonewline]} {
tkcon console insert output $arg2 $arg1
set sarg $arg2
set farg $arg1
set nl 0
} else {
set len 0
}
@ -2826,7 +2831,42 @@ proc tkcon_puts args {
## $len == 0 means it wasn't handled by tkcon above.
##
if {$len == 0} {
if {$len != 0} {
## "poor man's" \r substitution---erase everything on the output
## line and print from character after the \r
set rpt [string last \r $sarg]
if {$rpt >= 0} {
tkcon console delete "insert linestart" "insert lineend"
set sarg [string range $sarg [expr {$rpt + 1}] end]
}
set bpt [string first \b $sarg]
if {$bpt >= 0} {
set narg [string range $sarg [expr {$bpt + 1}] end]
set sarg [string range $sarg 0 [expr {$bpt - 1}]]
set nl 0
}
if {$nl == 0} {
tkcon console insert output $sarg $farg
} else {
tkcon console insert output "$sarg\n" $farg
}
if {$bpt >= 0} {
tkcon console delete "insert -1 char" insert
if {$nl == 0} {
tkcon_puts $farg $narg nonewline
} else {
tkcon_puts $farg $narg
}
}
} else {
global errorCode errorInfo
if {[catch "tkcon_tcl_puts $args" msg]} {
regsub tkcon_tcl_puts $msg puts msg
@ -2849,7 +2889,7 @@ proc tkcon_puts args {
## This allows me to capture all stdin input without needing to stdin
## This will be renamed to 'gets' at the appropriate time during init
##
# ARGS: same as gets
# ARGS: same as gets
# Outputs: same as gets
##
proc tkcon_gets args {
@ -2873,12 +2913,12 @@ proc tkcon_gets args {
}
## edit - opens a file/proc/var for reading/editing
##
##
# Arguments:
# type proc/file/var
# what the actual name of the item
# Returns: nothing
##
##
proc edit {args} {
array set opts {-find {} -type {} -attach {}}
while {[string match -* [lindex $args 0]]} {
@ -2954,14 +2994,14 @@ proc edit {args} {
##
set text $w.text
set m [menu [::tkcon::MenuButton $menu Edit edit]]
$m add command -label "Cut" -under 2 \
$m add command -label "Cut" -underline 2 \
-command [list tk_textCut $text]
$m add command -label "Copy" -under 0 \
$m add command -label "Copy" -underline 0 \
-command [list tk_textCopy $text]
$m add command -label "Paste" -under 0 \
$m add command -label "Paste" -underline 0 \
-command [list tk_textPaste $text]
$m add separator
$m add command -label "Find" -under 0 \
$m add command -label "Find" -underline 0 \
-command [list ::tkcon::FindBox $text]
## Send To Menu
@ -3030,7 +3070,7 @@ proc echo args { puts [concat $args] }
## clear - clears the buffer of the console (not the history though)
## This is executed in the parent interpreter
##
##
proc clear {{pcnt 100}} {
if {![regexp {^[0-9]*$} $pcnt] || $pcnt < 1 || $pcnt > 100} {
return -code error \
@ -3048,7 +3088,7 @@ proc clear {{pcnt 100}} {
## If called with one arg, returns the alias of that arg (or {} if none)
# ARGS: newcmd - (optional) command to bind alias to
# args - command and args being aliased
##
##
proc alias {{newcmd {}} args} {
if {[string match {} $newcmd]} {
set res {}
@ -3065,7 +3105,7 @@ proc alias {{newcmd {}} args} {
## unalias - unaliases an alias'ed command
# ARGS: cmd - command to unbind as an alias
##
##
proc unalias {cmd} {
interp alias {} $cmd {}
}
@ -3085,7 +3125,7 @@ proc unalias {cmd} {
# -- forcibly ends options recognition
#
# Returns: the values of the requested items in a 'source'able form
##
##
proc dump {type args} {
set whine 1
set code ok
@ -3637,13 +3677,13 @@ proc observe_var {name el op} {
## which - tells you where a command is found
# ARGS: cmd - command name
# Returns: where command is found (internal / external / unknown)
##
##
proc which cmd {
## This tries to auto-load a command if not recognized
set types [uplevel 1 [list what $cmd 1]]
if {[llength $types]} {
set out {}
foreach type $types {
switch -- $type {
alias { set res "$cmd: aliased to [alias $cmd]" }
@ -3674,7 +3714,7 @@ proc which cmd {
## what - tells you what a string is recognized as
# ARGS: str - string to id
# Returns: id types of command as list
##
##
proc what {str {autoload 0}} {
set types {}
if {[llength [info commands $str]] || ($autoload && \
@ -3721,7 +3761,7 @@ proc what {str {autoload 0}} {
# -long - list in full format "permissions size date filename"
# -full - displays / after directories and link paths for links
# Returns: a directory listing
##
##
proc dir {args} {
array set s {
all 0 full 0 long 0
@ -4106,7 +4146,7 @@ proc ::tkcon::Bindings {} {
global tcl_platform tk_version
#-----------------------------------------------------------------------
# Elements of tkPriv that are used in this file:
# Elements of ::tk::Priv that are used in this file:
#
# char - Character position on the line; kept in order
# to allow moving up or down past short lines while
@ -4131,9 +4171,12 @@ proc ::tkcon::Bindings {} {
}
## Get all Text bindings into TkConsole
foreach ev [bind Text] { bind TkConsole $ev [bind Text $ev] }
foreach ev [bind Text] { bind TkConsole $ev [bind Text $ev] }
## We really didn't want the newline insertion
bind TkConsole <Control-Key-o> {}
## in 8.6b3, the virtual events <<NextLine>> and <<PrevLine>>
# mess up our history feature
bind TkConsole <<NextLine>> {}
bind TkConsole <<PrevLine>> {}
@ -4342,9 +4385,9 @@ proc ::tkcon::Bindings {} {
bind TkConsole <Control-a> {
if {[%W compare {limit linestart} == {insert linestart}]} {
tkTextSetCursor %W limit
::tk::TextSetCursor %W limit
} else {
tkTextSetCursor %W {insert linestart}
::tk::TextSetCursor %W {insert linestart}
}
}
bind TkConsole <Key-Home> [bind TkConsole <Control-a>]
@ -4368,14 +4411,14 @@ proc ::tkcon::Bindings {} {
}
bind TkConsole <<TkCon_Previous>> {
if {[%W compare {insert linestart} != {limit linestart}]} {
tkTextSetCursor %W [tkTextUpDownLine %W -1]
::tk::TextSetCursor %W [::tk::TextUpDownLine %W -1]
} else {
::tkcon::Event -1
}
}
bind TkConsole <<TkCon_Next>> {
if {[%W compare {insert linestart} != {end-1c linestart}]} {
tkTextSetCursor %W [tkTextUpDownLine %W 1]
::tk::TextSetCursor %W [::tk::TextUpDownLine %W 1]
} else {
::tkcon::Event 1
}
@ -4390,7 +4433,7 @@ proc ::tkcon::Bindings {} {
}
bind TkConsole <<TkCon_Transpose>> {
## Transpose current and previous chars
if {[%W compare insert > "limit+1c"]} { tkTextTranspose %W }
if {[%W compare insert > "limit+1c"]} { ::tk::TextTranspose %W }
}
bind TkConsole <<TkCon_ClearLine>> {
## Clear command line (Unix shell staple)
@ -4408,10 +4451,10 @@ proc ::tkcon::Bindings {} {
::tkcon::Insert %W $::tkcon::PRIV(tmp)
%W see end
}
catch {bind TkConsole <Key-Page_Up> { tkTextScrollPages %W -1 }}
catch {bind TkConsole <Key-Prior> { tkTextScrollPages %W -1 }}
catch {bind TkConsole <Key-Page_Down> { tkTextScrollPages %W 1 }}
catch {bind TkConsole <Key-Next> { tkTextScrollPages %W 1 }}
catch {bind TkConsole <Key-Page_Up> { ::tk::TextScrollPages %W -1 }}
catch {bind TkConsole <Key-Prior> { ::tk::TextScrollPages %W -1 }}
catch {bind TkConsole <Key-Page_Down> { ::tk::TextScrollPages %W 1 }}
catch {bind TkConsole <Key-Next> { ::tk::TextScrollPages %W 1 }}
bind TkConsole <$PRIV(meta)-d> {
if {[%W compare insert >= limit]} {
%W delete insert {insert wordend}
@ -4429,7 +4472,7 @@ proc ::tkcon::Bindings {} {
}
bind TkConsole <ButtonRelease-2> {
if {
(!$tkPriv(mouseMoved) || $tk_strictMotif) &&
(!$::tk::Priv(mouseMoved) || $tk_strictMotif) &&
![catch {::tkcon::GetSelection %W} ::tkcon::PRIV(tmp)]
} {
if {[%W compare @%x,%y < limit]} {
@ -4600,7 +4643,7 @@ proc ::tkcon::TagProc w {
# c1 - first char of pair
# c2 - second char of pair
# Calls: ::tkcon::Blink
##
##
proc ::tkcon::MatchPair {w c1 c2 {lim 1.0}} {
if {[string compare {} [set ix [$w search -back $c1 insert $lim]]]} {
while {
@ -4638,7 +4681,7 @@ proc ::tkcon::MatchPair {w c1 c2 {lim 1.0}} {
## The quote to match is assumed to be at the text index 'insert'.
# ARGS: w - console text widget
# Calls: ::tkcon::Blink
##
##
proc ::tkcon::MatchQuote {w {lim 1.0}} {
set i insert-1c
set j 0
@ -4664,7 +4707,7 @@ proc ::tkcon::MatchQuote {w {lim 1.0}} {
# i2 - end index of blink region
# dur - duration in usecs to blink for
# Outputs: blinks selected characters in $w
##
##
proc ::tkcon::Blink {w args} {
eval [list $w tag add blink] $args
after $::tkcon::OPT(blinktime) [list $w] tag remove blink $args
@ -4679,7 +4722,7 @@ proc ::tkcon::Blink {w args} {
# ARGS: w - text window in which to insert the string
# s - string to insert (usually just a single char)
# Outputs: $s to text widget
##
##
proc ::tkcon::Insert {w s} {
if {[string match {} $s] || [string match disabled [$w cget -state]]} {
return
@ -4695,7 +4738,7 @@ proc ::tkcon::Insert {w s} {
$w see insert
}
## ::tkcon::Expand -
## ::tkcon::Expand -
# ARGS: w - text widget in which to expand str
# type - type of expansion (path / proc / variable)
# Calls: ::tkcon::Expand(Pathname|Procname|Variable)
@ -4704,7 +4747,7 @@ proc ::tkcon::Insert {w s} {
# match equaled the string to expand, then all possible matches
# are output to stdout. Triggers bell if no matches are found.
# Returns: number of matches found
##
##
proc ::tkcon::Expand {w {type ""}} {
set exp "\[^\\\\\]\[\[ \t\n\r\\\{\"$\]"
set tmp [$w search -backwards -regexp $exp insert-1c limit-1c]
@ -4743,7 +4786,7 @@ proc ::tkcon::Expand {w {type ""}} {
# Calls: ::tkcon::ExpandBestMatch
# Returns: list containing longest unique match followed by all the
# possible further matches
##
##
proc ::tkcon::ExpandPathname str {
set pwd [EvalAttached pwd]
# Cause a string like {C:/Program\ Files/} to become "C:/Program Files/"
@ -4825,7 +4868,7 @@ proc ::tkcon::ExpandProcname str {
# Calls: ::tkcon::ExpandBestMatch
# Returns: list containing longest unique match followed by all the
# possible further matches
##
##
proc ::tkcon::ExpandVariable str {
if {[regexp {([^\(]*)\((.*)} $str junk ary str]} {
## Looks like they're trying to expand an array.
@ -4853,7 +4896,7 @@ proc ::tkcon::ExpandVariable str {
## or $e is {}. $e is extra for compatibility with proc below.
# ARGS: l - list to find best unique match in
# Returns: longest unique match in the list
##
##
proc ::tkcon::ExpandBestMatch2 {l {e {}}} {
set s [lindex $l 0]
if {[llength $l]>1} {
@ -4873,7 +4916,7 @@ proc ::tkcon::ExpandBestMatch2 {l {e {}}} {
# ARGS: l - list to find best unique match in
# e - currently best known unique match
# Returns: longest unique match in the list
##
##
proc ::tkcon::ExpandBestMatch {l {e {}}} {
set ec [lindex $l 0]
if {[llength $l]>1} {
@ -5237,7 +5280,7 @@ proc ::tkcon::Retrieve {} {
## ::tkcon::Resource - re'source's this script into current console
## Meant primarily for my development of this program. It follows
## links until the ultimate source is found.
##
##
set ::tkcon::PRIV(SCRIPT) [info script]
if {!$::tkcon::PRIV(WWW) && [string compare $::tkcon::PRIV(SCRIPT) {}]} {
# we use a catch here because some wrap apps choke on 'file type'