luke
/
netgen
mirror of https://github.com/RTimothyEdwards/netgen.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Corrected missing case (greater-than or equal instead of greater than) 

that affects vectors sliced across instance arrays.  Can cause vector
numbers to be out-of-bounds if an instance is arrayed but each
instance is listed separately.
This commit is contained in:
Tim Edwards 2019-09-10 10:52:15 -04:00
parent d38bd77825
commit f04c72b984
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
base/verilog.c
View File

@ -1752,7 +1752,7 @@ skip_endmodule:
// Instance must be an array
char netname[128];
int slice;
if (wb.start > wb.end && arraystart > arrayend)
if (wb.start >= wb.end && arraystart >= arrayend)
slice = wb.start - (arraystart - i);
else if (wb.start < wb.end && arraystart > arrayend)
slice = wb.start + (arraystart - i);
@ -1760,6 +1760,7 @@ skip_endmodule:
slice = wb.start - (arraystart + i);
else // (wb.start < wb.end && arraystart < arrayend)
slice = wb.start + (arraystart + i);
sprintf(netname, "%s[%d]", scanroot, slice);
if (LookupObject(netname, CurrentCell) == NULL) Node(netname);
join(netname, obptr->name);