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netgen
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Corrected a corner-case where a module with no ports in verilog 

was creating an implicit net for the stand-in "(no pins)" port.
This commit is contained in:
R. Timothy Edwards 2025-10-09 10:36:41 -04:00
parent 0e958bd45c
commit b5432d139b
2 changed files with 8 additions and 6 deletions
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2
VERSION
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@ -1 +1 @@
1.5.302
1.5.303

12
base/verilog.c
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@ -2614,13 +2614,15 @@ nextinst:
if (scan == NULL) {
char localnet[MAX_STR_LEN];
/* Assume an implicit unconnected pin */
sprintf(localnet, "_noconnect_%d_", localcount++);
Node(localnet);
join(localnet, obptr->name);
Fprintf(stdout,
/* Assume an implicit unconnected pin, unless there are no pins */
if (strcmp(obpinname, "(no pins)")) {
sprintf(localnet, "_noconnect_%d_", localcount++);
Node(localnet);
join(localnet, obptr->name);
Fprintf(stdout,
"Note: Implicit pin %s in instance %s of %s in cell %s\n",
obpinname, locinst, modulename, CurrentCell->name);
}
}
else if (GetBus(scan->net, &wb) == 0) {
char *bptr2;