Corrected an issue with shorted ports. When shorted ports are
connected only to ports and not to any devices, then they do not show up in NodeClasses() and so pass through most of the checks in MatchPins(). A separate correspondence check is needed to make sure that the same shorted ports appear in both netlists.
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609d1de250
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1efa054ac1
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@ -7428,6 +7428,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
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int result = 1, haspins = 0, notempty = 0;
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int hasproxy1 = 0, hasproxy2 = 0;
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int needclean1 = 0, needclean2 = 0;
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int *correspond;
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char *ostr;
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#ifdef TCL_NETGEN
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Tcl_Obj *mlist, *plist1, *plist2;
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@ -7681,6 +7682,8 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
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/* legal SPICE. */
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ob1 = tc1->cell;
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correspond = (int *)CALLOC((tc1->nodename_cache_maxnodenum + 1), sizeof(int));
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for (i = 0; i < numorig; i++) {
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bangptr1 = strrchr(ob1->name, '!');
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@ -7723,7 +7726,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
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(tc2->flags & CELL_PLACEHOLDER)) ||
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(NodeClasses == NULL))) {
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ob2->model.port = i; /* save order */
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ob2->model.port = i; /* save order */
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*(cover + i) = (char)1;
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if (Debug == 0) {
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@ -7752,6 +7755,63 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
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if (bangptr2) *bangptr2 = '!';
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break;
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}
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else if ((ob1->node != -1) && (ob2->node != -1)) {
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/* Check for the case of ports on both sides being shorted
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* together. That means that the nodes on both sides connect
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* only to ports, that they connec to the same number of ports,
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* and that each port pair has a matching name.
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*/
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int onlyports = 1;
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struct objlist *oba, *obb;
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for (oba = tc1->cell; oba != NULL; oba = oba->next) {
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if ((oba->node == ob1->node) && (oba->type != PORT)) {
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onlyports = 0;
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break;
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}
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}
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if (onlyports) {
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for (obb = tc2->cell; obb != NULL; obb = obb->next) {
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if ((obb->node == ob2->node) && (obb->type != PORT)) {
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onlyports = 0;
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break;
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}
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}
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}
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if (onlyports) {
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if ((correspond[ob1->node] == 0) || (correspond[ob1->node] == ob2->node)) {
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correspond[ob1->node] = ob2->node; /* remember corresponding node */
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ob2->model.port = i; /* save order */
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*(cover + i) = (char)1;
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if (Debug == 0) {
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for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
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for (m = left_col_end + 1; m < right_col_end; m++) *(ostr + m) = ' ';
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snprintf(ostr, left_col_end, "%s", ob1->name);
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snprintf(ostr + left_col_end + 1, left_col_end, "%s", ob2->name);
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for (m = 0; m < right_col_end + 1; m++)
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if (*(ostr + m) == '\0') *(ostr + m) = ' ';
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Fprintf(stdout, ostr);
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}
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else {
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Fprintf(stdout, "Circuit %s port %d \"%s\""
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" = cell %s port %d \"%s\"\n",
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tc1->name, i, ob1->name,
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tc2->name, j, ob2->name);
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}
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#ifdef TCL_NETGEN
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if (dolist) {
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Tcl_ListObjAppendElement(netgeninterp, plist1,
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Tcl_NewStringObj(ob1->name, -1));
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Tcl_ListObjAppendElement(netgeninterp, plist2,
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Tcl_NewStringObj(ob2->name, -1));
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}
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#endif
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}
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if (bangptr2) *bangptr2 = '!';
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break;
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}
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}
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}
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if (bangptr2) *bangptr2 = '!';
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j++;
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@ -7760,6 +7820,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
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ob1 = ob1->next;
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if (bangptr1) *bangptr1 = '!';
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}
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FREE(correspond);
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/* Find the end of the pin list in tc1, for adding proxy pins */
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@ -1017,13 +1017,12 @@ void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,
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char devtype, in_module, in_param;
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char *eqptr, *matchptr;
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struct keyvalue *kvlist = NULL;
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char inst[MAX_STR_LEN], model[MAX_STR_LEN], instname[MAX_STR_LEN], portname[MAX_STR_LEN], pkey[MAX_STR_LEN];
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char inst[MAX_STR_LEN], model[MAX_STR_LEN], portname[MAX_STR_LEN], pkey[MAX_STR_LEN];
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struct nlist *tp;
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struct objlist *parent, *sobj, *nobj, *lobj, *pobj, *cref;
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inst[MAX_STR_LEN-1] = '\0';
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model[MAX_STR_LEN-1] = '\0';
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instname[MAX_STR_LEN-1] = '\0';
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in_module = (char)0;
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in_param = (char)0;
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