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netgen
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Added a piece of code that handles implicit pins in verilog by doing 

the following:  (1) Checking that the parent cell is verilog,
(2) only running after the two cells themselves have been compared
and matched, then (3) added the missing pin or pins while reordering
pins on instances (note: this may not work if the verilog netlist is
the first passed to netgen;  that case needs to be checked).
This commit is contained in:
Tim Edwards 2024-02-02 14:51:10 -05:00
parent eb27a18ae3
commit c7fa0324d9
2 changed files with 31 additions and 3 deletions
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2
VERSION
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@ -1 +1 @@
1.5.265
1.5.266

32
base/netcmp.c
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@ -7184,7 +7184,7 @@ int reorderpins(struct hashlist *p, int file)
{
struct nlist *ptr;
struct nlist *tc2 = Circuit2;
struct objlist *ob, *ob2, *firstpin;
struct objlist *ob, *ob2, *firstpin, *oblast, *newob;
int i, numports, *nodes, unordered;
char **names;
@ -7236,6 +7236,7 @@ int reorderpins(struct hashlist *p, int file)
names[ob2->model.port] = ob->name;
}
oblast = ob;
ob = ob->next;
ob2 = ob2->next;
if (i < numports - 1) {
@ -7243,7 +7244,34 @@ int reorderpins(struct hashlist *p, int file)
Fprintf(stderr, "Instance of %s has only "
"%d of %d ports\n",
tc2->name, i + 1, numports);
break;
if (ptr->flags & CELL_VERILOG) {
/* If parent cell is verilog, and the cells
* have been matched, then the instance can
* be assumed to be using an implicit pin.
*/
Fprintf(stderr, "Assuming implicit verilog pin \"%s\".\n",
ob2->name);
newob = (struct objlist *)CALLOC(1,
sizeof(struct objlist));
newob->name = (char *)MALLOC(strlen(oblast->instance.name)
+ strlen(ob2->name) + 2);
sprintf(newob->name, "%s/%s",
oblast->instance.name, ob2->name);
newob->type = oblast->type + 1;
newob->model.class = strsave(oblast->model.class);
newob->instance.name = strsave(oblast->instance.name);
newob->flags = 0;
ptr->nodename_cache_maxnodenum++;
newob->node = ptr->nodename_cache_maxnodenum;
newob->next = ob;
oblast->next = newob; /* Splice into object list */
/* Fill in the missing entries */
nodes[ob2->model.port] = newob->node;
names[ob2->model.port] = newob->name;
ob = newob;
}
else
break;
}
else if (ob2 == NULL || ob2->type != PORT) {
Fprintf(stderr, "Instance of %s has "