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netgen
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Fix missing prototype for ReadVerilogFile function 

Unbreak OpenBSD port for mips64 arch
This commit is contained in:
Alessandro De Laurenzis 2021-01-17 10:21:52 +01:00
parent 0df6c83df5
commit 8a7bb7f2ca
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3 changed files with 9 additions and 14 deletions
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9
base/netgen.h
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@ -65,6 +65,15 @@ extern void AssignCircuits(char *name1, int file1, char *name2, int file2);
/* flatten.c */
extern int PrematchLists(char *, int, char *, int);
/* verilog.c */
struct cellstack {
char *cellname;
struct cellstack *next;
};
void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,
int blackbox);
/* Define (enumerate) various device classes, largely based on SPICE */
/* model types, mixed with some ext/sim types. */

9
base/spice.c
View File

@ -473,15 +473,6 @@ void CleanupSubcell() {
SetClass(CLASS_MODULE);
}
/*------------------------------------------------------*/
/* Structure for stacking nested subcircuit definitions */
/*------------------------------------------------------*/
struct cellstack {
char *cellname;
struct cellstack *next;
};
/*------------------------------------------------------*/
/* Push a subcircuit name onto the stack */
/*------------------------------------------------------*/

5
base/verilog.c
View File

@ -632,11 +632,6 @@ void CleanupModule() {
/* Structure for stacking nested module definitions */
/*------------------------------------------------------*/
struct cellstack {
char *cellname;
struct cellstack *next;
};
/* Forward declarations */
extern void IncludeVerilog(char *, int, struct cellstack **, int);