Tracked down and fixed problems with implicit pins in verilog (pins
that are not declared in the verilog netlist because they don't connect to anything, and their presence is not required by verilog syntax) and the printing of proxy pins created to act as placeholders for those implicit pins. Also removed the pinting of the "disconnected pin" messages for black-box modules (since by definition they have disconnected pins, because black-box modules have no contents).
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@ -6918,6 +6918,8 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
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if (*(cover + i) == (char)0) {
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j = 0;
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for (ob2 = tc2->cell; ob2 != NULL; ob2 = ob2->next) {
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char *name1, *name2;
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if (!IsPort(ob2)) break;
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bangptr2 = strrchr(ob2->name, '!');
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@ -6925,7 +6927,14 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
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*bangptr2 = '\0';
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else bangptr2 = NULL;
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if ((*matchfunc)(ob1->name, ob2->name)) {
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name1 = ob1->name;
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name2 = ob2->name;
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/* Recognize proxy pins as matching */
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if (!strncmp(name1, "proxy", 5)) name1 +=5;
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if (!strncmp(name2, "proxy", 5)) name2 +=5;
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if ((*matchfunc)(name1, name2)) {
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ob2->model.port = i; /* save order */
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*(cover + i) = (char)1;
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@ -7032,7 +7041,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
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obn->name = (char *)MALLOC(6 + strlen(ob2->name));
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sprintf(obn->name, "proxy%s", ob2->name);
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obn->type = UNKNOWN;
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obn->model.port = -1;
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// obn->model.port = -1;
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obn->instance.name = NULL;
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obn->node = -1;
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if (ob1 == tc1->cell) {
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@ -7102,6 +7111,22 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
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obn->instance.name = NULL;
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obn->node = -1;
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if (Debug == 0) {
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if (strcmp(ob1->name, "(no pins)")) {
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for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
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for (m = left_col_end + 1; m < right_col_end; m++) *(ostr + m) = ' ';
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snprintf(ostr, left_col_end, "%s", ob1->name);
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snprintf(ostr + left_col_end + 1, left_col_end, "(no matching pin)");
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for (m = 0; m < right_col_end + 1; m++)
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if (*(ostr + m) == '\0') *(ostr + m) = ' ';
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Fprintf(stdout, ostr);
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}
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}
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else {
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Fprintf(stderr, "No netlist match for cell %s pin %s\n",
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tc1->name, ob1->name);
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}
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if (ob2 == tc2->cell) {
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obn->next = ob2;
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tc2->cell = obn;
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@ -801,7 +801,11 @@ void DescribeInstance(char *name, int file)
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{
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if (ob->node > nodemax) nodemax = ob->node;
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else if ((ob->node == -1) && (ob->model.port != PROXY)) {
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if (!(tp->flags & CELL_PLACEHOLDER))
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/* All black-box modules and placeholders by definition have all */
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/* disconnected pins, so don't report those. */
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if (!(tp->flags & CELL_PLACEHOLDER) && (tp->class != CLASS_MODULE))
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{
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if (disconnectednodes == 0) Fprintf(stderr, "\n");
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disconnectednodes++;
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