An example found by Leo Moser showed that netgen makes an incorrect

pin assignment when a verilog input file declares a signal "bundle"
with only one signal in it.  The solution is to detect bundles which
have only one component in them, and remove the bundle delimiters
("{...}") so that the pin connection is treated as a simple signal
or vector.

VERSION

@@ -1 +1 @@
-1.5.319
+1.5.320

base/verilog.c

@@ -2295,7 +2295,18 @@ nextinst:
 			 FREE(wire_bundle);
 			 wire_bundle = new_wire_bundle;
 			 if (!strcmp(nexttok, "}"))
+			 {
+			    /* If a "bundle" has only one component, then it is
+			     * not really a bundle and should be treated as a
+			     * single wire.
+			     */
+			    if (strchr(wire_bundle, ',') == NULL) {
+				int blen = strlen(wire_bundle + 1) - 1;
+				memmove(wire_bundle, wire_bundle + 1, blen);
+				*(wire_bundle + blen) = '\0';
+			    }
 			    break;
+			 }
 			 SkipTokComments(VLOG_PIN_CHECK_DELIMITERS);
 		     }
 		     if (!nexttok) {