Added support for converting a SPICE file to a SIM file simulatable
with IRSIM including recent changes made to support multiple device types using the subcircuit "x" component type. This requires reading in a .prm file, which incidentally can be used with any SPICE file to inform netgen of the specific component type of any model defined as a subcircuit.
This commit is contained in:
parent
ec0e097fcf
commit
eabb898578
293
base/ext.c
293
base/ext.c
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@ -31,6 +31,8 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "print.h"
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#include "hash.h"
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static int invlambda = 100; /* Used in sim and prm files */
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void extCell(char *name, int filenum)
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{
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struct nlist *tp, *tp2;
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@ -450,7 +452,8 @@ void simCell(char *name, int filenum)
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struct nlist *tp, *tp2;
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struct objlist *ob, *ob2;
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char FileName[500], simclass;
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short i;
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char writeLine[1024], paramString[128];
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short i, p, mult;
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double l, w, v;
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tp = LookupCellFile(name, filenum);
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@ -459,6 +462,11 @@ void simCell(char *name, int filenum)
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return;
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}
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/* Check procedure disabled because new extensions to .sim format
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* allow 'x' records to represent low-level components that are
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* modeled as SPICE subcircuits.
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*/
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#if 0
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/* check to see that all children have been dumped */
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ob = tp->cell;
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while (ob != NULL) {
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@ -470,6 +478,7 @@ void simCell(char *name, int filenum)
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}
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ob = ob->next;
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}
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#endif
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SetExtension(FileName, name, SIM_EXTENSION);
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if (!OpenFile(FileName, 0)) {
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@ -478,9 +487,9 @@ void simCell(char *name, int filenum)
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}
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/* print out header list */
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/* distance units are multiplied by 100 (distances are in um) */
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/* distance units are multiplied by invlambda */
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FlushString("| units: 100 tech: scmos\n");
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FlushString("| units: %d tech: scmos\n", 100 * invlambda);
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/* now run through cell's contents, print instances */
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for (ob = tp->cell; ob != NULL; ob = ob->next) {
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@ -516,13 +525,17 @@ void simCell(char *name, int filenum)
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case CLASS_NPN:
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simclass = 'b';
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break;
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default:
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case CLASS_SUBCKT:
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case CLASS_MODULE:
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simclass = 'x';
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break;
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default:
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simclass = '|';
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break;
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}
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if (simclass != 'x')
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FlushString("%c", simclass);
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FlushString("%c", simclass);
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switch (tp2->class) {
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case CLASS_NMOS: case CLASS_NMOS4:
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@ -590,6 +603,97 @@ void simCell(char *name, int filenum)
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FlushString(" %g\n", v);
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break;
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case CLASS_SUBCKT: case CLASS_MODULE:
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*writeLine = 'x';
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*(writeLine + 1) = '\0';
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mult = 1;
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ob2 = ob;
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while (ob2 != NULL) {
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strcat(writeLine, " ");
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strcat(writeLine, NodeAlias(tp, ob2));
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ob2 = ob2->next;
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if ((ob2 == NULL) || (ob2->type <= FIRSTPIN)) break;
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}
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if (ob2 && ob2->type == PROPERTY) {
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struct valuelist *vl;
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/* Only known parameters are L, W, X, and Y */
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for (p = 0;; p++) {
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vl = (struct valuelist *)(&(ob2->instance.props[p]));
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if (vl->type == PROP_ENDLIST) {
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strcat(writeLine, " l=1");
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break;
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}
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else if ((*matchfunc)(vl->key, "L")) {
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v = vl->value.dval;
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sprintf(paramString, " l=%d", (int)(0.5 + (v * invlambda)));
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strcat(writeLine, paramString);
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break;
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}
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}
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for (p = 0;; p++) {
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vl = (struct valuelist *)(&(ob2->instance.props[p]));
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if (vl->type == PROP_ENDLIST) {
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strcat(writeLine, " w=1");
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break;
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}
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else if ((*matchfunc)(vl->key, "W")) {
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v = vl->value.dval;
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sprintf(paramString, " w=%d", (int)(0.5 + (v * invlambda)));
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strcat(writeLine, paramString);
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break;
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}
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}
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for (p = 0;; p++) {
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vl = (struct valuelist *)(&(ob2->instance.props[p]));
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if (vl->type == PROP_ENDLIST) {
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strcat(writeLine, " x=0");
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break;
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}
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else if ((*matchfunc)(vl->key, "X")) {
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i = vl->value.ival;
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sprintf(paramString, " x=%d", i);
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strcat(writeLine, paramString);
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break;
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}
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}
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for (p = 0;; p++) {
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vl = (struct valuelist *)(&(ob2->instance.props[p]));
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if (vl->type == PROP_ENDLIST) {
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strcat(writeLine, " y=0");
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break;
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}
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else if ((*matchfunc)(vl->key, "Y")) {
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i = vl->value.ival;
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sprintf(paramString, " y=%d", i);
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strcat(writeLine, paramString);
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}
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}
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for (p = 0;; p++) {
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vl = (struct valuelist *)(&(ob2->instance.props[p]));
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if (vl->type == PROP_ENDLIST) {
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break;
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}
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else if ((*matchfunc)(vl->key, "M")) {
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if (vl->type == PROP_INTEGER)
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mult = vl->value.ival;
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else
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mult = vl->value.dval;
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}
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}
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}
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strcat(writeLine, " ");
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strcat(writeLine, tp2->name);
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strcat(writeLine, "\n");
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/* Multiple instances (M != 1) are written multiple times.
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* NF is ignored in favor of having a single device with
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* the total width.
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*/
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for (i = 0; i < mult; i++)
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FlushString(writeLine);
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break;
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default:
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FlushString("| unhandled component %s\n", tp2->name);
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break;
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@ -626,6 +730,181 @@ int StrIsInt(char *s)
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return (1);
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}
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/*------------------------------------------------------*/
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/* Read a .prm format file. This is specifically to */
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/* get the "device" lines that indicate how a SPICE */
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/* subcircuit model or a .sim "x" record needs to be */
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/* translated into a specific component type like a */
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/* FET, diode, resistor, etc. */
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/*------------------------------------------------------*/
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char *ReadPrm(char *fname, int *fnum)
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{
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int filenum;
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struct keyvalue *kvlist = NULL;
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struct nlist *tp;
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if ((filenum = OpenParseFile(fname, *fnum)) < 0) {
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char name[MAX_STR_LEN];
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SetExtension(name, fname, PRM_EXTENSION);
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if (OpenParseFile(name, *fnum) < 0) {
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Printf("Error in prm file read: No file %s\n",name);
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*fnum = filenum;
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return NULL;
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}
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}
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/* Make sure all .prm file reading is case INsensitive */
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/* This is because the only reason to read a PRM file */
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/* is to find all the subcircuit device types so that */
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/* a SPICE file can be read and a SIM file written. */
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matchfunc = matchnocase;
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matchintfunc = matchfile;
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hashfunc = hashnocase;
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CellDef(fname, filenum);
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while (!EndParseFile()) {
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char devicename[MAX_STR_LEN];
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SkipTok(NULL);
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if (EndParseFile()) break;
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if (nexttok[0] == ';') continue; /* Comment line */
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else if (nexttok[0] == '\0') continue; /* Blank line */
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else if (match(nexttok, "lambda")) {
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SkipTok(NULL);
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invlambda = (int)(0.5 + (1.0 / atof(nexttok)));
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SkipNewLine(NULL); /* skip any attributes */
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}
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else if (match(nexttok, "device")) {
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SkipTok(NULL);
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if (match(nexttok, "nfet")) {
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SkipTok(NULL);
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strcpy(devicename, nexttok);
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/* Create 4-terminal nfet subcircuit device record */
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if (LookupCellFile(devicename, filenum) == NULL) {
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CellDef(devicename, filenum);
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Port("gate");
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Port("source");
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Port("drain");
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Port("bulk");
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PropertyDouble(devicename, filenum, "l", 0.01, 0.0);
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PropertyDouble(devicename, filenum, "w", 0.01, 0.0);
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PropertyInteger(devicename, filenum, "nf", 0, 1);
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PropertyInteger(devicename, filenum, "m", 0, 1);
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SetClass(CLASS_SUBCKT);
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EndCell();
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ReopenCellDef(fname, filenum);
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}
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LinkProperties(devicename, kvlist);
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SkipNewLine(NULL); /* skip any attributes */
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}
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else if (match(nexttok, "pfet")) {
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SkipTok(NULL);
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strcpy(devicename, nexttok);
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/* Create 4-terminal pfet subcircuit device record */
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if (LookupCellFile(devicename, filenum) == NULL) {
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CellDef(devicename, filenum);
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Port("gate");
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Port("source");
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Port("drain");
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Port("well");
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PropertyDouble(devicename, filenum, "l", 0.01, 0.0);
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PropertyDouble(devicename, filenum, "w", 0.01, 0.0);
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PropertyInteger(devicename, filenum, "nf", 0, 1);
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PropertyInteger(devicename, filenum, "m", 0, 1);
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SetClass(CLASS_SUBCKT);
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EndCell();
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ReopenCellDef(fname, filenum);
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}
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LinkProperties(devicename, kvlist);
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SkipNewLine(NULL); /* skip various attributes */
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}
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else if (match(nexttok, "resistor")) {
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SkipTok(NULL);
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strcpy(devicename, nexttok);
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/* Resistor device has additional record for the value */
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/* (Need to do something with this. . . ?) */
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SkipTok(NULL);
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/* Create resistor subcircuit device record */
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if (LookupCellFile(devicename, filenum) == NULL) {
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CellDef(devicename, filenum);
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Port("end_a");
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Port("end_b");
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PropertyDouble(devicename, filenum, "value", 0.01, 0.0);
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PropertyDouble(devicename, filenum, "l", 0.01, 0.0);
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PropertyDouble(devicename, filenum, "w", 0.01, 0.0);
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PropertyInteger(devicename, filenum, "m", 0, 1);
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SetClass(CLASS_SUBCKT);
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EndCell();
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ReopenCellDef(fname, filenum);
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}
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LinkProperties(devicename, kvlist);
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SkipNewLine(NULL); /* skip various attributes */
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}
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else if (match(nexttok, "capacitor")) {
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SkipTok(NULL);
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strcpy(devicename, nexttok);
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/* Capacitor device has additional record for the value */
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/* (Need to do something with this. . . ?) */
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SkipTok(NULL);
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/* Create capacitor subcircuit device record */
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if (LookupCellFile(devicename, filenum) == NULL) {
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CellDef(devicename, filenum);
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Port("top");
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Port("bottom");
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PropertyDouble(devicename, filenum, "value", 0.01, 0.0);
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PropertyDouble(devicename, filenum, "l", 0.01, 0.0);
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PropertyDouble(devicename, filenum, "w", 0.01, 0.0);
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PropertyInteger(devicename, filenum, "m", 0, 1);
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SetClass(CLASS_SUBCKT);
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EndCell();
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ReopenCellDef(fname, filenum); /* Reopen */
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}
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LinkProperties(devicename, kvlist);
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SkipNewLine(NULL);
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}
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else if (match(nexttok, "diode")) {
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SkipTok(NULL);
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strcpy(devicename, nexttok);
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/* Create diode subcircuit device record */
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if (LookupCellFile(devicename, filenum) == NULL) {
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CellDef(devicename, filenum);
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Port("anode");
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Port("cathode");
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PropertyInteger(devicename, filenum, "m", 0, 1);
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SetClass(CLASS_SUBCKT);
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EndCell();
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ReopenCellDef(fname, filenum); /* Reopen */
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}
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LinkProperties(devicename, kvlist);
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SkipNewLine(NULL);
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}
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else {
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Printf("Unknown device type in .prm: '%s'\n", nexttok);
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InputParseError(stderr);
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SkipNewLine(NULL);
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}
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}
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else {
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/* Could spell out all the keywords used in .prm files */
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/* but probably not worth the effort. */
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SkipNewLine(NULL);
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}
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DeleteProperties(&kvlist);
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}
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EndCell();
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CloseParseFile();
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tp = LookupCellFile(fname, filenum);
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if (tp) tp->flags |= CELL_TOP;
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*fnum = filenum;
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return fname;
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}
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/*-------------------------*/
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/* Read a .sim format file */
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/*-------------------------*/
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@ -644,7 +923,7 @@ char *ReadSim(char *fname, int *fnum)
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SetExtension(name, fname, SIM_EXTENSION);
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if (OpenParseFile(name, *fnum) < 0) {
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Printf("Error in ext file read: No file %s\n",name);
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Printf("Error in sim file read: No file %s\n",name);
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*fnum = filenum;
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return NULL;
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}
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@ -847,7 +1126,7 @@ char *ReadSim(char *fname, int *fnum)
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}
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else if (match(nexttok, "r")) { /* 2-port resistors */
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if (IgnoreRC) {
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/* ignore all capacitances */
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/* ignore all resistances */
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SkipNewLine(NULL);
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}
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else {
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@ -886,7 +886,7 @@ char *ReadNetlist(char *fname, int *fnum)
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};
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#ifdef mips
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struct filetype formats[7];
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struct filetype formats[8];
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formats[0].extension = NTK_EXTENSION;
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formats[0].proc = ReadNtk;
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@ -894,14 +894,16 @@ char *ReadNetlist(char *fname, int *fnum)
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formats[1].proc = ReadExtHier;
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formats[2].extension = SIM_EXTENSION;
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formats[2].proc = ReadSim;
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formats[3].extension = SPICE_EXTENSION;
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formats[3].proc = ReadSpice;
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formats[4].extension = NETGEN_EXTENSION;
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formats[4].proc = ReadNetgenFile;
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formats[5].extension = VERILOG_EXTENSION;
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formats[5].proc = ReadVerilogFile;
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formats[6].extension = NULL;
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formats[6].proc = NULL;
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formats[3].extension = PRM_EXTENSION;
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formats[3].proc = ReadPrm;
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formats[4].extension = SPICE_EXTENSION;
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formats[4].proc = ReadSpice;
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formats[5].extension = NETGEN_EXTENSION;
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formats[5].proc = ReadNetgenFile;
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formats[6].extension = VERILOG_EXTENSION;
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formats[6].proc = ReadVerilogFile;
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formats[7].extension = NULL;
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formats[7].proc = NULL;
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#else /* not mips (i.e. compiler with reasonable initializers) */
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@ -910,6 +912,7 @@ char *ReadNetlist(char *fname, int *fnum)
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{NTK_EXTENSION, ReadNtk},
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{EXT_EXTENSION, ReadExtHier},
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{SIM_EXTENSION, ReadSim},
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{PRM_EXTENSION, ReadPrm},
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{SPICE_EXTENSION, ReadSpice},
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{SPICE_EXT2, ReadSpice},
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{SPICE_EXT3, ReadSpice},
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@ -7,6 +7,7 @@
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#define WOMBAT_EXTENSION ".wom"
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#define EXT_EXTENSION ".ext"
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#define SIM_EXTENSION ".sim"
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#define PRM_EXTENSION ".prm"
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#define SPICE_EXTENSION ".spice"
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#define SPICE_EXT2 ".spc"
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#define SPICE_EXT3 ".sp"
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@ -191,6 +191,7 @@ extern char *ReadNtk (char *fname, int *fnum);
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extern char *ReadExtHier(char *fname, int *fnum);
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extern char *ReadExtFlat(char *fname, int *fnum);
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extern char *ReadSim(char *fname, int *fnum);
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extern char *ReadPrm(char *fname, int *fnum);
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extern char *ReadSpice(char *fname, int *fnum);
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extern char *ReadSpiceLib(char *fname, int *fnum);
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extern char *ReadNetgenFile (char *fname, int *fnum);
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@ -707,11 +707,11 @@ _netgen_readnet(ClientData clientData,
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Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
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{
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char *formats[] = {
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"automatic", "ext", "extflat", "sim", "ntk", "spice",
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"automatic", "ext", "extflat", "sim", "prm", "ntk", "spice",
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"verilog", "netgen", "actel", "xilinx", NULL
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};
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enum FormatIdx {
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AUTO_IDX, EXT_IDX, EXTFLAT_IDX, SIM_IDX, NTK_IDX,
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AUTO_IDX, EXT_IDX, EXTFLAT_IDX, SIM_IDX, PRM_IDX, NTK_IDX,
|
||||
SPICE_IDX, VERILOG_IDX, NETGEN_IDX, ACTEL_IDX, XILINX_IDX
|
||||
};
|
||||
struct nlist *tc;
|
||||
|
|
@ -807,6 +807,9 @@ _netgen_readnet(ClientData clientData,
|
|||
case SIM_IDX:
|
||||
retstr = ReadSim(savstr, &filenum);
|
||||
break;
|
||||
case PRM_IDX:
|
||||
retstr = ReadPrm(savstr, &filenum);
|
||||
break;
|
||||
case NTK_IDX:
|
||||
retstr = ReadNtk(savstr, &filenum);
|
||||
break;
|
||||
|
|
|
|||
Loading…
Reference in New Issue