luke
/
netgen
mirror of https://github.com/RTimothyEdwards/netgen.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Modified some of the verilog read-in code to avoid a segmentation 

fault that would happen if the verilog had illegal syntax of a
misspelled net name (although normally netgen is expected not to
have to check the verilog for syntax, and there are probably many
such cases of netgen failing to handle incorrect verilog and then
crashing as a result).
This commit is contained in:
Tim Edwards 2023-09-01 09:04:44 -04:00
parent 615c55cbe2
commit c27d933adc
2 changed files with 12 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
VERSION
View File

@ -1 +1 @@
1.5.256
1.5.257

13
base/verilog.c
View File

@ -1898,12 +1898,21 @@ skip_endmodule:
if (i != -1)
snprintf(nodename, MAX_STR_LEN, "%s[%d]", noderoot, i);
else
else if (lhs != NULL)
strncpy(nodename, lhs->name, MAX_STR_LEN - 1);
else {
Printf("Error: Improper node name \"%s\".\n", noderoot);
goto skip_endmodule;
}
if (j != -1)
snprintf(assignname, MAX_STR_LEN, "%s[%d]", assignroot, j);
else
else if (rhs != NULL)
strncpy(assignname, rhs->name, MAX_STR_LEN - 1);
else {
Printf("Error: Improper assignment name \"%s\".\n",
assignroot);
goto skip_endmodule;
}
join(nodename, assignname);