Found examples where the automated "pin matching" algorithm causes
the top level circuits to be declared matching with no errors even though the pins do not match. "proxy pins" are fine for subcells to detect cases where one subcell has an unused pin and the matching subcell does not declare it, but that should not be allowed on the top level, as it cannot be known whether the pin is unused or not.
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@ -7132,6 +7132,8 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
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obn->instance.name = NULL;
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obn->node = -1;
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#if 0
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/* Note: This pin has already been accounted for */
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if (Debug == 0) {
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if (strcmp(ob1->name, "(no pins)")) {
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for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
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@ -7147,6 +7149,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
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Fprintf(stderr, "No netlist match for cell %s pin %s\n",
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tc1->name, ob1->name);
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}
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#endif
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if (ob2 == tc2->cell) {
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obn->next = ob2;
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@ -501,6 +501,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
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return
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}
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set properr {}
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set pinsgood 0
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while {$endval != {}} {
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if {$dolist == 1} {
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netgen::run -list converge
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@ -546,6 +547,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
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equate classes "$fnum1 [lindex $endval 0]" \
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"$fnum2 [lindex $endval 1]"
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}
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set pinsgood $result
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netgen::log echo on
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}
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if {$uresult == 2} {lappend properr [lindex $endval 0]}
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@ -569,7 +571,11 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
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netgen::log echo off
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puts stdout "Result: " nonewline
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netgen::log echo on
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verify only
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if {$pinsgood == 0} {
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netgen::log put "The top level cell failed pin matching.\n"
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} else {
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verify only
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}
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if {$properr != {}} {
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netgen::log put "The following cells had property errors: $properr\n"
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}
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