Fischer Moseley
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4e93a049cd
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docs: deploy using mike in CI
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2024-10-06 11:25:14 -06:00 |
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Fischer Moseley
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3fb5bfb4ad
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ci: run codecov directly instead of via GitHub Action
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2024-09-10 13:45:40 -06:00 |
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Fischer Moseley
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354309394d
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meta: export JSON during tests for codecov to injest
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2024-09-10 10:09:56 -06:00 |
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Fischer Moseley
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129f991dda
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meta: add codecov
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2024-09-10 07:17:50 -06:00 |
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Fischer Moseley
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e0aeb38cdb
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update docs
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2024-03-07 12:25:30 -08:00 |
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Fischer Moseley
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d075c04e2a
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update makefile to not require python scripts on PATH
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2024-01-21 00:47:14 -08:00 |
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Fischer Moseley
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bc616fd3bf
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inital source, imported from splat
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2023-12-28 14:22:29 -08:00 |
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Fischer Moseley
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060583d8fc
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add working io_core autogeneration
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2023-09-04 23:03:49 -04:00 |
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Fischer Moseley
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49021411ea
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add beginnings of working io_core with CDC/large inputs
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2023-09-04 23:03:49 -04:00 |
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Fischer Moseley
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23418066f9
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remove uart_rx formal
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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a841994fec
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remove .Xil folder after build
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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78a7cce83a
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add logic_analyzer_uart example
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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44a8c57dc5
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swap to zipcpu uart_rx
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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3af6f6ff0c
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add block_mem_uart example
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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6d3a32a988
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update lots of docs
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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c37a6e5e90
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move icestick build steps to makefile
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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179b3a8283
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update makefile
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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30f6e43916
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update makefile to reset build agent
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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17c91ffc34
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update makefile
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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0044ae5884
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merge nexys makefile targets
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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7e707e1fc1
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manually specify vivado path in makefile
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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b9318e9bf0
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make examples not require python scripts directory on path
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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6aa27e431e
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build examples on self-hosted runner
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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7ed4a9e6b8
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polish uart testbenches
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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56b2442df7
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move uart code for verification to test/
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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d580419a5b
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remove lut_mem, clean up examples
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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0840786914
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enforce consistent folder naming
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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c591c9c6ea
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update makefile targets
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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54022fff8d
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make obj/ if does not exist
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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da4920d89d
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fetch lab-bc on the fly, archive build outputs
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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2b483b1beb
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add bridge_rx formal to makefile
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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adf355c633
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make examples build
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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788c616b37
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update makefile and CI
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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ac23e8a599
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make functional sim run again
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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1a536080f1
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rewrite bridge_rx and add basic formal
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2023-09-02 11:39:16 -04:00 |
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Fischer Moseley
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df2dbf4ec6
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update makefile to reflect new paths
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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cef5e9318b
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flip i and j, and see the light
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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15aa5f469f
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add ethernet_tx_tb
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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2c461ed08d
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add working ethernet_tx testbench
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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9c5ea31d14
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enforce consistent naming of lut_mem module
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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b3d402c1f5
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refactor python/hdl structure
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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c507f795f1
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add ethernet_tx/rx, semi-working in hardware
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2023-04-28 14:57:36 -04:00 |
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Fischer Moseley
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ca814df63e
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forgot a semicolon in the makefile
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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1aa067b435
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update logic_analyzer_tb to use only generated HDL
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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102bdee410
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update makefile to match positional args from PATH'd binaries
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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a2ad90a66a
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modify sim and generator, seems to work in simulation
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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bdca8e01e7
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add boilerplate for new modules - just gotta rewrite the fsm
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2023-04-17 18:14:31 -04:00 |
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Fischer Moseley
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d8eeb65b8f
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fix pipelining in video_sprite exmaple
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2023-04-13 18:00:22 -04:00 |
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Fischer Moseley
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ba6100ce30
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import tutorial from yesterday, add mostly working bram core
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2023-04-12 11:47:50 -04:00 |
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Fischer Moseley
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12f498dc9a
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add cursed BRAM core implementation
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2023-04-10 14:38:29 -04:00 |