1f8bf643fd
docs: add mike
2024-10-06 10:52:23 -06:00
24b4ca2468
docs: add mention of CSV export from logic analyzer
2024-07-17 19:47:18 -07:00
67103ad70e
doc: remove warning about bidirectional mem cores on xilinx platforms
2024-07-17 18:51:05 -07:00
13bc196a34
rename Nexys A7 to Nexys 4 DDR
2024-05-12 10:35:18 -07:00
7957e5d74e
doc: change WaveDrom render branch to main
2024-04-14 16:11:46 -06:00
f6127791c7
doc: add inline CSS to fix WaveDrom renders in dark mode
2024-04-14 16:11:46 -06:00
b35bfa1152
doc: fix typo and migrate read timing diagram
2024-04-14 16:11:46 -06:00
697d6a00d9
doc: directly render read transaction timing diagram
2024-04-14 16:11:46 -06:00
7a44f34ae3
tweak wording of active low reset warning
2024-04-05 23:46:54 -07:00
af0dec7d76
Updated reset note and a doc link
2024-04-05 19:03:01 -05:00
ccc75270a8
Update getting_started.md
...
I was working through using Manta for the first time, and the only bit that gave me a struggle so far was that I was expecting the `rst` signal to be active LOW. I thought this might be worth calling out in the documentation here.
Awesome project btw, will definitely be using it more and try to contribute as I can! 😄
2024-03-31 23:17:03 -05:00
1a7adf4c63
add udev rule to docs
2024-03-14 10:28:37 -07:00
e0aeb38cdb
update docs
2024-03-07 12:25:30 -08:00
0b2c286075
pull latest from main
2024-03-06 11:31:35 -08:00
25ebae42e2
add GateMate ILA to alternatives
2024-03-03 13:57:52 -08:00
6aea5cc6e1
update MemoryCore references
2024-03-02 12:52:04 -08:00
a4d549f6f1
update static site to match README formatting
2024-02-29 15:20:11 -05:00
75a0fe46ff
fix PLL information in Ethernet docs
2024-02-10 01:13:11 -08:00
63e912fb63
fix grammar and diagrams
2024-02-09 22:49:58 -08:00
510bae6f38
add MATLAB fpga data capture to alternatives, thanks nathan
2024-01-22 00:03:54 -08:00
b8de6339aa
adjust some ergonomics found while playtesting
2024-01-21 00:23:07 -08:00
2b95fea496
update docs, bump required python to 3.8
2024-01-13 15:05:45 -08:00
ee4a3026af
refactor to use common bus layout across all modules
2024-01-07 18:17:09 -08:00
e2daf94f3f
remove unneeded diagram
2024-01-05 23:43:47 -08:00
89f1dcde1c
convert diagrams to .drawio.svg format
2024-01-05 23:01:57 -08:00
a1130e8424
update docs in response to feedback from Joe
2023-09-11 19:09:42 -07:00
dbdb379c56
update docs with GitHub Actions config
2023-09-11 09:47:09 -07:00
1e30f70a97
fix (another) typo in io_core example
2023-09-04 23:10:18 -04:00
c6dc1af6f2
fix typo in io_core example
2023-09-04 23:09:53 -04:00
3ce8594247
update docs with new IO core options
2023-09-04 23:03:49 -04:00
3fe95b75d8
upate image names
2023-09-02 09:54:20 -07:00
63760adef9
fix broken links
2023-09-02 09:33:42 -07:00
c436873296
fix images on docs site
2023-09-02 09:29:26 -07:00
245ff33b0a
move roadmap to github issues
2023-09-02 11:39:16 -04:00
f60ec0c0e3
finish most of docs ahead of v1
2023-09-02 11:39:16 -04:00
f902d07b1d
update read responses to use D as preamble
2023-09-02 11:39:16 -04:00
6401ab6020
update bram docs
2023-09-02 11:39:16 -04:00
833c3e5ca5
one last doc change
2023-09-02 11:39:16 -04:00
d497f80d2a
logic analyzer docs
2023-09-02 11:39:16 -04:00
7340ccbbcb
more docs
2023-09-02 11:39:16 -04:00
6d3a32a988
update lots of docs
2023-09-02 11:39:16 -04:00
6aa27e431e
build examples on self-hosted runner
2023-09-02 11:39:16 -04:00
c76a6de585
fix broken link in io core tutorial
2023-09-02 11:39:16 -04:00
86e491b432
update io core example
2023-09-02 11:39:16 -04:00
7ed4a9e6b8
polish uart testbenches
2023-09-02 11:39:16 -04:00
0132d8fab0
update roadmap
2023-09-02 11:39:16 -04:00
d580419a5b
remove lut_mem, clean up examples
2023-09-02 11:39:16 -04:00
d67ac9c799
add thesis pdf
2023-07-06 22:28:49 -07:00
9c5ea31d14
enforce consistent naming of lut_mem module
2023-04-28 14:57:36 -04:00
7cd8a2cfa5
tidy up mac stack
2023-04-28 14:57:36 -04:00
Fischer Moseley
Kenneth Wilke
Fischer Moseley