add MATLAB fpga data capture to alternatives, thanks nathan

doc/alternatives.md

@@ -58,4 +58,11 @@ An embedded logic analyzer for Lattice FPGAs, provided as part of the Diamond de
 Unlike other entries in this list, Opal Kelly's FrontPanel SDK is not marketed as a debugger (although it can be used as such). Instead, it's designed to provide a host computer with a real time interface to FGPA signals, and present them on a graphical “front panel". These front panels exist as a GUI window on the host, and contain buttons, knobs, and indicators, much like a LabVIEW virtual instrument. Communication between the host and FPGA is accomplished with either USB or PCIe. Bindings for hosts running Windows, macOS, and Linux are provided, and target C, C++, C#, Python, Java, Ruby, and MATLAB. The FrontPanel SDK differs from other debuggers in that it provides a skeleton module into which the user logic is instantiated, instead of being instantiated inside the user's logic.
 
 - [Documentation](https://docs.opalkelly.com/fpsdk/)
-- [User's Guide](https://assets00.opalkelly.com/library/FrontPanel-UM.pdf)
+- [User's Guide](https://assets00.opalkelly.com/library/FrontPanel-UM.pdf)
+
+
+### MATLAB FPGA Data Capture
+
+An embedded logic analyzer for Xilinx and Altera FPGAs, provided as part of MATLAB. Communication between the host and FPGA is accomplished with JTAG, but Ethernet is supported for Xilinx FPGAs. Notably, this tool allows for data to be captured and used directly inside MATLAB, which also includes a framework for FPGA-in-the-loop testing. It also provides an AXI manager IP block that allows for reads and writes to an AXI memory map from MATLAB. This IP supports PCI Express on Xilinx FPGAs, in addition to JTAG and Ethernet.
+
+- [Documentation](https://www.mathworks.com/help/hdlverifier/fpga-data-capture-xilinx.html)