4e93a049cd
docs: deploy using mike in CI
2024-10-06 11:25:14 -06:00
1f8bf643fd
docs: add mike
2024-10-06 10:52:23 -06:00
19342c4735
ci: add codecov.yml
2024-09-10 17:33:55 -06:00
236305729e
ci: invoke codecov via Python, not from command line
2024-09-10 15:21:41 -06:00
3fb5bfb4ad
ci: run codecov directly instead of via GitHub Action
2024-09-10 13:45:40 -06:00
354309394d
meta: export JSON during tests for codecov to injest
2024-09-10 10:09:56 -06:00
129f991dda
meta: add codecov
2024-09-10 07:17:50 -06:00
0715788ed7
meta: update description in pyproject.toml
2024-07-18 06:35:37 -07:00
fd65d9a009
meta: increment version to 1.0.1
2024-07-18 06:34:34 -07:00
24b4ca2468
docs: add mention of CSV export from logic analyzer
2024-07-17 19:47:18 -07:00
f687f071dd
cli: enable CSV export from logic analyzer capture
2024-07-17 18:51:05 -07:00
67103ad70e
doc: remove warning about bidirectional mem cores on xilinx platforms
2024-07-17 18:51:05 -07:00
b87f8cbc48
meta: move to lib.io and lib.mem, enable bidirectional mem tests on xilinx
2024-07-17 18:51:05 -07:00
753a3f9427
meta: finish moving simulations to new async API
2024-07-17 18:51:05 -07:00
8fd943257c
sim: update testbenches to async API
2024-07-17 18:51:05 -07:00
13bc196a34
rename Nexys A7 to Nexys 4 DDR
2024-05-12 10:35:18 -07:00
978937e4bc
modify example design naming convention
2024-05-12 10:25:00 -07:00
6c25f6e8d3
add sponsor button
2024-05-11 11:52:35 -06:00
7957e5d74e
doc: change WaveDrom render branch to main
2024-04-14 16:11:46 -06:00
f6127791c7
doc: add inline CSS to fix WaveDrom renders in dark mode
2024-04-14 16:11:46 -06:00
b35bfa1152
doc: fix typo and migrate read timing diagram
2024-04-14 16:11:46 -06:00
697d6a00d9
doc: directly render read transaction timing diagram
2024-04-14 16:11:46 -06:00
8da5b27010
Merge pull request #17 from KennethWilke/main
...
add warning about reset polarity in Manta instance
2024-04-06 00:50:19 -06:00
7a44f34ae3
tweak wording of active low reset warning
2024-04-05 23:46:54 -07:00
af0dec7d76
Updated reset note and a doc link
2024-04-05 19:03:01 -05:00
ccc75270a8
Update getting_started.md
...
I was working through using Manta for the first time, and the only bit that gave me a struggle so far was that I was expecting the `rst` signal to be active LOW. I thought this might be worth calling out in the documentation here.
Awesome project btw, will definitely be using it more and try to contribute as I can! 😄
2024-03-31 23:17:03 -05:00
5060933c72
bump node version in build_docs.yml
2024-03-14 20:58:28 -07:00
1a7adf4c63
add udev rule to docs
2024-03-14 10:28:37 -07:00
8efbad4dd8
Merge pull request #16 from fischermoseley/amaranth_rewrite
...
Rewrite Manta in Amaranth HDL
2024-03-07 13:31:59 -07:00
e0aeb38cdb
update docs
2024-03-07 12:25:30 -08:00
355b5d8c76
merge origin/main into amaranth_rewrite
2024-03-07 09:59:17 -08:00
e094865528
bump pyproject version ahead of final release
2024-03-07 09:44:05 -08:00
6251c162cc
update to node 20-based checkout in CI
2024-03-07 09:35:47 -08:00
c8665e8703
update environment on CI runner
2024-03-07 09:33:50 -08:00
4ae061ffdc
add missing .gitignore
2024-03-07 09:21:40 -08:00
05f9da383c
banish all .Xil/ folders
2024-03-07 09:19:11 -08:00
04cfa41190
add logic analyzer/io core ethernet example
2024-03-07 09:18:30 -08:00
7957d41a99
fix consistency in .gitignore
2024-03-06 23:09:37 -08:00
60066ccdca
add examples for the Nexys4DDR, bump version to 1.0.0
2024-03-06 23:07:20 -08:00
05b9b450e8
add logic analyzer icestick example
2024-03-06 22:05:24 -08:00
21afbad7c4
add icestick IO core example
2024-03-06 21:47:03 -08:00
bd452d94a4
put test outputs in build/
2024-03-06 16:40:54 -08:00
6900087237
delete dead code from memory core
2024-03-06 15:08:11 -08:00
71ec1174d1
add parameterized HW tests for all memory core modes
2024-03-06 14:53:27 -08:00
0b2c286075
pull latest from main
2024-03-06 11:31:35 -08:00
d1a772784a
add environment.sh for tool paths and serial ports
2024-03-06 11:26:31 -08:00
5d5a50042f
make model tracking automatic in memory core tests
2024-03-06 01:12:36 -08:00
c1935bcb11
add random memory core tests
2024-03-05 23:59:42 -08:00
fd22c9a9f4
finish memory core test class
2024-03-05 22:44:36 -08:00
b00e4d0e60
revert wiring.Component instead of Elaboratable
2024-03-04 01:18:31 -08:00
Fischer Moseley
Kenneth Wilke