upate image names

README.md

@@ -1,10 +1,11 @@
-![](doc/assets/manta.png)
+![](doc/assets/logo.png)
 
 ## Manta: An In-Situ Debugging Tool for Programmable Hardware
 ![functional_simulation](https://github.com/fischermoseley/manta/actions/workflows/functional_simulation.yml/badge.svg)
 ![formal_verification](https://github.com/fischermoseley/manta/actions/workflows/formal_verification.yml/badge.svg)
 ![build_examples](https://github.com/fischermoseley/manta/actions/workflows/build_examples.yml/badge.svg)
 ![build_docs](https://github.com/fischermoseley/manta/actions/workflows/build_docs.yml/badge.svg)
+
 [![License: GPL v3](https://img.shields.io/badge/License-GPLv3-blue.svg)](https://www.gnu.org/licenses/gpl-3.0)
 [![Code style: black](https://img.shields.io/badge/code%20style-black-000000.svg)](https://github.com/psf/black)
 

doc/index.md

@@ -1,4 +1,4 @@
-![](assets/manta.png)
+![](assets/logo.png)
 
 ## Manta: An In-Situ Debugging Tool for Programmable Hardware
 

doc/io_core.md

@@ -97,7 +97,7 @@ While the IO core performs a very, very simple task, it carries a few caveats.
 
 This is done with the architecture shown below:
 
-![](assets/io_core_block_diagram.png){:style="width:49%"}
+![](assets/io_core_architecture.png){:style="width:49%"}
 
 Each of the probes is mapped to a register of Manta's internal memory. Since Manta's internal registers are 16 bits wide, probes less than 16 bits are mapped to a single register, but probes wider than 16 bits require multiple.
 

doc/logic_analyzer_core.md

@@ -139,7 +139,7 @@ At present, this class contains methods used really only for capturing data, and
 ## How It Works
 The Logic Analyzer Core's implementation on the FPGA consists of three primary components:
 
-![](assets/manta_logic_analyzer_architecture.png){style="width:85%"}
+![](assets/logic_analyzer_architecture.png){style="width:85%"}
 
 - The _Finite State Machine (FSM)_, which controls the operation of the core. The FSM's operation is driven by its associated registers, which are placed in a separate module. This permits simple CDC between the bus and user clock domains.
 - The _Trigger Block_, which generates the core's trigger condition. The trigger block contains a trigger for each input probe, and the registers necessary to configure them. It also contains the $N$-logic gate (either AND or OR) that generates the core's trigger from the individual probe triggers. CDC is performed in exactly the same manner as the FSM. If an external trigger is specified, the trigger block is omitted from the Logic Analyzer Core, and the external trigger is routed to the FSM's `trig` input.

mkdocs.yml

@@ -8,8 +8,8 @@ docs_dir: 'doc'
 
 theme:
   name: material
-  logo: assets/manta_minimal_border.png
-  favicon: assets/manta_with_shadow.png
+  logo: assets/logo_minimal_border.png
+  favicon: assets/logo_ray_only_with_shadow.png
   features:
     - content.code.copy
     - content.code.annotate