doc: fix typo and migrate read timing diagram

doc/architecture.md

@@ -28,9 +28,8 @@ The data bus is designed for simplicity, and consists of five signals used to pe
 
 Each core has a bus input and output port, so that cores can be daisy-chained together. When it receives an incoming bus transaction (signalled by `valid`), the core checks the address on the wire against its own memory space. If the address lies within the core, the core will perform the requested operation against its own memory space. In the case of a read, it places the data at that address on `data`, and in the case of a write, it copies the value of `data` to the specified location in memory. However, if the address lies outside of the memory of the core, then no operations are performed.
 
-![](assets/read_transaction.png){:style="width:49%"}
-
-![Write Transaction](https://svg.wavedrom.com/github/fmoseley/manta/render_wavedrom_directly/doc/assets/write_transaction.json5){:style="width:49%"}
+![Read Transaction](https://svg.wavedrom.com/github/fischermoseley/manta/render_wavedrom_directly/doc/assets/read_transaction.json5){:style="width:49%"}
+![Write Transaction](https://svg.wavedrom.com/github/fischermoseley/manta/render_wavedrom_directly/doc/assets/write_transaction.json5){:style="width:49%"}
 
 ## Message Format
 

doc/assets/read_transaction.json5

@@ -0,0 +1,26 @@
+{
+  signal: [
+    {name: 'clk', wave: 'p...|....'},
+    {},
+    ['input port',
+      {name: 'addr',  wave: 'x3x.|....', data: ['A0']},
+      {name: 'data',  wave: 'xxx.|....', data: ["D0"]},
+      {name: 'rw',    wave: 'x0x.|....'},
+      {name: 'valid', wave: '010.|....'},
+    ],
+
+     {}, {},
+
+    ['output port',
+      {name: 'addr',  wave: 'x...|.3x.', data: ['A0']},
+      {name: 'data',  wave: 'x...|.8x.', data: ['D0']},
+      {name: 'rw',    wave: 'x...|.0x.'},
+      {name: 'valid', wave: '0...|.10.'},
+    ],
+
+     {}, {},
+
+  ],
+  head: {text: 'Read Transaction'},
+  config: {hscale: 1}
+}