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convert diagrams to .drawio.svg format

This commit is contained in:
Fischer Moseley 2024-01-05 23:01:57 -08:00
parent 03a3ec6c9f
commit 89f1dcde1c
20 changed files with 3886 additions and 7 deletions
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doc/assets/block_memory_architecture.png
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...
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doc/how_it_works.md
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@ -2,7 +2,7 @@
The whole system looks like the following:
![](assets/manta_architecture.png){:style="width:80%"}
![](assets/architecture.drawio.svg){:style="width:80%"}
Manta is operated via its Python API, which communicates with the connected FPGA over an interface API like `pySerial` or `Scapy`. These abstract away the OS device drivers, which function differently depending on the host machine's platform. The OS device drivers ultimately send out bytes to the FPGA, across either a USB or Ethernet cable.
@ -12,7 +12,7 @@ Once sent across the wire, bytes are picked up by an interface transciever on th
The logic Manta places on the FPGA consists of a series of cores connected in a chain along a common bus. Each core provides a unique method for interacting with the user’s logic, which it connects to by routing signals (called _probes_) between the user’s logic and the cores that interface with it.
![](assets/bus_architecture.png){:style="width:40%"}
![](assets/bus_architecture.drawio.svg){:style="width:40%"}
These probes are presented as addressable memory, and are be controlled by reading and writing to their corresponing memory - not unlike registers on a microcontroller. Each core is allotted a section of address space at compile time, and operations addressed to a core’s address space control the behavior of the core. These cores are then daisy-chained along an internal bus, which permits a chain arbitrarily many cores to be placed on the bus.
@ -37,7 +37,7 @@ Each core has a bus input and output port, so that cores can be daisy-chained to
Ethernet and UART both allow a stream of bytes to be sent between the host and FPGA, but since they're just interfaces, they don't define how these bytes are structured. As a result, Manta implements its own messaging format, with the following structure:
![](assets/uart.png){:style="width:85%"}
![](assets/uart_packets.drawio.svg){:style="width:85%"}
Each of these messages is a string of ASCII characters consisting of a preamble, optional address and data fields, and an End of Line (EOL). The preamble denotes the type of operation, _R_ for a read and _W_ for a write. The address and data fields are encoded as hexadecimal digits, represented with the characters 0-9 and A-F in ASCII. As a result, four characters are needed to encode a 16-bit address or 16-bits of data. If the message specifies a write request, then it will contain a data field after the address field. Both request types will conclude with an End of Line, which consists of the two ASCII characters indicating a Carriage Return (CR) and a Line Feed (LF).

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doc/io_core.md
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@ -90,7 +90,7 @@ While the IO core performs a very, very simple task, it carries a few caveats.
This is done with the architecture shown below:
![](assets/io_core_architecture.png){:style="width:49%"}
![](assets/io_core_architecture.drawio.svg){:style="width:49%"}
Each of the probes is mapped to a register of Manta's internal memory. Since Manta's internal registers are 16 bits wide, probes less than 16 bits are mapped to a single register, but probes wider than 16 bits require multiple.

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@ -139,7 +139,7 @@ At present, this class contains methods used really only for capturing data, and
## How It Works
The Logic Analyzer Core's implementation on the FPGA consists of three primary components:
![](assets/logic_analyzer_architecture.png){style="width:85%"}
![](assets/logic_analyzer_architecture.drawio.svg){style="width:85%"}
- The _Finite State Machine (FSM)_, which controls the operation of the core. The FSM's operation is driven by its associated registers, which are placed in a separate module. This permits simple CDC between the bus and user clock domains.
- The _Trigger Block_, which generates the core's trigger condition. The trigger block contains a trigger for each input probe, and the registers necessary to configure them. It also contains the $N$-logic gate (either AND or OR) that generates the core's trigger from the individual probe triggers. CDC is performed in exactly the same manner as the FSM. If an external trigger is specified, the trigger block is omitted from the Logic Analyzer Core, and the external trigger is routed to the FSM's `trig` input.

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@ -68,7 +68,7 @@ A Block Memory core is used in the [video_sprite](https://github.com/fischermose
Each Block Memory core is actually a set of 16-bit wide BRAMs with their ports concatenated together, with any spare bits masked off. Here's a diagram:
![](assets/block_memory_architecture.png)
![](assets/memory_architecture.drawio.svg)
This has one major consequence: if the core doesn't have a width that's an exact multiple of 16, synthesis engines (Vivado in particular) will throw some warnings as they optimize out the unused bits. This is expected behavior, and while the warnings are a little annoying, not having to manually deal with the unused bits simplifies the implementation immensely. No Python is needed to generate the core, and it'll configure itself just based on Verilog parameters. This turns the block memory core from a complicated conditionally-instantiated beast to a simple ~_100 line_ [Verilog file](https://github.com/fischermoseley/manta/blob/main/src/manta/block_memory.v).

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mkdocs.yml
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@ -61,7 +61,7 @@ nav:
- Getting Started: getting_started.md
- IO Core: io_core.md
- Logic Analyzer Core: logic_analyzer_core.md
- Block Memory Core: block_memory_core.md
- Memory Core: memory_core.md
- UART Interace: uart_interface.md
- Ethernet Interface: ethernet_interface.md
- For Developers: