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905 Commits

Author SHA1 Message Date
Matthias Koefferlein ac479c30bc Fixed unit tests. 2019-10-24 00:23:03 +02:00
Matthias Koefferlein 3a8d5d9779 Removed debug code. 2019-10-23 23:49:38 +02:00
Matthias Koefferlein 4ce37160d5 Two bug fixes in net compare (tests required): 
- name compare of net names wasn't always case insensitive
- tentative evaluation was sometimes continued even after
  a contradiction was detected because the return codes
  of different edge examinations were not combined correctly.
 2019-10-23 23:46:25 +02:00
Matthias Koefferlein 36ee1efe16 WIP: speedup LVS 'align' by flattening top-down 2019-10-21 22:14:36 +02:00
Matthias Koefferlein f0635589f7 WIP: fixed cell cluster interaction cache. 2019-10-20 23:27:15 +02:00
Matthias Koefferlein a0544e7807 WIP: caching of cell interactions in net cluster builder for speedup - test data needs update! 2019-10-19 21:44:29 +02:00
Matthias Koefferlein bf18000877 Added tests (breakout cells, LVS cheats) 2019-10-18 00:25:51 +02:00
Matthias Koefferlein 611f62e73f Removed debug leftover code 2019-10-17 22:47:43 +02:00
Matthias Koefferlein cd4516393b WIP: bugfix (breakout cell handling) and performance 
1.) Bugfix: breakout cells also need to be handled
    when diving down inside the hier cluster builder
2.) Performance: cache cell interactions
 2019-10-17 01:54:41 +02:00
Matthias Koefferlein 991778f718 "breakout cells": attempt to provide a solution for SRAM 
Breakout cells can be specified to shortcut hierarchy
evaluation for some cells. This allows treating SRAM cells
as isolated entities - specifically when it comes to extracting
devices.
 2019-10-16 00:49:41 +02:00
Matthias Koefferlein f8476bdf26 Fixed an issue with 'align' in LVS scripts - with multiple layout cells assigned to one schematic, align won't give the right results. 2019-10-05 09:30:38 +02:00
Matthias Koefferlein 2325e1bce4 Merge branch 'dvb' into pull_feature 2019-10-04 22:58:52 +02:00
Matthias Koefferlein ef56264f64 Fixed a regular arrays issue with begin_touching 
In case of 1d arrays with a or b == (0,0), the iterator
was always delivering all items, not just the touching ones.
 2019-10-04 22:45:23 +02:00
Matthias Koefferlein 2fa7c4b6d4 Partially enabled progress for hierarchical processor. 2019-10-04 01:48:45 +02:00
Matthias Koefferlein 212bd86aab Thread safetiness: enable multiple threads for deep region operations 2019-10-04 01:39:16 +02:00
Matthias Koefferlein 7c5ae471ab WIP: performance improvement of hier local processor 
The solution is to take intruder instances from as
far as possible in the hierarchy. This provides a
performance improvement in some cases, specifically
if this leads to compression of contexts.
 2019-10-03 22:53:38 +02:00
Matthias Koefferlein 5ed41cc345 Merge branch 'master' into pull_feature 2019-10-03 14:32:25 +02:00
Matthias Koefferlein e1d77a1476 pull_interacting for edges/edges and edges/regions, some enhancements and bug fixes 
Bug fixes:
- use dist 1 to cover touching case properly in local processor
- handling of raw mode and is_merged state

Additional tests
 2019-10-03 13:08:37 +02:00
Matthias Koefferlein 76b8bd3279 Fixed several issues with raw mode/merged semantics and many Region and Edges methods. Added edge/edge pull and edge/polygon pull. 2019-10-03 01:46:49 +02:00
Matthias Koefferlein 77c8ff50ed WIP: don't fallback to flat in case of non-deep other arguments in select_interacting and pull. 2019-10-02 00:12:04 +02:00
Matthias Koefferlein a1e87d4c14 First pull* implementation functional. 2019-10-01 23:53:05 +02:00
Matthias Koefferlein 74880a5198 First implementation of pull* methods 2019-10-01 22:06:16 +02:00
Matthias Koefferlein 0bc2321ade Some code cleanup. 2019-09-30 23:17:42 +02:00
Matthias Koefferlein a3cecb2ebe WIP: enable multiple layout versions of one schematic circuit using 'same_circuit' 2019-09-30 23:08:15 +02:00
Matthias Koefferlein bdf5e3c124 WIP: fake pin debug issue with LVS 
Fake pins: pins that happen because something connects to a cell at an
unexpected position. Such a pin is difficult to find. The solution is
to keep those nets and nur purge them so these nets can be identified
in the layout.

Here: is_floating? will be true only if there are no pins. Hence
nets with pins are not removed. is_passive is introduced for nets -
passive nets are such that don't have elements, but a pin.
Circuits are purged if they only have passive nets.
 2019-09-30 21:58:13 +02:00
Matthias Koefferlein 506cfc1c6f WIP: attempt to retain nets which don't have active elements but pins. This is supposed to simplify debugging in case of fake pins. When removing those nets, the pin is very difficult to find. 2019-09-30 20:58:55 +02:00
Matthias Koefferlein d69c60a5c5 Enabled net tracing for heavily decomposed polygons 2019-09-19 00:13:14 +02:00
Matthias Koefferlein 6c52daa3a3 Follow-up on #353 (sessions paths relative to session file) 
Consistent behavior for file paths for images too.
Plus: image paths are not kept as absolute paths
inside the session.
This makes regeneration of images stable.
 2019-09-18 22:05:37 +02:00
Matthias Koefferlein 56084b6b59 Merge branch 'dvb' 2019-09-08 20:07:16 +02:00
Matthias Koefferlein e2cc0c48b1 Provide flat and hierarchical 'trace all nets' feature, added Netlist#flatten. 2019-09-06 23:13:21 +02:00
Matthias Koefferlein fa72885020 issue #317: provide undo combination for the paste+move sequence in 'interactive paste'. Same for 'interactive dup' 2019-09-04 23:47:05 +02:00
Matthias Koefferlein 5cfadad54f Updated test data. 2019-08-30 11:01:00 +02:00
Matthias Koefferlein 2a8f4c9610 Updated test data. 2019-08-30 10:52:51 +02:00
Matthias Koefferlein 550e2622bf Put more amphasis on net names to resolve ambiguities 
The problem was that with the floating test case, the
ambiguity resolution sometimes assigned the wrong pins
and floating pins/connected pins were swapped.

One option is to make the ambiguity resolver consider
the pin connection state when tenatively evaluating
nodes.

Another option is to put more emphasis on net names
and use them for ambiguity resolution. This has helped
here.
 2019-08-30 10:24:55 +02:00
Matthias Koefferlein 60ed0cdc89 Updated test golden data (mainly: nets are not purged when there is a subcircuit pin on it) 2019-08-29 23:26:03 +02:00
Matthias Koefferlein b1acfe9587 Tried a better deal with floating pins 
1.) is_floating is now only true if there is no device
    and no subcircuit on a net. This means we only purge
    nets if they are really floating. So far we purged
    nets without pins which lead to the mismatch:

    Before purge:
      Layout:            (net) <--> DEVICE.TERMINAL
      Schematic:           PIN <--> DEVICE.TERMINAL

    After purge:
      Layout:           (null) <--> DEVICE.TERMINAL
      Schematic:           PIN <--> DEVICE.TERMINAL

    (null does not match any net)

2.) circuit pin matching was a bit picky. Only when
    one circuit did not have pins, matching was sloppy.

    In real cases however, circuits may have unconnected
    pins:
    - top level pins without a counterpart (no label)
    - subcircuits pins which are not used

    We catch both cases by refining the match: if a pin
    is not used, it does not need to match against
    any other pin. It's reported as "matching against null"
    though.
 2019-08-29 22:25:59 +02:00
Matthias Koefferlein 9a69d106fd Fixed some small issues in the netlist compare 2019-08-29 00:19:24 +02:00
Matthias Koefferlein 3a12714593 Fixed some doc issues, added doc for hierarchical compare. 2019-08-26 18:55:35 +02:00
Matthias Koefferlein 444e10d32f WIP: rerun LVS, partial LVS 
Rerun LVS: a button is provided which allows re-running
the LVS or netlist extraction from the netlist browser.
TODO: a generic concept for triggering the generators

"Partial LVS" is a feature where it's possible to
select a layout subcell - running LVS then will only
compare against the corresponding schematic subcell, not
the whole tree. The magic is done by "align" which will
remove the upper hierarchy part.
 2019-08-24 22:56:20 +02:00
Matthias Koefferlein a9a2cb69c8 Avoiding one assertion by not considering floating device terminals 2019-08-24 09:58:08 +02:00
Matthias Koefferlein 3ae848bff4 Provide test case for spice reader with delegate for devices as subcircuits. Small bugfix in spice reader: wrong line number in warning. 2019-08-23 23:13:04 +02:00
Matthias Koefferlein b0aa9b6540 Spice reader test compatible with Windows (three-digit exponential) 2019-08-21 23:03:24 +02:00
Matthias Koefferlein 45cdefcf9a Provide strict mode for device classes, dmos3/dmos4 for LVS 2019-08-20 23:12:17 +02:00
Matthias Koefferlein b7c83eaaa6 Spice reader: subcircuits w/o pins 
This happens for subcircuits which only
connect to global nets.

Plus: ".global" now accepts more than just one net
 2019-08-19 23:00:24 +02:00
Matthias Koefferlein 1bc03c3b79 Implement "M" parameter for Spice 
This implementation is pretty simplistic and
applies "M" the following way:
* R: R(final) = R/M
* L: L(final) = L/M
* C: C(final) = C*M
* M: W(final) = W*M
* D: A(final) = A*M
* Q: AE(final) = AE*M

The other parameters (specifically the other
geometry parameters) are not scaled yet.
 2019-08-19 22:51:22 +02:00
Matthias Koefferlein 24b985f32e Better .include for Spice reader 
* .inc is allowed as synonym
* Paths can be URL's (with HTTP)
* Relative resolution of paths/URL's vs. parent of .include
 2019-08-19 21:45:40 +02:00
Matthias Koefferlein 9fecc4b674 Merge branch 'dvb' 2019-08-19 21:06:37 +02:00
Matthias Köfferlein 15f45fb09d
Merge pull request #327 from KLayout/query-performance-fix 
Fix for layout query performance improvement: needs to check for qual…
 2019-08-19 19:37:15 +02:00
Matthias Koefferlein fe4396d872 Merge branch 'issue-306' 2019-08-19 00:03:39 +02:00
Matthias Koefferlein e9eed3842b Fix for layout query performance improvement: needs to check for qualified cell name (with lib), not pure cellname 2019-08-18 19:09:07 +02:00
Matthias Köfferlein c75a1bc2eb
Merge pull request #313 from KLayout/query-performance 
Query performance
 2019-08-18 17:31:17 +02:00
Matthias Köfferlein 16ae0346b8
Merge pull request #314 from KLayout/vars-for-queries 
Vars for queries
 2019-08-18 17:31:11 +02:00
Matthias Köfferlein bf41da69da
Merge pull request #315 from KLayout/lib-browser 
Lib browser
 2019-08-18 17:31:02 +02:00
Matthias Koefferlein 8981ed434a First fix for issue-306: some polygons are not recognized as rounded, more robust radius extraction. 2019-08-17 23:55:49 +02:00
Matthias Koefferlein aa72d03526 Fixed issue #322 by skipping used layer indexes - will also help with DXF and other named-layer formats 2019-08-17 15:30:47 +02:00
Matthias Koefferlein 7c0dd07d42 WIP: lib browser - cleanup and small bug fixes. 2019-08-04 00:49:08 +02:00
Matthias Koefferlein a104352a93 WIP: library browser - cleanup of unused cells in lib browser, some bug fixed, enhancements to parameter editor on drop 2019-08-04 00:08:39 +02:00
Matthias Koefferlein fda5d86b4b Performance enhancement of netlist compare (avoid O(2) loop) 2019-08-02 01:39:07 +02:00
Matthias Koefferlein 4428ef808b WIP: library browser - PCell variants as children of PCells 2019-08-01 22:52:20 +02:00
Matthias Koefferlein 0c18171e63 WIP: library browser - basic setup. Not much functionality yet. 2019-07-31 23:46:48 +02:00
Matthias Koefferlein dfd713016b Added some unit tests for performance improvement of queries. 2019-07-29 22:36:39 +02:00
Matthias Koefferlein 0dcfeabaf4 Query performance improvement for the cell tree recursion case by introducing optimization hints ('filter state objectives') 2019-07-29 22:27:36 +02:00
Matthias Koefferlein e329f60257 WIP: attempt to improve performance by using name match shortcuts 2019-07-28 19:05:25 +02:00
Matthias Koefferlein 49c1bacb98 Introducing variables for layout queries: 
1.) The ExpressionContext class is a mapping of tl::Eval
    and allows providing a variable context for the LQ.
    Expression class is derived from ExpressionContext now.
2.) The variable lookup has been changed so that variables
    can be modified even if they come from a parent context.
3.) LayoutQuery and iterator has been given an argument to
    supply the context
 2019-07-28 01:33:30 +02:00
Matthias Koefferlein 71f646c24f WIP: updated test data for latest updates, don't sort LVSDB on reading for consistency 2019-07-27 21:42:51 +02:00
Matthias Koefferlein 169cc5246d WIP: updated golden data for new device sorting in cross reference. 2019-07-27 20:37:41 +02:00
Matthias Koefferlein 2993a6411a WIP: some enhancements to cross reference and browser 
Devices: try to pair unmatching ones similar to subcircuits
Don't sort devices by the device name but by class name
Show the device parameters for netlist devices (same as
for netlist browser)
 2019-07-27 20:21:13 +02:00
Matthias Koefferlein b4fa4b1bae Flattening of layout with circuit flattening. 
Technically, the layout isn't flattened, but connections are made
which allow regenerating the layout even after the circuit
has been flattened.
 2019-07-27 00:37:22 +02:00
Matthias Koefferlein 9cad9ca024 Fixed missing initialization of device_scaling in LayoutToNetlist. 2019-07-24 20:49:56 +02:00
Matthias Koefferlein afb5cea576 Added "device_scaling" to LVS 
Plus: added some missing files

Implementation details:
* scaling factor was introduced in DeviceExtractor::extract
* for easy implementation this is available in "sdbu"
* "sdbu" is made available in GSI
* to test this, the db::compare_netlist had to be enhanced to
  exactly check device parameters
* enhancement of LVS script framework and doc updates
 2019-07-24 00:16:47 +02:00
Matthias Koefferlein aff8212f2f Provide 'align' method to auto-align circuit and cell hierarchy in LVS 2019-07-23 00:14:43 +02:00
Matthias Koefferlein 14d9689498 Added .global to Spice reader. 2019-07-22 23:02:31 +02:00
Matthias Koefferlein 9d250d6df9 Using a larger branch complexity than default for LVS full test's netlist compare 
In addition: typo fixed, added doc for complexity configuration
parameters.
 2019-07-21 22:24:07 +02:00
Matthias Köfferlein 4e1736a181 Updated golden data of two tests for Windows. 2019-07-16 01:27:08 +02:00
Matthias Köfferlein b3e9915259 Provide special LVS test golden data for Windows (slight differences in shape order etc.) 2019-07-16 00:40:43 +02:00
Matthias Köfferlein df23830a1c Fixed a runtime issue on Windows 2019-07-16 00:39:39 +02:00
Matthias Köfferlein 9820e57031 Don't write third terminal for R or C (WithBulk variants) 2019-07-15 23:19:03 +02:00
Matthias Köfferlein eb9ffb4a35 Another msvc2017 build warning fixed 2019-07-15 23:18:20 +02:00
Matthias Köfferlein 9a371b8fd2 Fixed some build warnings with msvc2017 (maybe real issues and memory leaks) 2019-07-15 23:17:24 +02:00
matthias 89ce2be5c2 Merge remote-tracking branch 'origin/master' into dvb 2019-07-14 01:28:11 +02:00
Matthias Köfferlein 397e86f4b4 Merge branch 'dvb' of https://github.com/klayout/klayout into dvb 2019-07-13 23:39:16 +02:00
Matthias Köfferlein 4172b60d60 Fixed a build issue on Windows. 2019-07-13 23:38:26 +02:00
matthias 8b17a4da4f A few utility functions 
Polygon#is_rectilinear?, Polygon#is_empty?
and same for SimplePolygon
 2019-07-13 22:45:22 +02:00
Matthias Koefferlein 1251fb2cd6 Added < and > to allowed chars for net names in Spice reader 2019-07-13 08:50:13 +02:00
Matthias Koefferlein e8ff8156a0 fix for #264 
1. Errors in coerce_parameters are now shown as
   red label + warning icon in the parameters dialog
2. Errors during produce are always logged now

Plus: the scroll bars of the PCell parameters page
don't jump back on "Apply".
 2019-07-12 21:13:18 +02:00
Matthias Koefferlein c7e883cdb2 SPICE reader now assigned net names as pin names. 2019-07-12 19:00:27 +02:00
Matthias Koefferlein f66b094e88 Merge branch 'dvb' into dvb_test 2019-07-12 17:44:11 +02:00
Matthias Koefferlein d109a22cf5 Renaming (distro nodes->virtual nodes) 2019-07-11 23:20:42 +02:00
Matthias Koefferlein e32ee570c7 Alternative algorithm for subcircuit matching - tests updated, refactoring 2019-07-11 23:19:02 +02:00
Matthias Koefferlein 7bc4acd8f6 WIP: new version of subcircuit match algorithm - needs refactoring. 2019-07-11 23:14:53 +02:00
Matthias Koefferlein 0d9273aaf6 WIP: new subcircuit match algorithm 2019-07-11 00:16:36 +02:00
Matthias Koefferlein 2f01c7a0bd WIP: other algorithm for handling subcircuits in netlist compare 2019-07-10 23:40:16 +02:00
Matthias Koefferlein 67f786035c WIP: during refactoring 2019-07-10 00:32:53 +02:00
Matthias Koefferlein cef96902ad Boundary for circuits, reverted automatic generation of global pins 
- global pins have been generated for device cells too and lead
  to implicit pins which may not be desired. The original problem
  was how to make abstract circuits comparable. This has to be
  solved differently.
- Circuit boundaries are good for displaying the boxes for
  abstract circuits
 2019-07-09 19:55:48 +02:00
Matthias Koefferlein 0c6ead6f90 WIP: introduced boundary into L2N format so we have something to display for abstracts. 2019-07-09 01:18:23 +02:00
Matthias Koefferlein c9e08c4500 WIP: propagate global nets to parent hierarchy even if there is no shape inside the cell. 2019-07-08 23:11:35 +02:00
Matthias Koefferlein bdb8a7bcc2 WIP: reverted modifications on SPICE reader. 2019-07-08 21:51:59 +02:00
Matthias Koefferlein 9625caea65 WIP: added full LVS test. 2019-07-08 21:43:06 +02:00
Matthias Koefferlein b48453633f WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
Matthias Koefferlein 993ef78575 WIP: some cleanup/enhancement 
General topic: abstracts and swappable pins.
Issue: we work bottom up and assign pins. This is the
basis for net graph building. But swappable means those
pins can change. The compare works fine, but debugging
output is strange: as the pin assigned is fixed, the nets
found to be attached to a circuit might not fit any
proposed pin pair (which does not contain swapping).

The problem gets worse with abstracts.

The enhancements are
- Such cases generate only warnings in the browser
  and the message says swapping might be the case
- Floating nets are treated differently. This should
  lead to a better performance for abstracts/black boxes,
  but in case of disconnected pins (due to wire errors),
  floating nets happen to create mismatches in the nets above.
- Net graph building does not consider swappable nets. In
  case of two swappable pins this wouldn't be an issue, but
  for more than two this would create ambiguities and
  prevent topological matching.

Plus: Debug output option for net graph

Tests updated
 2019-07-07 18:17:14 +02:00
Matthias Koefferlein ace0788f85 WIP: Spice reader reads pin names from nets 2019-07-07 00:05:22 +02:00
Matthias Koefferlein 0e5ecdc36b Attempt to make LVS compare output a little more predictable with boundary cases 
- For unattached subcircuit pins no error should be reported
- For abstract nets, graph propagation through subcircuit pins isn't attempted.
  Abstract nets are only dummy-associated currently.
 2019-07-06 23:40:49 +02:00
Matthias Koefferlein 903b1f7505 WIP: fixed 'equivalent_pins' 2019-07-06 21:47:25 +02:00
Matthias Koefferlein 5ce8dd2684 WIP: added circuit blankout. 2019-07-06 19:50:20 +02:00
Matthias Koefferlein 71777670de Fixed unit tests. 2019-07-04 01:24:19 +02:00
Matthias Koefferlein 5e70f4fa03 Fixed an edit bug. 2019-07-04 01:18:25 +02:00
Matthias Koefferlein 07ae488652 WIP: bugfix - don't uppercase file names in SPICE .include, typos fixed. 2019-07-04 00:57:52 +02:00
Matthias Koefferlein 66a9fa41e7 WIP: added more docs, confine BJT combination to emitter parameters. 2019-07-02 21:09:32 +02:00
Matthias Koefferlein f931b6a1c1 Bugfix: avoid an assertion in the netlist browser 
Reason: when a circuit does not have pins and is top level,
but the reference has pins, the reference pins are regarded
to match against (nil). This case has to be reported properly,
otherwise the model can't be built consistently.
 2019-07-02 00:01:11 +02:00
Matthias Koefferlein ef1441e546 WIP: fixed unit tests. 2019-06-28 17:08:04 +02:00
Matthias Koefferlein 6ed3838baf WIP: fixed an edit failure 2019-06-28 14:43:52 +02:00
Matthias Koefferlein 80d86cc425 WIP: netlist browser - allow switching between L2N and LVSDB view 2019-06-28 11:27:43 +02:00
Matthias Koefferlein 910a36b83d WIP: better matching of subcircuits - attempt to map them even if not identical. This hopefully makes solving subcircuit connection problems easier. 2019-06-28 11:05:43 +02:00
Matthias Koefferlein 3310d34cf3 WIP: better tooltips and comments for LVS browser. 2019-06-27 00:14:18 +02:00
Matthias Koefferlein 955d21a656 WIP: case insensitive compare of netlists (after reading Spice, the names are caseless) 2019-06-26 20:58:42 +02:00
Matthias Koefferlein 0cbfa698f0 WIP: debugging, development 
- LVS DSL debugging, enhancements
- Allow polygons with holes in L2N
- Spice Reader: was creating too many class objects
- Device class categorizer: allow associating A->C,B-C
- ...
 2019-06-26 20:41:49 +02:00
Matthias Koefferlein 37012efba0 WIP: fixed unit tests, bug fix in DeepRegion -> and and not shall return a DeepRegion always. 2019-06-24 20:56:20 +02:00
Matthias Koefferlein 624811d55e WIP: fixed a basic issue with empty layers 
Previous: empty layers occupied a special layer in the DSS
But what when empty layers are required as outputs?
ONE layer isn't good -> would overwrite the layer and it's
no longer empty for others.
So we need to keep the layers separate.
 2019-06-23 23:44:15 +02:00
Matthias Koefferlein 464a1f35fb WIP: enhancements to DRC DSL for net extraction, some bug fixes in L2N browser etc. 2019-06-23 23:23:36 +02:00
Matthias Koefferlein 717e7ca0ab WIP: Fixed Spice reader/writer delegate, tests. 2019-06-23 00:08:49 +02:00
Matthias Koefferlein a1a0b62a10 WIP: doc fixes, added Netlist::simplify as convenience method 2019-06-22 22:18:55 +02:00
Matthias Koefferlein 621c3f74ed WIP: reader delegate - GSI binding, tests. 2019-06-22 22:03:32 +02:00
Matthias Koefferlein 343e340e22 WIP: SPICE reader delegate, unit tests + debugging 2019-06-22 19:44:33 +02:00
Matthias Koefferlein d174fb73fd WIP: preparations for SPICE reader delegate. 2019-06-22 18:37:32 +02:00
Matthias Koefferlein 46dafd50ea WIP: unit tests updated 2019-06-22 10:15:32 +02:00
Matthias Koefferlein 847f60947d WIP: BJT - don't place base and emitter terminals over each other. 2019-06-22 02:19:49 +02:00
Matthias Koefferlein 9647c94c68 WIP: added NE parameter for BJT3/4, AE and NE are primary parameters now. 2019-06-21 23:41:08 +02:00
Matthias Koefferlein 6f6b9e898b WIP: reduced number of warnings with clang 2019-06-21 23:22:42 +02:00
Matthias Koefferlein a4d2be7fbf Merge remote-tracking branch 'origin/master' into dvb 2019-06-19 23:14:27 +02:00
Matthias Köfferlein 2ef403e0ac
Merge pull request #282 from KLayout/issue-281 
Fixed #281 (proper reporting of width/space violations in the kissing…
 2019-06-18 18:44:41 +02:00
Matthias Koefferlein 03bc7e7d9a Fixed non-Qt build. 2019-06-18 01:13:41 +02:00
Matthias Koefferlein 303cda6981 Fixed #277 (min_coherence not recognized by region size) 2019-06-17 21:40:37 +02:00
Matthias Koefferlein 2389d2b391 Fixed #281 (proper reporting of width/space violations in the kissing-corner case) 2019-06-17 20:48:07 +02:00
Matthias Koefferlein 0794290fb5 WIP: added RBA basic tests for device extractors. 2019-06-15 21:48:02 +02:00
Matthias Koefferlein a91c3d3a4e WIP: fixed BJT4 class, added RBA tests for new device classes. 2019-06-15 21:11:15 +02:00
Matthias Koefferlein e939d51104 WIP: BJT4 device, more parameters for resistor (W,L), BJT devices for Spice writer, tests updated 2019-06-15 18:22:04 +02:00
Matthias Koefferlein 1b2a611d83 WIP: diode extraction test. 2019-06-15 09:34:04 +02:00
Matthias Koefferlein c717eb1efa WIP: fixed RBA unit tests. 2019-06-15 00:01:40 +02:00
Matthias Koefferlein 0b5db06ca8 WIP: tests for BJT extraction 2019-06-14 23:45:04 +02:00
Matthias Koefferlein 4212a783a5 WIP: test cases for device extractors R/C with bulk 2019-06-14 21:21:11 +02:00
Matthias Koefferlein 020b874083 WIP: more device classes - unit tests for classes 2019-06-14 20:41:38 +02:00
Matthias Koefferlein a979b669db WIP: new device classes 2019-06-14 19:08:09 +02:00
Matthias Koefferlein 3569ce391c Fixed implementation of duplicate instance removed 2019-06-13 15:52:36 +02:00
Matthias Koefferlein 0d623bc57a Avoid netlist extraction issues with duplicate instances 
So far, duplicate instances have lead to net propagation
into parent cells and floating nets. This is fixed by ignoring
duplicate instances where possible.
 2019-06-13 13:33:28 +02:00
Matthias Koefferlein 8e1dadbe59 Updated golden data of unit tests. 2019-06-13 09:02:47 +02:00
Matthias Koefferlein ebd00c186b Enhancements for net export feature 
- some refactoring
- better performance (was slow because layer iteration
  was done outside of loop and recursive cluster iterator)
- with selected nets, only the required hierarchy is
  produced. For this a new argument is added to
  LayoutToNetlist::create_cell_mapping (nets) which
  allows selecting the nets for which a cell mapping
  is requested
 2019-06-12 22:55:24 +02:00
Matthias Koefferlein a64726e5aa Performance enhancement of netlist model (issue was sorting by expanded name) 2019-06-09 10:05:45 +02:00
Matthias Koefferlein 13f4547789 More progress reporting, performance enhancements 
Main performance enhancement: don't update layouts
between make_layer in DeepRegion
 2019-06-09 09:40:45 +02:00
Matthias Koefferlein 7c220c63e1 Functional netlist hierarchy tree. 2019-06-06 01:36:07 +02:00
Matthias Koefferlein 577edea08b Added tree model for netlist hierarchy browser (LVS/L2N) 2019-06-01 22:38:27 +02:00
Matthias Koefferlein 9c898f536b Merge branch 'dvb' into dvb_enhancements 2019-05-31 23:00:40 +02:00
Matthias Koefferlein 7d6237a90a Unescaping of net names on Spice reader -> writer/reader should be self-compatible. 2019-05-31 22:55:09 +02:00
Matthias Koefferlein 985cffc099 Unique net names for Spice netlist writer 2019-05-31 22:19:51 +02:00
Matthias Koefferlein 9409cfce5c Some more fixes for gcc 4.4.7 :) 2019-05-31 00:36:14 +02:00
Matthias Koefferlein c684633dd6 Some enhancements for netlist extraction and writer 
* Spice writer can now be configure to skip the debug
  comments
* < and > are allowed chars in spice names now
* global net names have second prio over labels now
 2019-05-31 00:11:28 +02:00
Matthias Koefferlein 98207cb454 Another fix for gcc 4.4.7 2019-05-30 23:45:27 +02:00
Matthias Koefferlein e9cc9345f1 Fixed build on gcc 4.4.7 2019-05-30 22:53:27 +02:00
Matthias Koefferlein d4634f8620 Try to establish reproducability of clock tree compare test. 2019-05-30 07:12:49 +02:00
Matthias Koefferlein 9c6ed3e956 Merge remote-tracking branch 'origin/master' into dvb 2019-05-29 22:32:05 +02:00
Matthias Koefferlein 1935ee7ff9 Tried to fix unit tests for MSVC 2019-05-29 22:09:39 +02:00
Matthias Koefferlein dea2b76dc8 Added unit tests for res and cap device extractors. 2019-05-29 21:35:02 +02:00
Matthias Koefferlein 3b3791204d Fixed two more unit tests and renamed new 'define_layer' to 'define_opt_layer' for disambiguation 2019-05-29 01:22:11 +02:00
Matthias Koefferlein 10667d8e35 Bugfixed last commit, fixed unit tests. 2019-05-29 00:51:42 +02:00
Matthias Koefferlein 9d01cb5282 Some updates (res/cap device ex, flatten preserved geometry) 
- Two new device extractors for resistors and caps
  (two-terminal only)
- R and C device classes have A and P parameters now
- A generic concept to supply terminal output layers
  for device extractors (tX).
- Converted offset to transformation for devices:
  this was required to make circuit flattening preserve
  the geometry (transformation of devices)
  L2N/LVSDB formats have been extended for this.
 2019-05-29 00:10:10 +02:00
Matthias Koefferlein 759cc835d9 Added LayoutToNetlist test for pya. 2019-05-27 20:28:48 +02:00
Matthias Koefferlein 7b7e35d3d5 Fixed some compiler warnings. 2019-05-27 18:05:38 +02:00
Matthias Koefferlein 2bf3f3d5c9 Fixed unit tests, bug fixes in netlist DB model. 2019-05-26 18:28:35 +02:00
Matthias Koefferlein eb81a7e5a6 GSI binding of LVS objects. 2019-05-26 09:01:21 +02:00
Matthias Koefferlein 89cbe930ae WIP: GSI binding of LVS framework, tests and debugging 2019-05-26 01:37:45 +02:00
Matthias Koefferlein 14bc72039e WIP: integration of LVSDB into LayoutView (GSI) 2019-05-25 23:22:24 +02:00
Matthias Koefferlein 58b9cfa3c5 WIP: corrected some bugs in the GSI binding of LVS objects. 2019-05-25 22:59:52 +02:00
Matthias Koefferlein 09fe41294b WIP: GSI binding for LayoutVsSchematic and NetlistCrossReference. 2019-05-25 22:33:35 +02:00
Matthias Koefferlein 3269c4cd15 WIP: further debugging of crossref model + tests. 2019-05-23 00:06:37 +02:00
Matthias Koefferlein 57f9efa611 WIP: debugged cross-reference model 2019-05-22 23:47:38 +02:00
Matthias Koefferlein f1fc16d55f WIP: LVS DB model 2019-05-22 00:46:15 +02:00
Matthias Koefferlein 252622e3f8 Fixed unit tests, support floating pins for netlist compare 2019-05-20 23:48:07 +02:00
Matthias Koefferlein 625b173379 Reworked l2n and lvsdb format such that reading/writing gets more reproducible: maintain unnamed state of devices, subcircuits and pins 2019-05-20 22:33:23 +02:00
Matthias Koefferlein 834dcc7474 WIP: LVSDB reader/writer fixes 2019-05-19 23:42:31 +02:00
Matthias Koefferlein ea8320dcf8 WIP: LVSDB reader/writer: bugfixes, refactoring, tests. 2019-05-19 22:55:03 +02:00
Matthias Koefferlein 81e512e1cd WIP: Debugging of LVS DB writer 2019-05-19 10:13:20 +02:00
Matthias Koefferlein b2fee5da3d WIP: LVS DB writer. 2019-05-19 00:34:14 +02:00
Matthias Koefferlein bee662eea8 WIP: refactoring of LVS/L2N DB readers 2019-05-18 22:24:58 +02:00
Matthias Koefferlein c09db62cf6 Supply a base class binding for netlist compare event receivers 2019-05-18 22:24:35 +02:00
Matthias Koefferlein 3a11951175 WIP: LVS DB structure, reader 2019-05-18 21:39:54 +02:00
Matthias Koefferlein d006d0c91e WIP: some refactoring 2019-05-17 21:49:40 +02:00
Matthias Koefferlein 65ea72c569 WIP: netlist cross reference - refactoring of sorting, more robust 2019-05-16 23:26:49 +02:00
Matthias Koefferlein 95caca1dd5 WIP: netlist cross reference - tests and bugfixes 2019-05-16 22:43:28 +02:00
Matthias Koefferlein 924daa65b7 WIP: tests for netlist cross ref. 2019-05-16 00:09:06 +02:00
Matthias Koefferlein 56f6143e4f Added RBA::Technology#clear_technologies 2019-05-10 23:24:04 +02:00
Matthias Koefferlein 6f689863b6 Fixed MSVC build, fixed unit tests. 2019-05-10 21:09:19 +02:00
Matthias Koefferlein 0f0dd42b4d Refactoring and GSI binding for combined device interface. 2019-05-10 18:32:05 +02:00
Matthias Koefferlein 675a96eb9e WIP: some refactoring. 2019-05-10 00:40:49 +02:00
Matthias Koefferlein dda7ee8b60 WIP: a small refactoring. 2019-05-10 00:18:58 +02:00
Matthias Koefferlein ea28530c55 L2N: combined device persistance (complex concept - needs simplification?) 2019-05-10 00:15:51 +02:00
Matthias Koefferlein db1e813635 WIP: combined devices and geometry/L2N DB representation. Yet to do: device cell transformation beyond vector? 2019-05-09 01:07:54 +02:00
Matthias Koefferlein 9a361ee234 WIP: Support for combined devices 2019-05-08 00:14:08 +02:00
Matthias Koefferlein 1dbb25b2e8 Some refactoring (reuse cell context cache) 2019-05-06 01:54:10 +02:00
Matthias Koefferlein 30fdb0089b Integration of netlist extractor with net tracer plugin (-> "trace all nets") 2019-05-05 22:30:07 +02:00
Matthias Koefferlein c33fd40ec9 Switched l2n format to relative mode by default (relative mode is an option and maybe shorter) 2019-05-04 23:06:18 +02:00
Matthias Koefferlein bc26e32a68 WIP: netlist browser 2019-05-04 18:48:57 +02:00