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1628 Commits

Author SHA1 Message Date
Matthias Koefferlein afb5cea576 Added "device_scaling" to LVS 
Plus: added some missing files

Implementation details:
* scaling factor was introduced in DeviceExtractor::extract
* for easy implementation this is available in "sdbu"
* "sdbu" is made available in GSI
* to test this, the db::compare_netlist had to be enhanced to
  exactly check device parameters
* enhancement of LVS script framework and doc updates
 2019-07-24 00:16:47 +02:00
Matthias Koefferlein 5dabd6093d Provide new 'align' feature in LVS for automatic circuit flattening. 2019-07-23 01:12:12 +02:00
Matthias Koefferlein aff8212f2f Provide 'align' method to auto-align circuit and cell hierarchy in LVS 2019-07-23 00:14:43 +02:00
Matthias Koefferlein 14d9689498 Added .global to Spice reader. 2019-07-22 23:02:31 +02:00
Matthias Köfferlein d87c27b4cd
Merge pull request #310 from KLayout/issue_293 
Fixed #293: window title of setup form is 'Setup'
 2019-07-21 23:49:38 +02:00
Matthias Köfferlein 8a66f59b6e
Merge pull request #308 from KLayout/issue-305 
Fixed issue #305 (CIF reader issue with rotated boxes)
 2019-07-21 23:49:11 +02:00
Matthias Köfferlein fbb8a432c4
Merge pull request #307 from KLayout/dvb 
Dvb
 2019-07-21 23:48:55 +02:00
Matthias Koefferlein 39011e3a37 Fixed #293: window title of setup form is 'Setup' 2019-07-21 23:22:10 +02:00
Matthias Koefferlein 8f21cdf449 Fixed issue #305 (CIF reader issue with rotated boxes) 2019-07-21 22:57:02 +02:00
Matthias Koefferlein 9d250d6df9 Using a larger branch complexity than default for LVS full test's netlist compare 
In addition: typo fixed, added doc for complexity configuration
parameters.
 2019-07-21 22:24:07 +02:00
Matthias Koefferlein df7195b81f Compatibility with ruby 1.8, force garbage cleanup for LVS/DRC and tests. 2019-07-21 10:23:08 +02:00
Matthias Koefferlein 6e6e449eef Consolidated test data for lvs:full - there are too many variants to support pure text compare. We use the netlist comparer now. 2019-07-21 09:20:44 +02:00
Matthias Köfferlein f82e7929d8 Fixed a conversion issue with ints on MSVC 
Because long is 32bit on Windows (like int), the
conversion from long to unsigned int was subject
to sign overflow. This was fixed by going to
unsigned int via unsigned long.
 2019-07-20 00:28:32 +02:00
Matthias Koefferlein 0215d05a12 Fixed unit tests. 2019-07-19 00:02:05 +02:00
Matthias Köfferlein 7fc907cf7e Fixed a segfault from the testsuite 2019-07-16 23:17:29 +02:00
Matthias Köfferlein 4e1736a181 Updated golden data of two tests for Windows. 2019-07-16 01:27:08 +02:00
Matthias Köfferlein 630f7e56d8
Merge pull request #303 from KLayout/issue-302 
Fixed #302 and plus a potential invalid memory access fixed
 2019-07-16 00:44:00 +02:00
Matthias Köfferlein b3e9915259 Provide special LVS test golden data for Windows (slight differences in shape order etc.) 2019-07-16 00:40:43 +02:00
Matthias Köfferlein df23830a1c Fixed a runtime issue on Windows 2019-07-16 00:39:39 +02:00
Matthias Köfferlein e4efaac12f MSVC builds fixed - XML source needs to accept URLs (specifically resource URLs) also with EXPAT 2019-07-15 23:23:19 +02:00
Matthias Köfferlein 9820e57031 Don't write third terminal for R or C (WithBulk variants) 2019-07-15 23:19:03 +02:00
Matthias Köfferlein eb9ffb4a35 Another msvc2017 build warning fixed 2019-07-15 23:18:20 +02:00
Matthias Köfferlein 9a371b8fd2 Fixed some build warnings with msvc2017 (maybe real issues and memory leaks) 2019-07-15 23:17:24 +02:00
Matthias Köfferlein 350ae397aa MSVC builds fixed - XML source needs to accept URLs (specifically resource URLs) also with EXPAT 2019-07-15 00:18:18 +02:00
Matthias Köfferlein ede217cd0b Fixed #302 and plus a potential invalid memory access fixed 2019-07-15 00:17:01 +02:00
matthias 89ce2be5c2 Merge remote-tracking branch 'origin/master' into dvb 2019-07-14 01:28:11 +02:00
Matthias Köfferlein 1b08656835
Merge pull request #300 from KLayout/issue-264 
Issue 264
 2019-07-14 00:12:58 +02:00
Matthias Köfferlein 397e86f4b4 Merge branch 'dvb' of https://github.com/klayout/klayout into dvb 2019-07-13 23:39:16 +02:00
Matthias Köfferlein 4172b60d60 Fixed a build issue on Windows. 2019-07-13 23:38:26 +02:00
matthias 8b17a4da4f A few utility functions 
Polygon#is_rectilinear?, Polygon#is_empty?
and same for SimplePolygon
 2019-07-13 22:45:22 +02:00
matthias 5f27341995 Some refactoring, better templates 
1.) tl::Stream now can read from resources
    (:<path> URL's)
2.) LVS/DRC templates are kept as resource,
    "create_template" uses the URL to read them.
3.) Added samples for LVS
4.) Configured LVS to match sample
 2019-07-13 18:40:00 +02:00
matthias ebca5e1ce6 Bugfix: small LVS and DRC macro iessues (LVS and DRC menus not working etc.) 2019-07-13 17:00:05 +02:00
Matthias Koefferlein 1251fb2cd6 Added < and > to allowed chars for net names in Spice reader 2019-07-13 08:50:13 +02:00
Matthias Koefferlein 2d57a11f8c Fixed #287 (RecursiveShapeIterator to ObjectInstPath) 
There is a new constructor for ObjectInstPath to
create one from a RecursiveShapeIterator.
 2019-07-12 23:13:50 +02:00
Matthias Koefferlein e8ff8156a0 fix for #264 
1. Errors in coerce_parameters are now shown as
   red label + warning icon in the parameters dialog
2. Errors during produce are always logged now

Plus: the scroll bars of the PCell parameters page
don't jump back on "Apply".
 2019-07-12 21:13:18 +02:00
Matthias Koefferlein c7e883cdb2 SPICE reader now assigned net names as pin names. 2019-07-12 19:00:27 +02:00
Matthias Koefferlein f66b094e88 Merge branch 'dvb' into dvb_test 2019-07-12 17:44:11 +02:00
Matthias Koefferlein a47190f3ab Write short versions of LVS and L2N DB by default. 2019-07-12 17:43:43 +02:00
Matthias Koefferlein 85717beca6 Allow saving LVS DB files from netlist browser. 2019-07-12 17:29:44 +02:00
Matthias Koefferlein d109a22cf5 Renaming (distro nodes->virtual nodes) 2019-07-11 23:20:42 +02:00
Matthias Koefferlein e32ee570c7 Alternative algorithm for subcircuit matching - tests updated, refactoring 2019-07-11 23:19:02 +02:00
Matthias Koefferlein 7bc4acd8f6 WIP: new version of subcircuit match algorithm - needs refactoring. 2019-07-11 23:14:53 +02:00
Matthias Koefferlein 0d9273aaf6 WIP: new subcircuit match algorithm 2019-07-11 00:16:36 +02:00
Matthias Koefferlein 2f01c7a0bd WIP: other algorithm for handling subcircuits in netlist compare 2019-07-10 23:40:16 +02:00
Matthias Koefferlein 67f786035c WIP: during refactoring 2019-07-10 00:32:53 +02:00
Matthias Koefferlein 1fd069ca99 Provide a better description for net mismatch with warning. 2019-07-09 20:29:35 +02:00
Matthias Koefferlein cef96902ad Boundary for circuits, reverted automatic generation of global pins 
- global pins have been generated for device cells too and lead
  to implicit pins which may not be desired. The original problem
  was how to make abstract circuits comparable. This has to be
  solved differently.
- Circuit boundaries are good for displaying the boxes for
  abstract circuits
 2019-07-09 19:55:48 +02:00
Matthias Koefferlein 0c6ead6f90 WIP: introduced boundary into L2N format so we have something to display for abstracts. 2019-07-09 01:18:23 +02:00
Matthias Koefferlein c9e08c4500 WIP: propagate global nets to parent hierarchy even if there is no shape inside the cell. 2019-07-08 23:11:35 +02:00
Matthias Koefferlein bdb8a7bcc2 WIP: reverted modifications on SPICE reader. 2019-07-08 21:51:59 +02:00
Matthias Koefferlein 9625caea65 WIP: added full LVS test. 2019-07-08 21:43:06 +02:00
Matthias Koefferlein b48453633f WIP: some fixes and small enhancements. New tests. 2019-07-08 00:09:10 +02:00
Matthias Koefferlein bc2d9448d6 Providing LVS tests. 2019-07-07 21:33:28 +02:00
Matthias Koefferlein 95a1e38fe3 WIP: better reproducablility for .lvsdb layer names, updated tests. 2019-07-07 19:39:00 +02:00
Matthias Koefferlein 993ef78575 WIP: some cleanup/enhancement 
General topic: abstracts and swappable pins.
Issue: we work bottom up and assign pins. This is the
basis for net graph building. But swappable means those
pins can change. The compare works fine, but debugging
output is strange: as the pin assigned is fixed, the nets
found to be attached to a circuit might not fit any
proposed pin pair (which does not contain swapping).

The problem gets worse with abstracts.

The enhancements are
- Such cases generate only warnings in the browser
  and the message says swapping might be the case
- Floating nets are treated differently. This should
  lead to a better performance for abstracts/black boxes,
  but in case of disconnected pins (due to wire errors),
  floating nets happen to create mismatches in the nets above.
- Net graph building does not consider swappable nets. In
  case of two swappable pins this wouldn't be an issue, but
  for more than two this would create ambiguities and
  prevent topological matching.

Plus: Debug output option for net graph

Tests updated
 2019-07-07 18:17:14 +02:00
Matthias Koefferlein ace0788f85 WIP: Spice reader reads pin names from nets 2019-07-07 00:05:22 +02:00
Matthias Koefferlein 0e5ecdc36b Attempt to make LVS compare output a little more predictable with boundary cases 
- For unattached subcircuit pins no error should be reported
- For abstract nets, graph propagation through subcircuit pins isn't attempted.
  Abstract nets are only dummy-associated currently.
 2019-07-06 23:40:49 +02:00
Matthias Koefferlein 903b1f7505 WIP: fixed 'equivalent_pins' 2019-07-06 21:47:25 +02:00
Matthias Koefferlein 5ce8dd2684 WIP: added circuit blankout. 2019-07-06 19:50:20 +02:00
Matthias Koefferlein fb8a64b0e1 WIP: updated LVS doc. 2019-07-06 09:37:54 +02:00
Matthias Koefferlein 24a0c3dd00 LVS template for macros. Enhancement: 'schematic' statement can now be anywhere in LVS script. 2019-07-06 09:35:51 +02:00
Matthias Koefferlein a179705a03 WIP: more refactoring. 2019-07-06 09:15:33 +02:00
Matthias Koefferlein 0595ec2e0f WIP: one more test for LVS 2019-07-06 09:08:32 +02:00
Matthias Koefferlein 2f6aae7204 WIP: refactoring, added first tests for LVS 2019-07-06 08:52:40 +02:00
Matthias Koefferlein 15022709b4 WIP: doc update, robustness of LVS browser model (xref) 2019-07-05 23:35:14 +02:00
Matthias Koefferlein a6a0d9946c Updated documentation 2019-07-05 21:45:50 +02:00
Matthias Koefferlein fade779238 WIP: doc update. 2019-07-05 17:48:23 +02:00
Matthias Koefferlein 153bfa9c52 Updated doc. 2019-07-04 23:56:04 +02:00
Matthias Koefferlein 68f98d9f0d Some typos fixed, connect_implicit now can be used multiple times (but without glob pattern) 2019-07-04 23:55:46 +02:00
Matthias Koefferlein 71777670de Fixed unit tests. 2019-07-04 01:24:19 +02:00
Matthias Koefferlein 5e70f4fa03 Fixed an edit bug. 2019-07-04 01:18:25 +02:00
Matthias Koefferlein bd5fbc065a WIP: updated doc. 2019-07-04 01:16:08 +02:00
Matthias Koefferlein 07ae488652 WIP: bugfix - don't uppercase file names in SPICE .include, typos fixed. 2019-07-04 00:57:52 +02:00
Matthias Koefferlein 20c8c6bdaa WIP: more LVS doc. 2019-07-04 00:57:04 +02:00
Matthias Koefferlein 437ead7699 WIP: updated doc. 2019-07-03 01:48:55 +02:00
Matthias Koefferlein 0399b07ff3 WIP: Added sample / xs for vertical BJT 2019-07-03 01:25:26 +02:00
Matthias Koefferlein d913d2352c WIP: doc updated, small typos fixed. 2019-07-03 00:45:11 +02:00
Matthias Koefferlein 66a9fa41e7 WIP: added more docs, confine BJT combination to emitter parameters. 2019-07-02 21:09:32 +02:00
Matthias Koefferlein 8aa6f4edcf WIP: added more test data, doc links 2019-07-02 02:03:58 +02:00
Matthias Koefferlein 87ca28a83f WIP: updated LVS doc. 2019-07-02 01:49:56 +02:00
Matthias Koefferlein 9f26553d4b Added inverter test layout 2019-07-02 00:25:31 +02:00
Matthias Koefferlein 3c4c1b9c4f WIP: bugfixes 
1.) Don't error out in batch mode (without view)
2.) Don't add nets to connectivity when they just
    serve for device recognition
 2019-07-02 00:07:50 +02:00
Matthias Koefferlein f931b6a1c1 Bugfix: avoid an assertion in the netlist browser 
Reason: when a circuit does not have pins and is top level,
but the reference has pins, the reference pins are regarded
to match against (nil). This case has to be reported properly,
otherwise the model can't be built consistently.
 2019-07-02 00:01:11 +02:00
Matthias Koefferlein 1e49338fe9 WIP: doc. 2019-06-30 23:36:51 +02:00
Matthias Koefferlein 2f66f3ee3b WIP: Extraction of DRC and LVS doc, added doc to classes 2019-06-28 18:44:36 +02:00
Matthias Koefferlein ef1441e546 WIP: fixed unit tests. 2019-06-28 17:08:04 +02:00
Matthias Koefferlein 6ed3838baf WIP: fixed an edit failure 2019-06-28 14:43:52 +02:00
Matthias Koefferlein ed41af9b4b WIP: added documentation to LVS script. 2019-06-28 12:50:55 +02:00
Matthias Koefferlein a8f8ca0d7d WIP: fixed a display issue and a segfault in the netlist browser. 2019-06-28 11:45:58 +02:00
Matthias Koefferlein 80d86cc425 WIP: netlist browser - allow switching between L2N and LVSDB view 2019-06-28 11:27:43 +02:00
Matthias Koefferlein 910a36b83d WIP: better matching of subcircuits - attempt to map them even if not identical. This hopefully makes solving subcircuit connection problems easier. 2019-06-28 11:05:43 +02:00
Matthias Koefferlein 3310d34cf3 WIP: better tooltips and comments for LVS browser. 2019-06-27 00:14:18 +02:00
Matthias Koefferlein 955d21a656 WIP: case insensitive compare of netlists (after reading Spice, the names are caseless) 2019-06-26 20:58:42 +02:00
Matthias Koefferlein 0cbfa698f0 WIP: debugging, development 
- LVS DSL debugging, enhancements
- Allow polygons with holes in L2N
- Spice Reader: was creating too many class objects
- Device class categorizer: allow associating A->C,B-C
- ...
 2019-06-26 20:41:49 +02:00
Matthias Koefferlein 37012efba0 WIP: fixed unit tests, bug fix in DeepRegion -> and and not shall return a DeepRegion always. 2019-06-24 20:56:20 +02:00
Matthias Koefferlein 33bb85e4f3 WIP: live actions for netlist extraction - connect etc. are no longer delayed for better error messages 2019-06-24 19:41:02 +02:00
Matthias Koefferlein 624811d55e WIP: fixed a basic issue with empty layers 
Previous: empty layers occupied a special layer in the DSS
But what when empty layers are required as outputs?
ONE layer isn't good -> would overwrite the layer and it's
no longer empty for others.
So we need to keep the layers separate.
 2019-06-23 23:44:15 +02:00
Matthias Koefferlein 464a1f35fb WIP: enhancements to DRC DSL for net extraction, some bug fixes in L2N browser etc. 2019-06-23 23:23:36 +02:00
Matthias Koefferlein 0f9c50c405 WIP: new macro category: LVS 2019-06-23 16:57:41 +02:00
Matthias Koefferlein 04f0edc814 WIP: split DRC into multiple files, bug fixed from lym management. 2019-06-23 09:25:16 +02:00