Nick Gasson
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561953e494
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Minial LPM to support continuous assignments
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2008-06-16 19:41:01 +01:00 |
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Nick Gasson
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83a7796b74
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Make sure signal names conform to VHDL rules
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2008-06-16 17:37:17 +01:00 |
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Nick Gasson
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ce72eb4eb4
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Fix Valgrind warnings
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2008-06-16 14:26:38 +01:00 |
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Nick Gasson
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7cde5f247e
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Add translation for not-equals operator
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2008-06-16 12:47:41 +01:00 |
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Nick Gasson
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849e7cb4d5
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Add equality operator
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2008-06-16 12:20:28 +01:00 |
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Nick Gasson
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92c823680a
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Fix crash when `if' statement had no `else'
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2008-06-16 12:13:01 +01:00 |
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Nick Gasson
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8a9486eb49
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Eliminate useless Resize() call
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2008-06-14 18:11:10 +01:00 |
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Nick Gasson
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2fb57805ea
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Use signed rather than std_logic_vector
Arithmetic operators now working correctly
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2008-06-14 18:03:25 +01:00 |
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Nick Gasson
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919c1d695c
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Adding binary +
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2008-06-14 17:09:31 +01:00 |
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Nick Gasson
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0ea64ad8ab
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Correct misleading comment
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2008-06-13 14:47:06 +01:00 |
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Nick Gasson
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9fbb449e06
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Optimise away empty (VHDL) processes
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2008-06-13 14:17:24 +01:00 |
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Nick Gasson
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be3c4cf268
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Generate signal initial values from `initial' processes
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2008-06-13 14:10:28 +01:00 |
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Nick Gasson
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0a8fd50c4a
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Find assignments that could be initializers
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2008-06-13 13:59:48 +01:00 |
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Nick Gasson
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70db096b6d
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Clean up the edge detector code a bit
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2008-06-13 12:52:20 +01:00 |
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Nick Gasson
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005df31a0d
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Use renamed signal in expressions, if there is one
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2008-06-13 12:39:18 +01:00 |
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Nick Gasson
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d6193c1622
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Add _Reg internal signal if output is registered
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2008-06-13 12:34:27 +01:00 |
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Nick Gasson
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b8c1f9ab67
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A system for linking ivl_signal_t to entities
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2008-06-12 20:26:23 +01:00 |
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Nick Gasson
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0df3eabe26
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Convert `if (foo) ..' to `if foo = '1' then ..'
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2008-06-12 11:36:21 +01:00 |
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Nick Gasson
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8fe2211e2b
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Generate `after' modifier instead of `wait' statements
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2008-06-12 11:24:43 +01:00 |
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Nick Gasson
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645ee2003f
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Translation for unary not
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2008-06-12 10:56:28 +01:00 |
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Nick Gasson
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d6f1162547
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Generate correct VHDL signal values
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2008-06-12 10:50:46 +01:00 |
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Nick Gasson
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46991aa65c
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Generate process bodies in the right place
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2008-06-12 10:47:52 +01:00 |
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Nick Gasson
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7eb41304e6
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Generate rising/falling edge detectors
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2008-06-12 10:36:38 +01:00 |
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Nick Gasson
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19e60b698f
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Translate if statements
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2008-06-11 14:20:05 +01:00 |
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Nick Gasson
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a7cfdc3a87
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Add VHDL if statement to AST types
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2008-06-11 14:11:37 +01:00 |
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Nick Gasson
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b010b8e3ca
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Use `assert false' as initial translation of $finish
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2008-06-11 13:37:21 +01:00 |
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Nick Gasson
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26a2c69c2e
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Change architecture name to `FromVerilog'
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2008-06-11 11:31:43 +01:00 |
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Nick Gasson
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5a7cfd8c02
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Clean up vhdl_comp_inst
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2008-06-10 14:00:15 +01:00 |
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Nick Gasson
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babe694366
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Generate port mappings
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2008-06-10 13:58:41 +01:00 |
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Nick Gasson
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7560b29fb9
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Find signals to map together
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2008-06-10 12:21:48 +01:00 |
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Nick Gasson
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f6753a9013
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Add ports to component declarations
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2008-06-10 11:24:16 +01:00 |
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Nick Gasson
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191187ed1b
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Cosmetic change to avoid useless `null' statement after delay
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2008-06-09 16:40:32 +01:00 |
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Nick Gasson
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1fb01d4d98
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Emit port declarations
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2008-06-09 16:37:05 +01:00 |
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Nick Gasson
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3106fe0ed6
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Generate port declarations for entities.
But doesn't emit them yet!
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2008-06-09 16:27:04 +01:00 |
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Nick Gasson
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e29954e03f
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Generate concurrent assignments from logic gates
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2008-06-09 15:05:32 +01:00 |
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Nick Gasson
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3b5d56e087
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Allow n-ary expressions
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2008-06-09 14:53:50 +01:00 |
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Nick Gasson
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aa91186119
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Add AST elements for unary/binary expressions to model logic gates
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2008-06-09 14:39:58 +01:00 |
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Nick Gasson
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d08f5af9c6
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Add concurrent assignments
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2008-06-09 14:21:55 +01:00 |
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Nick Gasson
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b96e471fa2
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Stub code for handling logic gates
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2008-06-09 14:08:27 +01:00 |
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Nick Gasson
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7120ab7b13
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Expression type might be null in some cases
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2008-06-09 12:54:21 +01:00 |
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Nick Gasson
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2f5dcda3b6
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Delay statements now translated correctly
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2008-06-09 12:49:38 +01:00 |
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Nick Gasson
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120b5dc80e
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Add constant integers
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2008-06-09 12:46:55 +01:00 |
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Nick Gasson
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d762253f74
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Wait statements
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2008-06-09 12:40:59 +01:00 |
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Nick Gasson
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1d28b935e8
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Split vhdl_element.cc into multiple files
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2008-06-08 13:27:48 +01:00 |
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Nick Gasson
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4b4a1c6cac
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Tidy up type casting
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2008-06-08 12:55:18 +01:00 |
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Nick Gasson
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110a1b2ac7
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Replace type classes with enumeration
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2008-06-08 12:48:56 +01:00 |
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Nick Gasson
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79558910d1
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Catch case where NULL return wasn't detected
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2008-06-07 16:44:01 +01:00 |
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Nick Gasson
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fbf85398da
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Support converting bit strings to std_logic
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2008-06-07 16:19:10 +01:00 |
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Nick Gasson
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1e4b96aa0a
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Simplify code a bit as rval type is never needed
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2008-06-07 14:57:20 +01:00 |
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Nick Gasson
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c064ae6bc3
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Generate VHDL for non-blocking assignments
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2008-06-07 14:54:00 +01:00 |
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Nick Gasson
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39228f3495
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VHDL AST element for non-blocking assignment
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2008-06-07 14:31:33 +01:00 |
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Nick Gasson
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12e2237131
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Add Type'Image cast to $display parameters
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2008-06-07 14:21:50 +01:00 |
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Nick Gasson
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066a9b7a61
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Add AST element for function call expressions
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2008-06-07 13:29:27 +01:00 |
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Nick Gasson
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cdb180e1d4
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Associate a type with each VHDL expression node
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2008-06-07 13:23:21 +01:00 |
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Nick Gasson
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a8ecce7421
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Make sure all declarations have a type
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2008-06-07 12:15:46 +01:00 |
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Nick Gasson
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8c3461f0ff
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Generate sensitivity lists properly and add signal declarations
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2008-06-07 11:48:38 +01:00 |
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Nick Gasson
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305f448d05
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Generate code for signal references
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2008-06-07 11:24:09 +01:00 |
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Nick Gasson
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5f90a3e48c
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Translate sub-statement of @{..}
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2008-06-06 18:22:03 +01:00 |
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Nick Gasson
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96cf190720
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Generate signals and sensitivity list for @(..) statement
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2008-06-06 17:56:52 +01:00 |
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Nick Gasson
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373832ba22
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Specify correct sensitivity list
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2008-06-06 17:36:15 +01:00 |
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Nick Gasson
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4f472e451e
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Stubs for statement types in mux2.v test
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2008-06-06 16:55:45 +01:00 |
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Nick Gasson
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d36bbec5b5
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Generate VHDL for no-op statements
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2008-06-05 13:16:35 +01:00 |
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Nick Gasson
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e258058cf1
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Fully qualify std.textio.Output to avoid name collisions
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2008-06-04 21:58:51 +01:00 |
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Nick Gasson
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c3ac1aac8c
|
Remove debugging messages from output
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2008-06-04 21:07:50 +01:00 |
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Nick Gasson
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234f73e7bf
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Don't generate any output if there were errors
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2008-06-04 21:03:36 +01:00 |
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Nick Gasson
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f49dd97d24
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Add support for blocks and make hello1.v test pass
|
2008-06-04 20:57:15 +01:00 |
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Nick Gasson
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7bd1565cfb
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$display now (mostly) working
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2008-06-04 20:42:44 +01:00 |
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Nick Gasson
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6e448da90d
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Emit Write() calls for parameters of $display
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2008-06-04 15:19:44 +01:00 |
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Nick Gasson
|
9f035108e1
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Stub code for translating expressions
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2008-06-04 14:59:04 +01:00 |
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Nick Gasson
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4bf2e1669d
|
Store packages required with entity rather than globally
Add parent link to architecture and process so code generators can push things higher up
$display now prints blank lines
|
2008-06-04 13:52:56 +01:00 |
|
Nick Gasson
|
dd30c1b39d
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Support procedure call generation for $display
|
2008-06-04 13:27:42 +01:00 |
|
Nick Gasson
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94006cb44c
|
Working on code generation for $display task
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2008-06-03 19:46:10 +01:00 |
|
Nick Gasson
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2e6ec91ce0
|
Scalar types
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2008-06-03 19:20:45 +01:00 |
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Nick Gasson
|
fe80da362c
|
Collect required packages as compilation progresses
|
2008-06-03 19:14:47 +01:00 |
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Nick Gasson
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82aca1b02e
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Stub code for handling $display
|
2008-06-03 18:44:17 +01:00 |
|
Nick Gasson
|
4211e651d0
|
Stub file for processing statements
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2008-06-03 18:26:36 +01:00 |
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Nick Gasson
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f9e1289463
|
Tidy up vhdl_element.cc
|
2008-06-03 17:43:54 +01:00 |
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Nick Gasson
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a09b4e3b92
|
Initial process have wait at the end
(do it properly this time rather than a hack :-)
|
2008-06-03 17:39:24 +01:00 |
|
Nick Gasson
|
ab6ae621cb
|
Remove useless comments in output
|
2008-06-02 20:24:25 +01:00 |
|
Nick Gasson
|
17ae0a6a09
|
Fix a bug where the same instantiation appeared multiple times
|
2008-06-02 18:05:39 +01:00 |
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Nick Gasson
|
041925c123
|
Component instantiation to replicate Verilog hierarchy
|
2008-06-02 17:45:58 +01:00 |
|
Nick Gasson
|
9292a087e8
|
Generate VHDL processes from Verilog processes
|
2008-06-02 16:17:01 +01:00 |
|
Nick Gasson
|
fef0fd82ff
|
Comments
|
2008-06-02 00:12:47 +01:00 |
|
Nick Gasson
|
5cbd587833
|
Clean up generated objects
|
2008-05-31 16:08:57 +01:00 |
|
Nick Gasson
|
7c9d154461
|
Forgot source files for entity generation
|
2008-05-31 15:31:48 +01:00 |
|
Nick Gasson
|
8189c4ee43
|
Generate VHDL entities and architectures for all module scopes
|
2008-05-31 15:28:25 +01:00 |
|
Nick Gasson
|
05de2f56b4
|
Dummy code for processes
|
2008-05-30 01:04:47 +01:00 |
|
Nick Gasson
|
e38494a10c
|
Pretty-print VHDL output
|
2008-05-29 16:24:16 +01:00 |
|
Nick Gasson
|
bfa2bfc8ae
|
Makefile and autoconf changes to build VHDL code generator
|
2008-05-28 17:17:39 +01:00 |