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539 Commits

Author SHA1 Message Date
Nick Gasson 899a70908e Fix small bug with initialisation and ammend comments 2008-06-24 20:13:18 +01:00
Nick Gasson bf95d77562 Finish replacing vhdl_process with vhdl_procedural 2008-06-24 20:01:06 +01:00
Nick Gasson db992e808f Start using vhdl_procedural instead of vhdl_process 2008-06-24 19:54:22 +01:00
Nick Gasson f2aca68b82 Add new vhdl_procedural superclass for process/task/func 2008-06-24 19:50:57 +01:00
Nick Gasson 12b448ef01 Merge branch 'vhdl' of git@github.com:nickg/iverilog into vhdl 
Conflicts:

	tgt-vhdl/vhdl_syntax.cc
 2008-06-24 19:42:35 +01:00
Nick Gasson e77bb0157e Remove redundant methods from vhdl_arch 2008-06-24 19:39:05 +01:00
Nick Gasson 75631bd8f1 Move is_inital code out of vhdl_process into vhdl_scope 
Part of tidy up before implementing functions
 2008-06-24 19:06:06 +01:00
Nick Gasson 63b1887ff2 Refactor code to use the new vhdl_scope class 2008-06-24 18:52:25 +01:00
Nick Gasson ba36e47575 Add new vhdl_scope class and refactor 2008-06-24 18:12:00 +01:00
Nick Gasson 3866c4526e Simplify code to emit operators 2008-06-24 14:58:58 +01:00
Nick Gasson cb08f02de1 Resize signed/unsigned bit vectors correctly 2008-06-24 10:58:21 +01:00
Nick Gasson 4188fbecee Add XOR operator and catch default case branch 2008-06-24 10:55:45 +01:00
Nick Gasson f261bf7e97 Fix bug where variables could be declared twice 2008-06-23 15:13:10 +01:00
Nick Gasson 88dc9b6b63 Remove debugging information from the output 2008-06-23 15:02:26 +01:00
Nick Gasson 632a265e14 Fix casting/resizing order bug 2008-06-23 15:00:55 +01:00
Nick Gasson 449cd0a76e Correctly generate signed/unsigned types 2008-06-23 14:28:27 +01:00
Nick Gasson 44958409f5 A slightly smarter $display 2008-06-23 13:45:24 +01:00
Nick Gasson f81129aa68 Fix some bugs with blocking assignment 2008-06-23 13:36:28 +01:00
Nick Gasson e5ef0d97bd Fix signed/unsigned resizing 2008-06-23 13:04:28 +01:00
Nick Gasson 469036990a Output blocking assignments in the right place 2008-06-23 12:30:48 +01:00
Nick Gasson d06f5c7c54 Emit loop statements with the correct indent 2008-06-23 12:27:30 +01:00
Nick Gasson 9911939576 Simplify casting code 2008-06-23 12:21:10 +01:00
Nick Gasson c9ace14c40 Shift operators working correctly 2008-06-23 12:14:12 +01:00
Nick Gasson d5cdb91d55 Handle complex expressions in case statement 2008-06-23 11:36:12 +01:00
Nick Gasson 75f7c9ae0c Only move constant assignments into initialisation 2008-06-21 16:40:18 +01:00
Nick Gasson c926454a41 Statements might be emitted in wrong order 2008-06-21 16:33:05 +01:00
Nick Gasson 5cfe7ea0aa Tidy up output 2008-06-21 16:28:07 +01:00
Nick Gasson c70fb4ba08 Simple implementation of IVL_EX_SELECT 2008-06-21 16:17:44 +01:00
Nick Gasson 7cba9f3cb2 Shift left/right 2008-06-21 15:19:33 +01:00
Nick Gasson d6acb8d059 Less than / greater than 2008-06-21 15:16:22 +01:00
Nick Gasson ec23b70bb7 While loops 2008-06-21 15:13:44 +01:00
Nick Gasson 58f2f5007d Bitwise AND 2008-06-21 15:05:48 +01:00
Nick Gasson 0caf4fd9d0 Add case statement 2008-06-21 15:03:36 +01:00
Nick Gasson 037ce08f72 Fix tiny bug in $display code 2008-06-21 14:42:54 +01:00
Nick Gasson 204862ac3c Implement $write 2008-06-20 19:00:07 +01:00
Nick Gasson 0f50849fbb Add call to To_Integer when printing signed/unsigned 2008-06-20 18:26:39 +01:00
Nick Gasson 404c22ac86 Improved implementation of $display 2008-06-20 11:51:13 +01:00
Nick Gasson 08d80b35cb Rename signals that would be illegal VHDL names 2008-06-19 16:15:47 +01:00
Nick Gasson 6622b5fe3a Compare logic values for === and !== 2008-06-19 16:08:33 +01:00
Nick Gasson d7bb5658f2 Translate IVL_ST_DELAYX statements 2008-06-19 12:16:19 +01:00
Nick Gasson be12f56856 Document blocking assignment behaviour 2008-06-18 14:04:16 +01:00
Nick Gasson e0f41198d6 Blocking assignment working correctly 2008-06-18 13:49:03 +01:00
Nick Gasson fb31a88c51 Blocking assignment nearly working 2008-06-18 13:30:19 +01:00
Nick Gasson 254ccb9ccb First passing at blocking assignment 2008-06-18 13:06:27 +01:00
Nick Gasson d2bebee9d9 Refactor before adding blocking assignment 2008-06-18 12:51:11 +01:00
Nick Gasson af8c08e6a7 Allow optional VHPI $finish implementation 2008-06-17 20:16:16 +01:00
Nick Gasson 01249000c3 Temporarily treat blocking assignment as non-blocking 2008-06-17 14:07:36 +01:00
Nick Gasson 1debbc3100 Simplify edge_detector() a bit 2008-06-16 20:06:06 +01:00
Nick Gasson ae0b09dd3a Don't bother emitting else part if it's empty 2008-06-16 19:53:42 +01:00
Nick Gasson 8d0afa632d Subtraction and multiplication LPM devices 2008-06-16 19:49:24 +01:00
Nick Gasson 561953e494 Minial LPM to support continuous assignments 2008-06-16 19:41:01 +01:00
Nick Gasson 83a7796b74 Make sure signal names conform to VHDL rules 2008-06-16 17:37:17 +01:00
Nick Gasson ce72eb4eb4 Fix Valgrind warnings 2008-06-16 14:26:38 +01:00
Nick Gasson 7cde5f247e Add translation for not-equals operator 2008-06-16 12:47:41 +01:00
Nick Gasson 849e7cb4d5 Add equality operator 2008-06-16 12:20:28 +01:00
Nick Gasson 92c823680a Fix crash when `if' statement had no `else' 2008-06-16 12:13:01 +01:00
Nick Gasson 8a9486eb49 Eliminate useless Resize() call 2008-06-14 18:11:10 +01:00
Nick Gasson 2fb57805ea Use signed rather than std_logic_vector 
Arithmetic operators now working correctly
 2008-06-14 18:03:25 +01:00
Nick Gasson 919c1d695c Adding binary + 2008-06-14 17:09:31 +01:00
Nick Gasson 0ea64ad8ab Correct misleading comment 2008-06-13 14:47:06 +01:00
Nick Gasson 9fbb449e06 Optimise away empty (VHDL) processes 2008-06-13 14:17:24 +01:00
Nick Gasson be3c4cf268 Generate signal initial values from `initial' processes 2008-06-13 14:10:28 +01:00
Nick Gasson 0a8fd50c4a Find assignments that could be initializers 2008-06-13 13:59:48 +01:00
Nick Gasson 70db096b6d Clean up the edge detector code a bit 2008-06-13 12:52:20 +01:00
Nick Gasson 005df31a0d Use renamed signal in expressions, if there is one 2008-06-13 12:39:18 +01:00
Nick Gasson d6193c1622 Add _Reg internal signal if output is registered 2008-06-13 12:34:27 +01:00
Nick Gasson b8c1f9ab67 A system for linking ivl_signal_t to entities 2008-06-12 20:26:23 +01:00
Nick Gasson 0df3eabe26 Convert `if (foo) ..' to `if foo = '1' then ..' 2008-06-12 11:36:21 +01:00
Nick Gasson 8fe2211e2b Generate `after' modifier instead of `wait' statements 2008-06-12 11:24:43 +01:00
Nick Gasson 645ee2003f Translation for unary not 2008-06-12 10:56:28 +01:00
Nick Gasson d6f1162547 Generate correct VHDL signal values 2008-06-12 10:50:46 +01:00
Nick Gasson 46991aa65c Generate process bodies in the right place 2008-06-12 10:47:52 +01:00
Nick Gasson 7eb41304e6 Generate rising/falling edge detectors 2008-06-12 10:36:38 +01:00
Nick Gasson 19e60b698f Translate if statements 2008-06-11 14:20:05 +01:00
Nick Gasson a7cfdc3a87 Add VHDL if statement to AST types 2008-06-11 14:11:37 +01:00
Nick Gasson b010b8e3ca Use `assert false' as initial translation of $finish 2008-06-11 13:37:21 +01:00
Nick Gasson 26a2c69c2e Change architecture name to `FromVerilog' 2008-06-11 11:31:43 +01:00
Nick Gasson 5a7cfd8c02 Clean up vhdl_comp_inst 2008-06-10 14:00:15 +01:00
Nick Gasson babe694366 Generate port mappings 2008-06-10 13:58:41 +01:00
Nick Gasson 7560b29fb9 Find signals to map together 2008-06-10 12:21:48 +01:00
Nick Gasson f6753a9013 Add ports to component declarations 2008-06-10 11:24:16 +01:00
Nick Gasson 191187ed1b Cosmetic change to avoid useless `null' statement after delay 2008-06-09 16:40:32 +01:00
Nick Gasson 1fb01d4d98 Emit port declarations 2008-06-09 16:37:05 +01:00
Nick Gasson 3106fe0ed6 Generate port declarations for entities. 
But doesn't emit them yet!
 2008-06-09 16:27:04 +01:00
Nick Gasson e29954e03f Generate concurrent assignments from logic gates 2008-06-09 15:05:32 +01:00
Nick Gasson 3b5d56e087 Allow n-ary expressions 2008-06-09 14:53:50 +01:00
Nick Gasson aa91186119 Add AST elements for unary/binary expressions to model logic gates 2008-06-09 14:39:58 +01:00
Nick Gasson d08f5af9c6 Add concurrent assignments 2008-06-09 14:21:55 +01:00
Nick Gasson b96e471fa2 Stub code for handling logic gates 2008-06-09 14:08:27 +01:00
Nick Gasson 7120ab7b13 Expression type might be null in some cases 2008-06-09 12:54:21 +01:00
Nick Gasson 2f5dcda3b6 Delay statements now translated correctly 2008-06-09 12:49:38 +01:00
Nick Gasson 120b5dc80e Add constant integers 2008-06-09 12:46:55 +01:00
Nick Gasson d762253f74 Wait statements 2008-06-09 12:40:59 +01:00
Nick Gasson 1d28b935e8 Split vhdl_element.cc into multiple files 2008-06-08 13:27:48 +01:00
Nick Gasson 4b4a1c6cac Tidy up type casting 2008-06-08 12:55:18 +01:00
Nick Gasson 110a1b2ac7 Replace type classes with enumeration 2008-06-08 12:48:56 +01:00
Nick Gasson 79558910d1 Catch case where NULL return wasn't detected 2008-06-07 16:44:01 +01:00
Nick Gasson fbf85398da Support converting bit strings to std_logic 2008-06-07 16:19:10 +01:00
Nick Gasson 1e4b96aa0a Simplify code a bit as rval type is never needed 2008-06-07 14:57:20 +01:00
Nick Gasson c064ae6bc3 Generate VHDL for non-blocking assignments 2008-06-07 14:54:00 +01:00
Nick Gasson 39228f3495 VHDL AST element for non-blocking assignment 2008-06-07 14:31:33 +01:00
Nick Gasson 12e2237131 Add Type'Image cast to $display parameters 2008-06-07 14:21:50 +01:00
Nick Gasson 066a9b7a61 Add AST element for function call expressions 2008-06-07 13:29:27 +01:00
Nick Gasson cdb180e1d4 Associate a type with each VHDL expression node 2008-06-07 13:23:21 +01:00
Nick Gasson a8ecce7421 Make sure all declarations have a type 2008-06-07 12:15:46 +01:00
Nick Gasson 8c3461f0ff Generate sensitivity lists properly and add signal declarations 2008-06-07 11:48:38 +01:00
Nick Gasson 305f448d05 Generate code for signal references 2008-06-07 11:24:09 +01:00
Nick Gasson 5f90a3e48c Translate sub-statement of @{..} 2008-06-06 18:22:03 +01:00
Nick Gasson 96cf190720 Generate signals and sensitivity list for @(..) statement 2008-06-06 17:56:52 +01:00
Nick Gasson 373832ba22 Specify correct sensitivity list 2008-06-06 17:36:15 +01:00
Nick Gasson 4f472e451e Stubs for statement types in mux2.v test 2008-06-06 16:55:45 +01:00
Nick Gasson d36bbec5b5 Generate VHDL for no-op statements 2008-06-05 13:16:35 +01:00
Nick Gasson e258058cf1 Fully qualify std.textio.Output to avoid name collisions 2008-06-04 21:58:51 +01:00
Nick Gasson c3ac1aac8c Remove debugging messages from output 2008-06-04 21:07:50 +01:00
Nick Gasson 234f73e7bf Don't generate any output if there were errors 2008-06-04 21:03:36 +01:00
Nick Gasson f49dd97d24 Add support for blocks and make hello1.v test pass 2008-06-04 20:57:15 +01:00
Nick Gasson 7bd1565cfb $display now (mostly) working 2008-06-04 20:42:44 +01:00
Nick Gasson 6e448da90d Emit Write() calls for parameters of $display 2008-06-04 15:19:44 +01:00
Nick Gasson 9f035108e1 Stub code for translating expressions 2008-06-04 14:59:04 +01:00
Nick Gasson 4bf2e1669d Store packages required with entity rather than globally 
Add parent link to architecture and process so code generators can push things higher up
$display now prints blank lines
 2008-06-04 13:52:56 +01:00
Nick Gasson dd30c1b39d Support procedure call generation for $display 2008-06-04 13:27:42 +01:00
Nick Gasson 94006cb44c Working on code generation for $display task 2008-06-03 19:46:10 +01:00
Nick Gasson 2e6ec91ce0 Scalar types 2008-06-03 19:20:45 +01:00
Nick Gasson fe80da362c Collect required packages as compilation progresses 2008-06-03 19:14:47 +01:00
Nick Gasson 82aca1b02e Stub code for handling $display 2008-06-03 18:44:17 +01:00
Nick Gasson 4211e651d0 Stub file for processing statements 2008-06-03 18:26:36 +01:00
Nick Gasson f9e1289463 Tidy up vhdl_element.cc 2008-06-03 17:43:54 +01:00
Nick Gasson a09b4e3b92 Initial process have wait at the end 
(do it properly this time rather than a hack :-)
 2008-06-03 17:39:24 +01:00
Nick Gasson ab6ae621cb Remove useless comments in output 2008-06-02 20:24:25 +01:00
Nick Gasson 17ae0a6a09 Fix a bug where the same instantiation appeared multiple times 2008-06-02 18:05:39 +01:00
Nick Gasson 041925c123 Component instantiation to replicate Verilog hierarchy 2008-06-02 17:45:58 +01:00
Nick Gasson 9292a087e8 Generate VHDL processes from Verilog processes 2008-06-02 16:17:01 +01:00
Nick Gasson fef0fd82ff Comments 2008-06-02 00:12:47 +01:00
Nick Gasson 5cbd587833 Clean up generated objects 2008-05-31 16:08:57 +01:00
Nick Gasson 7c9d154461 Forgot source files for entity generation 2008-05-31 15:31:48 +01:00
Nick Gasson 8189c4ee43 Generate VHDL entities and architectures for all module scopes 2008-05-31 15:28:25 +01:00
Nick Gasson 05de2f56b4 Dummy code for processes 2008-05-30 01:04:47 +01:00
Nick Gasson e38494a10c Pretty-print VHDL output 2008-05-29 16:24:16 +01:00
Nick Gasson bfa2bfc8ae Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00