AngeloJacobo
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058da90bfc
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changed SKIP_INTERNAL_TEST to BIST_MODE (0,1, or 2)
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2025-02-09 09:45:30 +08:00 |
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AngeloJacobo
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016df010c7
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added regression test shell scrip to simulate multiple corners
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2025-01-30 19:16:11 +08:00 |
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AngeloJacobo
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760979db27
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hardware runs on ddr3-1333! Now working on ddr3-1600
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2025-01-19 17:15:40 +08:00 |
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AngeloJacobo
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339adfe8d6
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added simulation and project demo with XADC
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2025-01-12 14:55:43 +08:00 |
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AngeloJacobo
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fbb3b65aaf
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added waveform for spd reader testbench
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2025-01-02 13:02:05 +08:00 |
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AngeloJacobo
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7acaf34b44
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added uart to display spd report
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2024-12-29 20:41:17 +08:00 |
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AngeloJacobo
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75857a0af0
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read bytes 0 to 63 of spd then store (sim passing)
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2024-12-29 14:47:57 +08:00 |
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AngeloJacobo
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fbc4b5ff9a
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added initial files for spd
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2024-12-29 12:18:37 +08:00 |
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AngeloJacobo
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7367182640
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dual rank enabled is now passing formal and simulation!
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2024-12-20 18:56:21 +08:00 |
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AngeloJacobo
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4fdaace899
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add dual-rank feature (PHY ongoing changes)
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2024-12-02 11:28:21 +08:00 |
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AngeloJacobo
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e08612658b
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self-refresh feature done, passing simulation and formal
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2024-11-24 14:31:20 +08:00 |
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AngeloJacobo
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1078e2ffe0
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Revert "add self-refresh option, passing Simulation, ongoing formal"
This reverts commit a5e2adf4a4.
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2024-11-23 11:43:05 +08:00 |
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AngeloJacobo
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a5e2adf4a4
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add self-refresh option, passing Simulation, ongoing formal
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2024-11-17 20:47:14 +08:00 |
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AngeloJacobo
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c58a9d70e6
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add self-refresh feature (untested)
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2024-11-03 14:52:32 +08:00 |
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AngeloJacobo
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6f5eb49e79
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add vivado batch sim script (just run run_batch.sh)
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2024-07-28 17:39:21 +08:00 |
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AngeloJacobo
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55bb8be939
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stb now goes low (instead of fixed high)
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2024-07-28 17:37:15 +08:00 |
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AngeloJacobo
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a458a06de0
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add test for ECC
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2024-06-29 19:36:35 +08:00 |
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AngeloJacobo
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7d93717b72
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add initial ECC, ECC_ENABLE = 2 working
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2024-06-17 16:25:06 +08:00 |
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AngeloJacobo
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8fb24dd180
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add copyright on headers
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2024-06-09 12:01:30 +08:00 |
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AngeloJacobo
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91fc6d8ed6
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moved axi-related files to separate folders
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2024-06-03 17:36:19 +08:00 |
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AngeloJacobo
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66f0daf0e9
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added AXI4 feature
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2024-06-01 15:30:15 +08:00 |
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Angelo Jacobo
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e9633ddae7
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fixed instantiation template
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2024-05-05 13:27:51 +08:00 |
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Angelo Jacobo
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4491ddaa18
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update waveform config
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2024-04-28 16:22:30 +08:00 |
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Angelo Jacobo
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f70180b7c7
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add calibration_state signal to monitor calibration
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2024-04-28 16:22:11 +08:00 |
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Angelo Jacobo
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a14afa4c4b
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zero all delays
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2024-04-28 16:21:07 +08:00 |
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Angelo Jacobo
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926e167376
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zero all delays
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2024-04-28 16:20:39 +08:00 |
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Angelo Jacobo
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d959ecf8d2
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make vivado waveform config more organized
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2024-04-21 13:47:37 +08:00 |
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Angelo Jacobo
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d2f0fd046b
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correct clock periods to ps
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2024-04-20 12:26:39 +08:00 |
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AngeloJacobo
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2a926cfc91
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moved ARTY-S7 project files
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2023-11-26 14:04:15 +08:00 |
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AngeloJacobo
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8d20a6f4d0
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moved wcfg file inside testbench
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2023-11-26 13:53:43 +08:00 |
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AngeloJacobo
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ba98139c56
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changed the extension of all simulation files to systemverilog
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2023-11-26 13:53:02 +08:00 |
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AngeloJacobo
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dcb48b75d3
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changed the extension of all simulation files to systemverilog
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2023-11-26 13:51:30 +08:00 |
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AngeloJacobo
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b54000f5f0
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fix instantiation
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2023-11-18 13:41:39 +08:00 |
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AngeloJacobo
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b9b49d67ab
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add xdc file used to test controller in Arty-S7
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2023-11-09 14:16:46 +08:00 |
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AngeloJacobo
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0b7d07e133
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delete old bit and debug files
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2023-11-09 14:14:27 +08:00 |
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AngeloJacobo
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2037044fb4
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fixed reset logic of _top, changed address accessed by ~
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2023-11-09 14:13:08 +08:00 |
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AngeloJacobo
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57e9f1b3f9
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update simulation files
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2023-09-15 20:04:55 +08:00 |
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AngeloJacobo
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0ba4f433e5
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add delay option to misalign dq from dqs
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2023-09-15 20:02:05 +08:00 |
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AngeloJacobo
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fd443ddefd
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add wb2 width
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2023-08-20 13:23:48 +08:00 |
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AngeloJacobo
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a8aec13ed9
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using different address now finally works!
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2023-08-20 11:52:54 +08:00 |
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AngeloJacobo
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5df83b8182
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added working bitfiles for arty s7
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2023-08-20 11:20:41 +08:00 |
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AngeloJacobo
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989e8dd9e7
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use macro for defining the ddr3 config (EIGHT_LANES_x8 or TWO_LANES_x8) and the source of clk (if clock wizard or not)
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2023-08-20 11:13:50 +08:00 |
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AngeloJacobo
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7c68bee5e8
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changed for x8 config
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2023-08-20 11:10:15 +08:00 |
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AngeloJacobo
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e839e220c3
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ddr3 model fails when ROW_BITS less than 16 (has Z value in address)
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2023-08-17 11:42:09 +08:00 |
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AngeloJacobo
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c97e5a8c1f
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added test for testing design in ARTY-S7
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2023-08-17 11:40:41 +08:00 |
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AngeloJacobo
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c9b19ac887
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added uart submodule
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2023-08-17 11:36:15 +08:00 |
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AngeloJacobo
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a8bf429bc8
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allow tdqs off and use dm
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2023-08-15 21:17:13 +08:00 |
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AngeloJacobo
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bc66655ca7
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just fixed delay
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2023-08-04 07:54:20 +08:00 |
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AngeloJacobo
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d2ae29c26a
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simulation file for SODIMM
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2023-07-24 17:34:40 +08:00 |
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AngeloJacobo
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4e5b98f485
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use SODIMM instead of DIMM in simulation
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2023-07-24 17:32:56 +08:00 |