zero all delays

2024-04-28 16:21:07 +08:00 · 2024-04-28 16:21:07 +08:00 · a14afa4c4b
parent 926e167376
commit a14afa4c4b
1 changed files with 1 additions and 1 deletions
--- a/testbench/ddr3.sv
+++ b/testbench/ddr3.sv
@ -138,7 +138,7 @@ module ddr3 (
    parameter feature_truebl4 = 0;
    parameter feature_odt_hi = 0;
    parameter PERTCKAVG=TDLLK;
-    parameter FLY_BY_DELAY = 1600, DQ_DELAY = 0;
+    parameter FLY_BY_DELAY = 0, DQ_DELAY = 0;
    
    // text macros
    `define DQ_PER_DQS DQ_BITS/DQS_BITS