moved axi-related files to separate folders
This commit is contained in:
AngeloJacobo
parent
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313
rtl/migsdram.v
313
rtl/migsdram.v
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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: migsdram.v
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// {{{
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// Project: WB2AXIPSP: bus bridges and other odds and ends
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//
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// Purpose: This file isn't really a part of the synthesis implementation
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// of the wb2axip project itself, but rather it is an example
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// of how the wb2axip project can be used to connect a MIG generated
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// IP component.
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//
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// This implementation depends upon the existence of a MIG generated
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// core, named "mig_axis", and illustrates how such a core might be
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// connected to the wbm2axip bridge. Specific options of the mig_axis
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// setup include 6 identifier bits, and a full-sized bus width of 128
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// bits. These two settings are both appropriate for driving a DDR3
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// memory (whose minimum transfer size is 128 bits), but may need to be
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// adjusted to support other memories.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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// }}}
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// Copyright (C) 2015-2024, Gisselquist Technology, LLC
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// {{{
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// This file is part of the WB2AXIP project.
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//
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// The WB2AXIP project contains free software and gateware, licensed under the
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// Apache License, Version 2.0 (the "License"). You may not use this project,
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// or this file, except in compliance with the License. You may obtain a copy
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// of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// License for the specific language governing permissions and limitations
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// under the License.
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype none
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// }}}
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module migsdram(i_clk, i_clk_200mhz, o_sys_clk, i_rst, o_sys_reset,
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// Wishbone components
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel,
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o_wb_ack, o_wb_stall, o_wb_data, o_wb_err,
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// SDRAM connections
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o_ddr_ck_p, o_ddr_ck_n,
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o_ddr_reset_n, o_ddr_cke,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_ba, o_ddr_addr,
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o_ddr_odt, o_ddr_dm,
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io_ddr_dqs_p, io_ddr_dqs_n,
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io_ddr_data
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);
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parameter DDRWIDTH = 16, WBDATAWIDTH=32;
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parameter AXIDWIDTH = 6;
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// The SDRAM address bits (RAMABITS) are a touch more difficult to work
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// out. Here we leave them as a fixed parameter, but there are
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// consequences to this. Specifically, the wishbone data width, the
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// wishbone address width, and this number have interactions not
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// well captured here.
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parameter RAMABITS = 28;
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// All DDR3 memories have 8 timeslots. This, if the DDR3 memory
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// has 16 bits to it (as above), the entire transaction must take
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// AXIWIDTH bits ...
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localparam AXIWIDTH= DDRWIDTH *8;
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localparam DW=WBDATAWIDTH;
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localparam AW=(WBDATAWIDTH==32)? RAMABITS-2
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:((WBDATAWIDTH==64) ? RAMABITS-3
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:((WBDATAWIDTH==128) ? RAMABITS-4
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: RAMABITS-5)); // (WBDATAWIDTH==256)
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localparam SELW= (WBDATAWIDTH/8);
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//
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input wire i_clk, i_clk_200mhz, i_rst;
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output wire o_sys_clk;
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output reg o_sys_reset;
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//
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input wire i_wb_cyc, i_wb_stb, i_wb_we;
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input wire [(AW-1):0] i_wb_addr;
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input wire [(DW-1):0] i_wb_data;
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input wire [(SELW-1):0] i_wb_sel;
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output wire o_wb_ack, o_wb_stall;
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output wire [(DW-1):0] o_wb_data;
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output wire o_wb_err;
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//
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output wire [0:0] o_ddr_ck_p, o_ddr_ck_n;
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output wire [0:0] o_ddr_cke;
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output wire o_ddr_reset_n,
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o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n;
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output wire [0:0] o_ddr_cs_n;
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output wire [2:0] o_ddr_ba;
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output wire [13:0] o_ddr_addr;
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output wire [0:0] o_ddr_odt;
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output wire [(DDRWIDTH/8-1):0] o_ddr_dm;
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inout wire [1:0] io_ddr_dqs_p, io_ddr_dqs_n;
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inout wire [(DDRWIDTH-1):0] io_ddr_data;
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`define SDRAM_ACCESS
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`ifdef SDRAM_ACCESS
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wire aresetn;
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assign aresetn = 1'b1; // Never reset
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// Write address channel
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wire [(AXIDWIDTH-1):0] s_axi_awid;
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wire [(RAMABITS-1):0] s_axi_awaddr;
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wire [7:0] s_axi_awlen;
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wire [2:0] s_axi_awsize;
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wire [1:0] s_axi_awburst;
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wire [0:0] s_axi_awlock;
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wire [3:0] s_axi_awcache;
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wire [2:0] s_axi_awprot;
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wire [3:0] s_axi_awqos;
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wire s_axi_awvalid;
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wire s_axi_awready;
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// Writei data channel
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wire [(AXIWIDTH-1):0] s_axi_wdata;
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wire [(AXIWIDTH/8-1):0] s_axi_wstrb;
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wire s_axi_wlast, s_axi_wvalid, s_axi_wready;
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// Write response channel
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wire s_axi_bready;
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wire [(AXIDWIDTH-1):0] s_axi_bid;
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wire [1:0] s_axi_bresp;
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wire s_axi_bvalid;
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// Read address channel
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wire [(AXIDWIDTH-1):0] s_axi_arid;
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wire [(RAMABITS-1):0] s_axi_araddr;
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wire [7:0] s_axi_arlen;
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wire [2:0] s_axi_arsize;
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wire [1:0] s_axi_arburst;
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wire [0:0] s_axi_arlock;
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wire [3:0] s_axi_arcache;
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wire [2:0] s_axi_arprot;
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wire [3:0] s_axi_arqos;
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wire s_axi_arvalid;
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wire s_axi_arready;
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// Read response/data channel
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wire [(AXIDWIDTH-1):0] s_axi_rid;
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wire [(AXIWIDTH-1):0] s_axi_rdata;
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wire [1:0] s_axi_rresp;
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wire s_axi_rlast;
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wire s_axi_rvalid;
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wire s_axi_rready;
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// Other wires ...
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wire init_calib_complete, mmcm_locked;
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wire app_sr_active, app_ref_ack, app_zq_ack;
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wire app_sr_req, app_ref_req, app_zq_req;
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wire w_sys_reset;
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wire [11:0] w_device_temp;
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mig_axis mig_sdram(
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.ddr3_ck_p(o_ddr_ck_p), .ddr3_ck_n(o_ddr_ck_n),
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.ddr3_reset_n(o_ddr_reset_n), .ddr3_cke(o_ddr_cke),
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.ddr3_cs_n(o_ddr_cs_n), .ddr3_ras_n(o_ddr_ras_n),
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.ddr3_we_n(o_ddr_we_n), .ddr3_cas_n(o_ddr_cas_n),
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.ddr3_ba(o_ddr_ba), .ddr3_addr(o_ddr_addr),
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.ddr3_odt(o_ddr_odt),
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.ddr3_dqs_p(io_ddr_dqs_p), .ddr3_dqs_n(io_ddr_dqs_n),
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.ddr3_dq(io_ddr_data), .ddr3_dm(o_ddr_dm),
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//
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.sys_clk_i(i_clk),
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.clk_ref_i(i_clk_200mhz),
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.ui_clk(o_sys_clk),
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.ui_clk_sync_rst(w_sys_reset),
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.mmcm_locked(mmcm_locked),
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.aresetn(aresetn),
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.app_sr_req(1'b0),
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.app_ref_req(1'b0),
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.app_zq_req(1'b0),
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.app_sr_active(app_sr_active),
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.app_ref_ack(app_ref_ack),
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.app_zq_ack(app_zq_ack),
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//
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.s_axi_awid(s_axi_awid), .s_axi_awaddr(s_axi_awaddr),
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.s_axi_awlen(s_axi_awlen), .s_axi_awsize(s_axi_awsize),
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.s_axi_awburst(s_axi_awburst), .s_axi_awlock(s_axi_awlock),
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.s_axi_awcache(s_axi_awcache), .s_axi_awprot(s_axi_awprot),
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.s_axi_awqos(s_axi_awqos), .s_axi_awvalid(s_axi_awvalid),
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.s_axi_awready(s_axi_awready),
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//
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.s_axi_wready( s_axi_wready),
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.s_axi_wdata( s_axi_wdata),
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.s_axi_wstrb( s_axi_wstrb),
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.s_axi_wlast( s_axi_wlast),
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.s_axi_wvalid( s_axi_wvalid),
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//
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.s_axi_bready(s_axi_bready), .s_axi_bid(s_axi_bid),
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.s_axi_bresp(s_axi_bresp), .s_axi_bvalid(s_axi_bvalid),
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//
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.s_axi_arid(s_axi_arid), .s_axi_araddr(s_axi_araddr),
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.s_axi_arlen(s_axi_arlen), .s_axi_arsize(s_axi_arsize),
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.s_axi_arburst(s_axi_arburst), .s_axi_arlock(s_axi_arlock),
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.s_axi_arcache(s_axi_arcache), .s_axi_arprot(s_axi_arprot),
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.s_axi_arqos(s_axi_arqos), .s_axi_arvalid(s_axi_arvalid),
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.s_axi_arready(s_axi_arready),
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//
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.s_axi_rready(s_axi_rready), .s_axi_rid(s_axi_rid),
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.s_axi_rdata(s_axi_rdata), .s_axi_rresp(s_axi_rresp),
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.s_axi_rlast(s_axi_rlast), .s_axi_rvalid(s_axi_rvalid),
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.init_calib_complete(init_calib_complete),
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.sys_rst(i_rst),
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.device_temp(w_device_temp)
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);
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wbm2axisp #(
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.C_AXI_ID_WIDTH(AXIDWIDTH),
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.C_AXI_DATA_WIDTH(AXIWIDTH),
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.C_AXI_ADDR_WIDTH(RAMABITS),
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.AW(AW), .DW(DW)
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)
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bus_translator(
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.i_clk(o_sys_clk),
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// .i_reset(i_rst), // internally unused
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// Write address channel signals
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.o_axi_awvalid( s_axi_awvalid),
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.i_axi_awready( s_axi_awready),
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.o_axi_awid( s_axi_awid),
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.o_axi_awaddr( s_axi_awaddr),
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.o_axi_awlen( s_axi_awlen),
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.o_axi_awsize( s_axi_awsize),
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.o_axi_awburst( s_axi_awburst),
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.o_axi_awlock( s_axi_awlock),
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.o_axi_awcache( s_axi_awcache),
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.o_axi_awprot( s_axi_awprot), // s_axi_awqos
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.o_axi_awqos( s_axi_awqos), // s_axi_awqos
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//
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.o_axi_wvalid( s_axi_wvalid),
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.i_axi_wready( s_axi_wready),
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.o_axi_wdata( s_axi_wdata),
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.o_axi_wstrb( s_axi_wstrb),
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.o_axi_wlast( s_axi_wlast),
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//
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.i_axi_bvalid( s_axi_bvalid),
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.o_axi_bready( s_axi_bready),
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.i_axi_bid( s_axi_bid),
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.i_axi_bresp( s_axi_bresp),
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//
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.o_axi_arvalid( s_axi_arvalid),
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.i_axi_arready( s_axi_arready),
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.o_axi_arid( s_axi_arid),
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.o_axi_araddr( s_axi_araddr),
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.o_axi_arlen( s_axi_arlen),
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.o_axi_arsize( s_axi_arsize),
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.o_axi_arburst( s_axi_arburst),
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.o_axi_arlock( s_axi_arlock),
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.o_axi_arcache( s_axi_arcache),
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.o_axi_arprot( s_axi_arprot),
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.o_axi_arqos( s_axi_arqos),
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//
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.i_axi_rvalid( s_axi_rvalid),
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.o_axi_rready( s_axi_rready),
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.i_axi_rid( s_axi_rid),
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.i_axi_rdata( s_axi_rdata),
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.i_axi_rresp( s_axi_rresp),
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.i_axi_rlast( s_axi_rlast),
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//
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.i_wb_cyc( i_wb_cyc),
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.i_wb_stb( i_wb_stb),
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.i_wb_we( i_wb_we),
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.i_wb_addr( i_wb_addr),
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.i_wb_data( i_wb_data),
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.i_wb_sel( i_wb_sel),
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//
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.o_wb_stall( o_wb_stall),
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.o_wb_ack( o_wb_ack),
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.o_wb_data( o_wb_data),
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.o_wb_err( o_wb_err)
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);
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// Convert from active low to active high, *and* hold the system in
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// reset until the memory comes up.
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initial o_sys_reset = 1'b1;
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always @(posedge o_sys_clk)
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o_sys_reset <= (!w_sys_reset)
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||(!init_calib_complete)
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||(!mmcm_locked);
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`else
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BUFG sysclk(i_clk, o_sys_clk);
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initial o_sys_reset <= 1'b1;
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always @(posedge i_clk)
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o_sys_reset <= 1'b1;
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OBUFDS ckobuf(.I(i_clk), .O(o_ddr_ck_p), .OB(o_ddr_ck_n));
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assign o_ddr_reset_n = 1'b0;
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assign o_ddr_cke[0] = 1'b0;
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assign o_ddr_cs_n[0] = 1'b1;
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assign o_ddr_cas_n = 1'b1;
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assign o_ddr_ras_n = 1'b1;
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assign o_ddr_we_n = 1'b1;
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assign o_ddr_ba = 3'h0;
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assign o_ddr_addr = 14'h00;
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assign o_ddr_dm = 2'b00;
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assign io_ddr_data = 16'h0;
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OBUFDS dqsbufa(.I(i_clk), .O(io_ddr_dqs_p[1]), .OB(io_ddr_dqs_n[1]));
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OBUFDS dqsbufb(.I(i_clk), .O(io_ddr_dqs_p[0]), .OB(io_ddr_dqs_n[0]));
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`endif
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endmodule
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`ifndef YOSYS
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`default_nettype wire
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`endif
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@ -0,0 +1,258 @@
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memory_initialization_radix = 16;
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memory_initialization_vector =
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00000000
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00000000
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00000010
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00000010
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00000020
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00000020
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00000030
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00000030
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00000040
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00000040
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00000050
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00000050
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00000060
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00000060
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00000070
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00000070
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00000000
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00000000
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00000000
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00000000
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00000000
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00000000
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00000000
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||||
00000000
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|
|
@ -0,0 +1,258 @@
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Binary file not shown.
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@ -0,0 +1,258 @@
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;
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|
|
@ -0,0 +1,205 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
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|
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|
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|
||||
<db_ref_list>
|
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|
||||
<top_modules>
|
||||
<top_module name="ddr3_axi_traffic_gen_tb" />
|
||||
<top_module name="glbl" />
|
||||
</top_modules>
|
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</db_ref>
|
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|
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|
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|
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|
||||
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|
||||
<obj_property name="ObjectShortName">i_controller_clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/i_ddr3_clk">
|
||||
<obj_property name="ElementShortName">i_ddr3_clk</obj_property>
|
||||
<obj_property name="ObjectShortName">i_ddr3_clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/i_ref_clk">
|
||||
<obj_property name="ElementShortName">i_ref_clk</obj_property>
|
||||
<obj_property name="ObjectShortName">i_ref_clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/i_ddr3_clk_90">
|
||||
<obj_property name="ElementShortName">i_ddr3_clk_90</obj_property>
|
||||
<obj_property name="ObjectShortName">i_ddr3_clk_90</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/i_rst_n">
|
||||
<obj_property name="ElementShortName">i_rst_n</obj_property>
|
||||
<obj_property name="ObjectShortName">i_rst_n</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="divider622" type="divider">
|
||||
<obj_property name="label">AXI Lite (Traffic Generator)</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/axi_traffic_gen_inst/s_axi_aclk">
|
||||
<obj_property name="ElementShortName">s_axi_aclk</obj_property>
|
||||
<obj_property name="ObjectShortName">s_axi_aclk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/axi_traffic_gen_inst/s_axi_aresetn">
|
||||
<obj_property name="ElementShortName">s_axi_aresetn</obj_property>
|
||||
<obj_property name="ObjectShortName">s_axi_aresetn</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/axi_traffic_gen_inst/m_axi_lite_ch1_awaddr">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_awaddr[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_awaddr[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/axi_traffic_gen_inst/m_axi_lite_ch1_awprot">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_awprot[2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_awprot[2:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/axi_traffic_gen_inst/m_axi_lite_ch1_awvalid">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_awvalid</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_awvalid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/axi_traffic_gen_inst/m_axi_lite_ch1_awready">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_awready</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_awready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/axi_traffic_gen_inst/m_axi_lite_ch1_wdata">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_wdata[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_wdata[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/axi_traffic_gen_inst/m_axi_lite_ch1_wstrb">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_wstrb[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_wstrb[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/axi_traffic_gen_inst/m_axi_lite_ch1_wvalid">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_wvalid</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_wvalid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/axi_traffic_gen_inst/m_axi_lite_ch1_wready">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_wready</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_wready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/axi_traffic_gen_inst/m_axi_lite_ch1_bresp">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_bresp[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_bresp[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/axi_traffic_gen_inst/m_axi_lite_ch1_bvalid">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_bvalid</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_bvalid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/axi_traffic_gen_inst/m_axi_lite_ch1_bready">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_bready</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_bready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/m_axi_lite_ch1_araddr">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_araddr[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_araddr[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/m_axi_lite_ch1_arvalid">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_arvalid</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_arvalid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/m_axi_lite_ch1_arready">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_arready</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_arready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/m_axi_lite_ch1_rdata">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_rdata[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_rdata[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/m_axi_lite_ch1_rvalid">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_rvalid</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_rvalid</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/m_axi_lite_ch1_rresp">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_rresp[1:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_rresp[1:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/m_axi_lite_ch1_rready">
|
||||
<obj_property name="ElementShortName">m_axi_lite_ch1_rready</obj_property>
|
||||
<obj_property name="ObjectShortName">m_axi_lite_ch1_rready</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/axi_traffic_gen_inst/done">
|
||||
<obj_property name="ElementShortName">done</obj_property>
|
||||
<obj_property name="ObjectShortName">done</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/axi_traffic_gen_inst/status">
|
||||
<obj_property name="ElementShortName">status[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">status[31:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/dut/s_axi_wdata">
|
||||
<obj_property name="ElementShortName">s_axi_wdata[127:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">s_axi_wdata[127:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/dut/s_axi_wstrb">
|
||||
<obj_property name="ElementShortName">s_axi_wstrb[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">s_axi_wstrb[15:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="divider621" type="divider">
|
||||
<obj_property name="label">Controller</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/dut/ddr3_top_inst/ddr3_controller_inst/instruction_address">
|
||||
<obj_property name="ElementShortName">instruction_address[4:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">instruction_address[4:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/dut/ddr3_top_inst/ddr3_controller_inst/state_calibrate">
|
||||
<obj_property name="ElementShortName">state_calibrate[5:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">state_calibrate[5:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/dut/ddr3_top_inst/ddr3_controller_inst/lane">
|
||||
<obj_property name="ElementShortName">lane[0:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">lane[0:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/dut/ddr3_top_inst/ddr3_controller_inst/correct_read_data">
|
||||
<obj_property name="ElementShortName">correct_read_data[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">correct_read_data[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/dut/ddr3_top_inst/ddr3_controller_inst/wrong_read_data">
|
||||
<obj_property name="ElementShortName">wrong_read_data[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">wrong_read_data[31:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/dut/ddr3_top_inst/i_wb_cyc">
|
||||
<obj_property name="ElementShortName">i_wb_cyc</obj_property>
|
||||
<obj_property name="ObjectShortName">i_wb_cyc</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/dut/ddr3_top_inst/i_wb_stb">
|
||||
<obj_property name="ElementShortName">i_wb_stb</obj_property>
|
||||
<obj_property name="ObjectShortName">i_wb_stb</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/dut/ddr3_top_inst/i_wb_we">
|
||||
<obj_property name="ElementShortName">i_wb_we</obj_property>
|
||||
<obj_property name="ObjectShortName">i_wb_we</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/dut/ddr3_top_inst/i_wb_addr">
|
||||
<obj_property name="ElementShortName">i_wb_addr[23:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">i_wb_addr[23:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/dut/ddr3_top_inst/i_wb_data">
|
||||
<obj_property name="ElementShortName">i_wb_data[127:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">i_wb_data[127:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/dut/ddr3_top_inst/i_wb_sel">
|
||||
<obj_property name="ElementShortName">i_wb_sel[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">i_wb_sel[15:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/dut/ddr3_top_inst/o_wb_stall">
|
||||
<obj_property name="ElementShortName">o_wb_stall</obj_property>
|
||||
<obj_property name="ObjectShortName">o_wb_stall</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/ddr3_axi_traffic_gen_tb/dut/ddr3_top_inst/o_wb_ack">
|
||||
<obj_property name="ElementShortName">o_wb_ack</obj_property>
|
||||
<obj_property name="ObjectShortName">o_wb_ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/ddr3_axi_traffic_gen_tb/dut/ddr3_top_inst/o_wb_data">
|
||||
<obj_property name="ElementShortName">o_wb_data[127:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">o_wb_data[127:0]</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
module ddr3_axi_traffic_gen;
|
||||
module ddr3_axi_traffic_gen_tb;
|
||||
|
||||
reg i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90;
|
||||
reg i_rst_n;
|
||||
|
|
@ -68,7 +68,7 @@ wire m_axi_lite_ch1_rready;
|
|||
wire done;
|
||||
wire [31 : 0] status;
|
||||
|
||||
axi_traffic_gen_1 axi_traffic_gen_inst(
|
||||
axi_traffic_gen_0 axi_traffic_gen_inst(
|
||||
.s_axi_aclk(i_controller_clk),
|
||||
.s_axi_aresetn(i_rst_n && (dut.ddr3_top_inst.ddr3_controller_inst.state_calibrate == 23)), //stay reset until calibration is done
|
||||
.m_axi_lite_ch1_awaddr(m_axi_lite_ch1_awaddr),
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
memory_initialization_radix = 16;
|
||||
memory_initialization_vector =
|
||||
ffffffff
|
||||
00000000
|
||||
ffffffff
|
||||
00000000
|
||||
ffffffff
|
||||
00000000
|
||||
ffffffff
|
||||
00000000
|
||||
ffffffff
|
||||
00000000
|
||||
ffffffff
|
||||
00000000
|
||||
ffffffff
|
||||
00000000
|
||||
ffffffff
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
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00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
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00000000
|
||||
00000000
|
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00000000
|
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00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
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00000000
|
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00000000
|
||||
00000000
|
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00000000
|
||||
00000000
|
||||
00000000
|
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00000000
|
||||
00000000
|
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00000000
|
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00000000
|
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00000000
|
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00000000
|
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00000000
|
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00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
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00000000
|
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00000000
|
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00000000
|
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00000000
|
||||
00000000
|
||||
00000000
|
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00000000
|
||||
00000000
|
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00000000
|
||||
00000000
|
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00000000
|
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00000000
|
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00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
;
|
||||
|
|
@ -1,282 +0,0 @@
|
|||
module ddr3_axi_tb;
|
||||
|
||||
reg i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90;
|
||||
reg i_rst_n;
|
||||
|
||||
// AXI Interface
|
||||
// AXI write address channel signals
|
||||
reg s_axi_awvalid;
|
||||
wire s_axi_awready;
|
||||
reg [dut.AXI_ID_WIDTH-1:0] s_axi_awid;
|
||||
reg [dut.AXI_ADDR_WIDTH-1:0] s_axi_awaddr;
|
||||
// AXI write data channel signals
|
||||
reg s_axi_wvalid;
|
||||
wire s_axi_wready;
|
||||
reg [dut.AXI_DATA_WIDTH-1:0] s_axi_wdata;
|
||||
reg [dut.AXI_DATA_WIDTH/8-1:0] s_axi_wstrb;
|
||||
reg s_axi_wlast;
|
||||
// AXI write response channel signals
|
||||
wire s_axi_bvalid;
|
||||
reg s_axi_bready;
|
||||
wire [dut.AXI_ID_WIDTH-1:0] s_axi_bid;
|
||||
wire [1:0] s_axi_bresp;
|
||||
// AXI read address channel signals
|
||||
reg s_axi_arvalid;
|
||||
wire s_axi_arready;
|
||||
reg [dut.AXI_ID_WIDTH-1:0] s_axi_arid;
|
||||
reg [dut.AXI_ADDR_WIDTH-1:0] s_axi_araddr;
|
||||
// AXI read data channel signals
|
||||
wire s_axi_rvalid; // rd rslt valid
|
||||
reg s_axi_rready; // rd rslt ready
|
||||
wire [dut.AXI_ID_WIDTH-1:0] s_axi_rid; // response id
|
||||
wire [dut.AXI_DATA_WIDTH-1:0] s_axi_rdata;// read data
|
||||
wire s_axi_rlast; // read last
|
||||
wire [1:0] s_axi_rresp; // read response
|
||||
|
||||
// DDR3 Pins
|
||||
wire o_ddr3_clk_p;
|
||||
wire o_ddr3_clk_n;
|
||||
wire o_ddr3_reset_n;
|
||||
wire o_ddr3_cke;
|
||||
wire o_ddr3_cs_n;
|
||||
wire o_ddr3_ras_n;
|
||||
wire o_ddr3_cas_n;
|
||||
wire o_ddr3_we_n;
|
||||
wire[dut.ROW_BITS-1:0] o_ddr3_addr;
|
||||
wire[dut.BA_BITS-1:0] o_ddr3_ba_addr;
|
||||
wire[(dut.DQ_BITS*dut.BYTE_LANES)-1:0] io_ddr3_dq;
|
||||
wire[dut.BYTE_LANES-1:0] io_ddr3_dqs, io_ddr3_dqs_n;
|
||||
wire[dut.BYTE_LANES-1:0] o_ddr3_dm;
|
||||
wire o_ddr3_odt;
|
||||
|
||||
localparam CONTROLLER_CLK_PERIOD = 10_000, //ps, period of clock input to this DDR3 controller module
|
||||
DDR3_CLK_PERIOD = 2500; //ps, period of clock input to DDR3 RAM device
|
||||
|
||||
|
||||
// Clocks and reset
|
||||
always #(CONTROLLER_CLK_PERIOD/2) i_controller_clk = !i_controller_clk;
|
||||
always #(DDR3_CLK_PERIOD/2) i_ddr3_clk = !i_ddr3_clk;
|
||||
always #2500 i_ref_clk = !i_ref_clk;
|
||||
initial begin //90 degree phase shifted ddr3_clk
|
||||
#(DDR3_CLK_PERIOD/4);
|
||||
while(1) begin
|
||||
#(DDR3_CLK_PERIOD/2) i_ddr3_clk_90 = !i_ddr3_clk_90;
|
||||
end
|
||||
end
|
||||
initial begin
|
||||
i_controller_clk = 1;
|
||||
i_ddr3_clk = 1;
|
||||
i_ref_clk = 1;
|
||||
i_ddr3_clk_90 = 1;
|
||||
i_rst_n = 0;
|
||||
#1_000_000;
|
||||
i_rst_n = 1;
|
||||
end
|
||||
|
||||
initial begin
|
||||
// initialize AXI
|
||||
s_axi_awvalid = 0;
|
||||
s_axi_awid = 0;
|
||||
s_axi_awaddr = 0;
|
||||
|
||||
s_axi_wvalid = 0;
|
||||
s_axi_wdata = 0;
|
||||
s_axi_wstrb = 0;
|
||||
s_axi_wlast = 0;
|
||||
|
||||
s_axi_bready = 0;
|
||||
|
||||
s_axi_arvalid = 0;
|
||||
s_axi_arid = 0;
|
||||
s_axi_araddr = 0;
|
||||
|
||||
s_axi_rready = 0;
|
||||
|
||||
//wait until done calibrate
|
||||
wait(dut.ddr3_top_inst.ddr3_controller_inst.state_calibrate == 23);
|
||||
|
||||
// write data to address 3 (0-15 = address 0, 16-31 = address 1, 32-47 = address 2)
|
||||
@(negedge i_controller_clk);
|
||||
s_axi_awvalid = 1;
|
||||
s_axi_awid = 0;
|
||||
s_axi_awaddr = 33;
|
||||
@(negedge i_controller_clk);
|
||||
// while(!s_axi_awready) begin
|
||||
// @(negedge i_controller_clk);
|
||||
// end
|
||||
s_axi_awvalid = 0;
|
||||
s_axi_awid = 0;
|
||||
s_axi_awaddr = 0;
|
||||
|
||||
s_axi_wvalid = 1;
|
||||
s_axi_wdata = 128'hAAAA_BBBB_CCCC_DDDD_EEEE_FFFF_0000_1111; // data 1
|
||||
s_axi_wstrb = -1;
|
||||
|
||||
@(negedge i_controller_clk);
|
||||
while(!s_axi_wready) begin
|
||||
@(negedge i_controller_clk);
|
||||
end
|
||||
s_axi_wdata = 128'h2222_3333_4444_5555_6666_7777_8888_9999; // data 2
|
||||
|
||||
@(negedge i_controller_clk);
|
||||
while(!s_axi_wready) begin
|
||||
@(negedge i_controller_clk);
|
||||
end
|
||||
s_axi_wdata = 100; // data 3
|
||||
|
||||
@(negedge i_controller_clk);
|
||||
while(!s_axi_wready) begin
|
||||
@(negedge i_controller_clk);
|
||||
end
|
||||
s_axi_wdata = 2000; // data 4
|
||||
s_axi_wlast = 1;
|
||||
|
||||
@(negedge i_controller_clk);
|
||||
while(!s_axi_wready) begin
|
||||
@(negedge i_controller_clk);
|
||||
end
|
||||
s_axi_wvalid = 0;
|
||||
s_axi_wdata = 0;
|
||||
s_axi_wstrb = 0;
|
||||
s_axi_wlast = 0;
|
||||
// DONE write data to address 3
|
||||
|
||||
// wait for write response
|
||||
wait(s_axi_bvalid);
|
||||
@(negedge i_controller_clk);
|
||||
s_axi_bready = 1;
|
||||
@(negedge i_controller_clk);
|
||||
s_axi_bready = 0;
|
||||
// done waiting for write response
|
||||
|
||||
#1000_000;
|
||||
// read data request from address 2 (0-15 = address 0, 16-31 = address 1, 32-47 = address 2)
|
||||
@(negedge i_controller_clk);
|
||||
s_axi_arvalid = 1;
|
||||
s_axi_arid = 2;
|
||||
s_axi_araddr = 46;
|
||||
@(negedge i_controller_clk);
|
||||
s_axi_arvalid = 0;
|
||||
s_axi_arid = 0;
|
||||
s_axi_araddr = 0;
|
||||
// done read data request from address 3
|
||||
|
||||
// wait for read data
|
||||
wait(s_axi_rvalid);
|
||||
@(negedge i_controller_clk);
|
||||
@(negedge i_controller_clk);
|
||||
@(negedge i_controller_clk);
|
||||
@(negedge i_controller_clk);
|
||||
s_axi_rready = 1;
|
||||
@(negedge i_controller_clk);
|
||||
@(negedge i_controller_clk);
|
||||
@(negedge i_controller_clk);
|
||||
@(negedge i_controller_clk);
|
||||
s_axi_rready = 0;
|
||||
#1000_000;
|
||||
$finish;
|
||||
|
||||
end
|
||||
ddr3_top_axi #(
|
||||
.CONTROLLER_CLK_PERIOD(10_000), //ps, clock period of the controller interface
|
||||
.DDR3_CLK_PERIOD(2_500), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
|
||||
.ROW_BITS(14), //width of row address
|
||||
.COL_BITS(10), //width of column address
|
||||
.BA_BITS(3), //width of bank address
|
||||
.BYTE_LANES(2), //number of byte lanes of DDR3 RAM
|
||||
.AXI_ID_WIDTH(4), // The AXI id width used for R&W, an int between 1-16
|
||||
.MICRON_SIM(1), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
|
||||
.ODELAY_SUPPORTED(0), //set to 1 when ODELAYE2 is supported
|
||||
.SECOND_WISHBONE(0) //set to 1 if 2nd wishbone for debugging is needed
|
||||
) dut
|
||||
(
|
||||
.i_controller_clk(i_controller_clk),
|
||||
.i_ddr3_clk(i_ddr3_clk),
|
||||
.i_ref_clk(i_ref_clk), //i_controller_clk = CONTROLLER_CLK_PERIOD, i_ddr3_clk = DDR3_CLK_PERIOD, i_ref_clk = 200MHz
|
||||
.i_ddr3_clk_90(i_ddr3_clk_90), //required only when ODELAY_SUPPORTED is zero
|
||||
.i_rst_n(i_rst_n),
|
||||
//
|
||||
// AXI Interface
|
||||
// AXI write address channel signals
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(3), // 4 transfers in a transaction
|
||||
.s_axi_awsize($clog2(128)),
|
||||
.s_axi_awburst(1), //incrementing burst address
|
||||
.s_axi_awlock(0),
|
||||
.s_axi_awcache(0),
|
||||
.s_axi_awprot(0),
|
||||
.s_axi_awqos(0),
|
||||
// AXI write data channel signals
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
// AXI write response channel signals
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
// AXI read address channel signals
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(3), // only 1 transfer in a transaction
|
||||
.s_axi_arsize($clog2(128)),
|
||||
.s_axi_arburst(1), //incrementing burst address
|
||||
.s_axi_arlock(0),
|
||||
.s_axi_arcache(0),
|
||||
.s_axi_arprot(0),
|
||||
.s_axi_arqos(0),
|
||||
// AXI read data channel signals
|
||||
.s_axi_rvalid(s_axi_rvalid), // rd rslt valid
|
||||
.s_axi_rready(s_axi_rready), // rd rslt ready
|
||||
.s_axi_rid(s_axi_rid), // response id
|
||||
.s_axi_rdata(s_axi_rdata),// read data
|
||||
.s_axi_rlast(s_axi_rlast), // read last
|
||||
.s_axi_rresp(s_axi_rresp), // read response
|
||||
//
|
||||
// DDR3 I/O Interface
|
||||
.o_ddr3_clk_p(o_ddr3_clk_p),
|
||||
.o_ddr3_clk_n(o_ddr3_clk_n),
|
||||
.o_ddr3_reset_n(o_ddr3_reset_n),
|
||||
.o_ddr3_cke(o_ddr3_cke),
|
||||
.o_ddr3_cs_n(o_ddr3_cs_n),
|
||||
.o_ddr3_ras_n(o_ddr3_ras_n),
|
||||
.o_ddr3_cas_n(o_ddr3_cas_n),
|
||||
.o_ddr3_we_n(o_ddr3_we_n),
|
||||
.o_ddr3_addr(o_ddr3_addr),
|
||||
.o_ddr3_ba_addr(o_ddr3_ba_addr),
|
||||
.io_ddr3_dq(io_ddr3_dq),
|
||||
.io_ddr3_dqs(io_ddr3_dqs),
|
||||
.io_ddr3_dqs_n(io_ddr3_dqs_n),
|
||||
.o_ddr3_dm(o_ddr3_dm),
|
||||
.o_ddr3_odt(o_ddr3_odt)
|
||||
//
|
||||
);
|
||||
|
||||
ddr3 ddr3_0(
|
||||
.rst_n(o_ddr3_reset_n),
|
||||
.ck(o_ddr3_clk_p),
|
||||
.ck_n(o_ddr3_clk_n),
|
||||
.cke(o_ddr3_cke),
|
||||
.cs_n(o_ddr3_cs_n),
|
||||
.ras_n(o_ddr3_ras_n),
|
||||
.cas_n(o_ddr3_cas_n),
|
||||
.we_n(o_ddr3_we_n),
|
||||
.dm_tdqs(o_ddr3_dm),
|
||||
.ba(o_ddr3_ba_addr),
|
||||
.addr({0,o_ddr3_addr}),
|
||||
.dq(io_ddr3_dq),
|
||||
.dqs(io_ddr3_dqs),
|
||||
.dqs_n(io_ddr3_dqs_n),
|
||||
.tdqs_n(),
|
||||
.odt(o_ddr3_odt)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue