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UberDDR3
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allow tdqs off and use dm

This commit is contained in:
AngeloJacobo 2023-08-15 21:17:13 +08:00
parent f296d08c6b
commit a8bf429bc8
1 changed files with 2 additions and 2 deletions
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4
testbench/ddr3.v
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@ -96,7 +96,7 @@
`timescale 1ps / 1ps
`define den8192Mb
`define sg125
`define x8
`define x16
`default_nettype wire
module ddr3 (
@ -157,7 +157,7 @@ module ddr3 (
input ras_n;
input cas_n;
input we_n;
inout [DM_BITS-1:0] dm_tdqs;
input [DM_BITS-1:0] dm_tdqs;
input [BA_BITS-1:0] ba;
input [ROW_BITS-1:0] addr;
inout [DQ_BITS-1:0] dq;