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UberDDR3
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add test for ECC

This commit is contained in:
AngeloJacobo 2024-06-29 19:36:35 +08:00
parent c81c51c9f4
commit a458a06de0
1 changed files with 47 additions and 13 deletions
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60
testbench/ddr3_dimm_micron_sim.sv
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@ -57,14 +57,14 @@ module ddr3_dimm_micron_sim;
`ifdef EIGHT_LANES_x8
localparam BYTE_LANES = 8,
ODELAY_SUPPORTED = 1;;
ODELAY_SUPPORTED = 1;
`endif
localparam CONTROLLER_CLK_PERIOD = 10_000, //ps, period of clock input to this DDR3 controller module
DDR3_CLK_PERIOD = 2500, //ps, period of clock input to DDR3 RAM device
AUX_WIDTH = 16, // AUX lines
ECC_ENABLE = 2; // ECC enable
ECC_ENABLE = 1; // ECC enable
reg i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90;
reg i_rst_n;
@ -260,16 +260,38 @@ ddr3_top #(
.dq(dq)
);
`endif
reg[ddr3_top.ddr3_controller_inst.wb_data_bits-1:0] orig_phy_data;
// Force change for ECC tests
always @(ddr3_top.ddr3_controller_inst.stage2_data[ddr3_top.ddr3_controller_inst.STAGE2_DATA_DEPTH-1]) begin
if(ddr3_top.ddr3_controller_inst.initial_calibration_done) begin
force ddr3_top.ddr3_controller_inst.o_phy_data = {ddr3_top.ddr3_controller_inst.stage2_data[ddr3_top.ddr3_controller_inst.STAGE2_DATA_DEPTH-1][ddr3_top.ddr3_controller_inst.wb_data_bits - 1:1], 1'b0};
generate
if(ECC_ENABLE == 2) begin
always @(ddr3_top.ddr3_controller_inst.stage2_data[ddr3_top.ddr3_controller_inst.STAGE2_DATA_DEPTH-1]) begin
if(ddr3_top.ddr3_controller_inst.initial_calibration_done) begin
orig_phy_data = ddr3_top.ddr3_controller_inst.stage2_data[ddr3_top.ddr3_controller_inst.STAGE2_DATA_DEPTH-1];
for(index = 0; index < 8; index = index + 1) begin
orig_phy_data[8*BYTE_LANES*index] = 1'b0;
end
force ddr3_top.ddr3_controller_inst.o_phy_data = orig_phy_data;
end
else begin
release ddr3_top.ddr3_controller_inst.o_phy_data;
end
end
end
else begin
release ddr3_top.ddr3_controller_inst.o_phy_data;
else if(ECC_ENABLE == 1) begin
always @(ddr3_top.ddr3_controller_inst.stage2_data[ddr3_top.ddr3_controller_inst.STAGE2_DATA_DEPTH-1]) begin
if(ddr3_top.ddr3_controller_inst.initial_calibration_done) begin
orig_phy_data = ddr3_top.ddr3_controller_inst.stage2_data[ddr3_top.ddr3_controller_inst.STAGE2_DATA_DEPTH-1];
for(index = 0; index < 8; index = index + 1) begin
orig_phy_data[8*BYTE_LANES*index] = 1'b0;
end
force ddr3_top.ddr3_controller_inst.o_phy_data = orig_phy_data;
end
else begin
release ddr3_top.ddr3_controller_inst.o_phy_data;
end
end
end
end
endgenerate
reg[511:0] write_data = 0, expected_read_data = 0;
integer address = 0, read_address = 0, address_inner = 0;
integer start_address = 0, start_read_address;
@ -630,9 +652,12 @@ ddr3_top #(
for (index = 0; index < $bits(ddr3_top.i_wb_data)/32; index = index + 1) begin
expected_read_data[index*32 +: 32] = $random(read_address + index); //each $random only has 32 bits
end
if (ECC_ENABLE == 1 || ECC_ENABLE == 2) begin
if (ECC_ENABLE == 2) begin
expected_read_data[511 : ddr3_top.ddr3_controller_inst.ECC_INFORMATION_BITS] = 0;
end
else if (ECC_ENABLE == 1) begin
expected_read_data[511 : ddr3_top.ddr3_controller_inst.ECC_INFORMATION_BITS*8] = 0;
end
if(expected_read_data == o_wb_data) begin
//$display("SUCCESSFUL: Address = %0d, expected data = %h, read data = %h", (read_address/($bits(ddr3_top.i_wb_data)/32)), expected_read_data, o_wb_data);
number_of_successful = number_of_successful + 1;
@ -653,9 +678,12 @@ ddr3_top #(
for (index = 0; index < $bits(ddr3_top.i_wb_data)/32; index = index + 1) begin
expected_read_data[index*32 +: 32] = $random(read_address + index); //each $random only has 32 bits
end
if (ECC_ENABLE == 1 || ECC_ENABLE == 2) begin
if (ECC_ENABLE == 2) begin
expected_read_data[511 : ddr3_top.ddr3_controller_inst.ECC_INFORMATION_BITS] = 0;
end
else if (ECC_ENABLE == 1) begin
expected_read_data[511 : ddr3_top.ddr3_controller_inst.ECC_INFORMATION_BITS*8] = 0;
end
if(expected_read_data == o_wb_data) begin
//$display("SUCCESSFUL: Address = %0d, expected data = %h, read data = %h", (read_address/($bits(ddr3_top.i_wb_data)/32)), expected_read_data, o_wb_data);
number_of_successful = number_of_successful + 1;
@ -676,9 +704,12 @@ ddr3_top #(
for (index = 0; index < $bits(ddr3_top.i_wb_data)/32; index = index + 1) begin
expected_read_data[index*32 +: 32] = $random(read_address + index); //each $random only has 32 bits
end
if (ECC_ENABLE == 1 || ECC_ENABLE == 2) begin
if (ECC_ENABLE == 2) begin
expected_read_data[511 : ddr3_top.ddr3_controller_inst.ECC_INFORMATION_BITS] = 0;
end
else if (ECC_ENABLE == 1) begin
expected_read_data[511 : ddr3_top.ddr3_controller_inst.ECC_INFORMATION_BITS*8] = 0;
end
if(expected_read_data == o_wb_data) begin
//$display("SUCCESSFUL: Address = %0d, expected data = %h, read data = %h", (read_address/($bits(ddr3_top.i_wb_data)/32)), expected_read_data, o_wb_data);
number_of_successful = number_of_successful + 1;
@ -699,9 +730,12 @@ ddr3_top #(
for (index = 0; index < $bits(ddr3_top.i_wb_data)/32; index = index + 1) begin
expected_read_data[index*32 +: 32] = $random(read_address + index); //each $random only has 32 bits
end
if (ECC_ENABLE == 1 || ECC_ENABLE == 2) begin
if (ECC_ENABLE == 2) begin
expected_read_data[511 : ddr3_top.ddr3_controller_inst.ECC_INFORMATION_BITS] = 0;
end
else if (ECC_ENABLE == 1) begin
expected_read_data[511 : ddr3_top.ddr3_controller_inst.ECC_INFORMATION_BITS*8] = 0;
end
if(expected_read_data == o_wb_data) begin
//$display("SUCCESSFUL: Address = %0d, expected data = %h, read data = %h", (read_address/($bits(ddr3_top.i_wb_data)/32)), expected_read_data, o_wb_data);
number_of_successful = number_of_successful + 1;