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added uart submodule

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AngeloJacobo 2023-08-17 11:36:15 +08:00
parent 36c93689e5
commit c9b19ac887
2 changed files with 4 additions and 0 deletions
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[submodule "testbench/ARTY_S7/verilog-uart"]
path = testbench/ARTY_S7/verilog-uart
url = https://github.com/alexforencich/verilog-uart.git

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testbench/ARTY_S7/verilog-uart Submodule

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Subproject commit 1363dc76788527bf6017dd5294593f42162133e2