AngeloJacobo
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db8e0fd400
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test GoCD CI with this new commit
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2025-05-28 19:44:40 +08:00 |
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AngeloJacobo
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426a4e626b
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revert back current_design (test gocd)
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2025-05-25 13:15:13 +08:00 |
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AngeloJacobo
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e2b0829b74
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removed iodelay group string (test gocd)
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2025-05-25 13:14:43 +08:00 |
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AngeloJacobo
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76815bac35
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remove current_design on xdc (not supported in openxc7)
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2025-05-25 12:54:02 +08:00 |
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AngeloJacobo
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da4ffebe9b
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update vivado sim log files
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2025-05-25 09:03:28 +08:00 |
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AngeloJacobo
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e5bd0d74c3
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use SIM_MODEL directive to use models during vivado simulation
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2025-05-25 09:03:16 +08:00 |
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AngeloJacobo
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a33560122c
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added icarus simulation scripts (PASSING!)
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2025-05-24 17:35:39 +08:00 |
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AngeloJacobo
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cb5f78b057
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modified vivado simulation files
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2025-05-24 17:33:49 +08:00 |
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AngeloJacobo
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972506bb4b
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moved verilog models to model/
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2025-05-24 17:31:55 +08:00 |
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AngeloJacobo
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8fbb6387ab
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removed UART in example demo for arty s7 to pass openxc7 timing
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2025-05-24 17:31:13 +08:00 |
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AngeloJacobo
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f0b4a15b7c
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icarus verilog simulation now working!
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2025-05-18 17:08:38 +08:00 |
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AngeloJacobo
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4be9a30ff8
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added files needed for icarus simulation (not yet working)
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2025-05-18 15:24:10 +08:00 |
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AngeloJacobo
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157cca28d8
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fixed late_dq logic
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2025-05-12 18:27:57 +08:00 |
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AngeloJacobo
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90647a70e0
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resolved (again) the verilator lint
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2025-05-12 16:28:07 +08:00 |
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AngeloJacobo
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5f8f5974b4
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added vivado on makefile (make vivado)
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2025-05-12 16:02:38 +08:00 |
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AngeloJacobo
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fe8563ed65
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update all simulation log files
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2025-05-12 11:05:36 +08:00 |
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AngeloJacobo
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9fd104b566
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updated example demo bitstream files
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2025-05-11 20:11:05 +08:00 |
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AngeloJacobo
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50c0a6488d
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verilator now passing lint even with older verilator version
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2025-05-11 20:02:13 +08:00 |
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AngeloJacobo
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5b0c48ca0a
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fixed bug on vivado IP (convert string to long for SELF_REFRESH)
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2025-04-19 13:59:30 +08:00 |
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AngeloJacobo
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c7ec0a54fc
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set default BIST_MODE to 1 for shorter bring up
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2025-04-19 13:37:58 +08:00 |
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AngeloJacobo
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73431cdd82
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added simulation for DLL Off (low frequency ddr3 clk)
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2025-04-19 13:32:07 +08:00 |
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AngeloJacobo
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baaa2a2482
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added example demo for orangecrab ecp5
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2025-04-19 13:30:40 +08:00 |
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AngeloJacobo
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b990372663
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added support for DLL_OFF and Lattice ECP5 PHY
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2025-04-19 13:24:20 +08:00 |
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AngeloJacobo
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08ead41fd6
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updated simulation
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2025-04-19 10:07:51 +08:00 |
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Angelo Jacobo
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a34a5369ec
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Merge pull request #26 from AngeloJacobo/openxc7_run
Now tested working on OpenXC7 toolchain
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2025-03-21 20:33:19 +08:00 |
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Angelo Jacobo
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8c088fee72
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Merge branch 'main' into openxc7_run
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2025-03-21 20:32:51 +08:00 |
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AngeloJacobo
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b02e66b7d8
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revert changes in shiftin and iodelay_group string name since openxc7 now works on them
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2025-03-16 12:29:48 +08:00 |
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AngeloJacobo
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0175db1ca6
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openFPGAloader now working on qmtech_wukong
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2025-03-14 16:12:25 +08:00 |
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AngeloJacobo
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58f887ced3
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openfpgaloader now works on qmtech_kintex7
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2025-03-14 16:03:18 +08:00 |
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AngeloJacobo
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5ab1ac5d42
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add UART to ax7325b board, make openFPGAloader works on ax7325b board
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2025-03-14 15:23:34 +08:00 |
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AngeloJacobo
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75e42476f5
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openfpgaloader now working on alinx ax7103b board
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2025-03-14 14:34:25 +08:00 |
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AngeloJacobo
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117a9c5837
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update enclustra demo project
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2025-03-14 13:56:24 +08:00 |
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AngeloJacobo
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d787c77116
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pass simulation
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2025-03-13 18:31:23 +08:00 |
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AngeloJacobo
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47067f6903
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remove xadc define and uncomment INTERNAL_VREF to make this work in openxc7 (openxc7 still fails due to shiftout ports)
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2025-03-09 10:57:43 +08:00 |
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AngeloJacobo
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89568b127c
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add demo project for qmtech kintex-7 board
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2025-03-09 10:41:33 +08:00 |
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Angelo Jacobo
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42b42023dd
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Update README.md
updated link for micron model file
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2025-03-09 10:13:07 +08:00 |
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AngeloJacobo
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7f801b1f1d
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add uart_tx to top
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2025-03-02 19:05:30 +08:00 |
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AngeloJacobo
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c0bc4ca48a
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removed extra semicolon
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2025-03-02 18:46:07 +08:00 |
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AngeloJacobo
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4ce06f5fd8
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all example demos passing openxc7 run!
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2025-03-02 18:42:49 +08:00 |
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AngeloJacobo
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e8444fb379
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fix flagged errors from openxc7 (shiftin grounded, iodelay_group string)
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2025-03-02 18:40:18 +08:00 |
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AngeloJacobo
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0c484d54f6
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fix flagged errors from openxc7
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2025-03-02 14:34:59 +08:00 |
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AngeloJacobo
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94b4e0866b
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added UART for debugging, DQ now support 1 cycle late
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2025-03-02 14:15:44 +08:00 |
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AngeloJacobo
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5c52351bce
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uncommented default_nettype
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2025-03-01 19:32:35 +08:00 |
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AngeloJacobo
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e19c6023c4
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remove wb2 related logic when SECOND_WISHBONE == 0 to pass DDR3-1600 timing
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2025-03-01 15:51:48 +08:00 |
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AngeloJacobo
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4a71002cf8
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ignore new fiels due to new verilator, run_compile can now run lint separately
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2025-03-01 14:42:05 +08:00 |
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AngeloJacobo
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99eaa7d103
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added IODELAY_GROUP for ODELAY,IDELAY,and IDELAYCTRL
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2025-03-01 14:41:00 +08:00 |
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AngeloJacobo
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74f68760a4
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removed mark_debug
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2025-03-01 14:40:21 +08:00 |
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AngeloJacobo
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f10fc7d10b
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vivado simulation files directory are now relative, can now run sim anywhere
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2025-03-01 14:39:54 +08:00 |
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AngeloJacobo
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af48f1fa08
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solve timing slack due to 64-bit counters
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2025-02-27 20:28:55 +08:00 |
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Angelo Jacobo
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c0e3f32bfb
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Merge pull request #22 from AngeloJacobo/higher_speed_feature
Pass simulation and hardware test for DDR3-1333 and DDR3-1600!
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2025-02-22 11:32:19 +08:00 |