Merge pull request #270 from hpretl/stable

Switching from `volare` to `ciel` and bumping the version number

.github/workflows/regress.yml

@@ -12,6 +12,9 @@ jobs:
     steps:
       - name: Checkout code
         uses: actions/checkout@v1
+      - name: Install dependencies
+        run: |
+         pip3 install -r requirements.txt
       - name: Library build
         run: |
          rm -rf ~/.local/lib/python3.8/site-packages/openram*
@@ -24,8 +27,9 @@ jobs:
          export OPENRAM_HOME="${{ github.workspace }}/compiler"
          export OPENRAM_TECH="${{ github.workspace }}/technology"
          export PDK_ROOT="${{ github.workspace }}/pdk"
-         make pdk
-         make install
+         # Add make targets to install PDKs of all technologies that need it
+         make sky130-pdk
+         make sky130-install
       - name: Regress
         run: |
          export OPENRAM_HOME="${{ github.workspace }}/compiler"
@@ -43,7 +47,7 @@ jobs:
          make -k -j 48
       - name: Archive
         if: ${{ failure() }}
-        uses: actions/upload-artifact@v2
+        uses: actions/upload-artifact@v4
         with:
           name: Regress Archives
           path: ${{ github.workspace }}/compiler/tests/results/*

.gitignore

@@ -13,14 +13,20 @@ outputs
 technology/freepdk45/ncsu_basekit
 technology/sky130/*_lib
 technology/sky130/tech/.magicrc
+technology/gf180mcu/*_lib
 .idea
 compiler/tests/results/
 open_pdks/
 dist/
 openram.egg-info/
 miniconda/
-sky130A/
-sky130B/
+sky130A
+sky130B
+gf180mcuA
+gf180mcuB
+gf180mcuC
+gf180mcuD
 skywater-pdk/
 sky130_fd_bd_sram/
 docker/openram-ubuntu.log
+ciel/

Makefile

@@ -15,18 +15,25 @@ SRAM_LIB_GIT_REPO ?= https://github.com/vlsida/sky130_fd_bd_sram.git
 #SRAM_LIB_GIT_REPO ?= https://github.com/google/skywater-pdk-libs-sky130_fd_bd_sram.git
 SRAM_LIB_GIT_COMMIT ?= dd64256961317205343a3fd446908b42bafba388
 
-# Open PDKs
-OPEN_PDKS_DIR ?= $(PDK_ROOT)/open_pdks
-OPEN_PDKS_GIT_REPO ?= https://github.com/RTimothyEdwards/open_pdks.git
-OPEN_PDKS_GIT_COMMIT ?= 1.0.311
-#OPEN_PDKS_GIT_COMMIT ?= 7ea416610339d3c29af9d0d748ceadd3fd368608
 SKY130_PDK ?= $(PDK_ROOT)/sky130A
+GF180_PDK ?= $(PDK_ROOT)/gf180mcuD
+
+# Ciel SKY130 PDK
+SKY130_CIEL = e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066 # 2022.07.29
+
+# Ciel GF180 PDK
+GF180_CIEL = cd1748bb197f9b7af62a54507de6624e30363943 # 2023.12.04
 
 # Skywater PDK
 SKY130_PDKS_DIR ?= $(PDK_ROOT)/skywater-pdk
 SKY130_PDKS_GIT_REPO ?= https://github.com/google/skywater-pdk.git
 SKY130_PDKS_GIT_COMMIT ?= f70d8ca46961ff92719d8870a18a076370b85f6c
 
+# GF180 PDK
+GF180_PDKS_DIR ?= $(PDK_ROOT)/gf180mcu-pdk
+GF180_PDKS_GIT_REPO ?= https://github.com/google/gf180mcu-pdk.git
+GF180_PDKS_GIT_COMMIT ?= main
+
 # Create lists of all the files to copy/link
 GDS_FILES := $(sort $(wildcard $(SRAM_LIB_DIR)/cells/*/*.gds))
 GDS_FILES := $(GDS_FILES) $(PDK_ROOT)/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlxtn/sky130_fd_sc_hd__dlxtn_1.gds
@@ -47,12 +54,11 @@ MAGICRC_FILE := $(SKY130_PDK)/libs.tech/magic/sky130A.magicrc
 
 ALL_FILES := $(ALL_SPICE_FILES) $(GDS_FILES) $(MAG_FILES) $(MAGLEF_FILES)
 
-
 INSTALL_BASE_DIRS := gds_lib mag_lib sp_lib lvs_lib calibre_lvs_lib klayout_lvs_lib maglef_lib
 INSTALL_BASE := $(OPENRAM_HOME)/../technology/sky130
 INSTALL_DIRS := $(addprefix $(INSTALL_BASE)/,$(INSTALL_BASE_DIRS))
 
-# If conda is installed, we will use Magic from there
+# If conda is installed, we will use ciel from there
 CONDA_DIR := $(wildcard $(TOP_DIR)/miniconda)
 
 check-pdk-root:
@@ -67,31 +73,14 @@ $(SKY130_PDKS_DIR): check-pdk-root
 	@git -C $(SKY130_PDKS_DIR) checkout $(SKY130_PDKS_GIT_COMMIT) && \
 		git -C $(SKY130_PDKS_DIR) submodule update --init libraries/sky130_fd_pr/latest libraries/sky130_fd_sc_hd/latest
 
-$(OPEN_PDKS_DIR): $(SKY130_PDKS_DIR)
-	@echo "Cloning open_pdks..."
-	@[ -d $(OPEN_PDKS_DIR) ] || \
-		git clone $(OPEN_PDKS_GIT_REPO) $(OPEN_PDKS_DIR)
-	@git -C $(OPEN_PDKS_DIR) checkout $(OPEN_PDKS_GIT_COMMIT)
-
-$(SKY130_PDK): $(OPEN_PDKS_DIR) $(SKY130_PDKS_DIR)
-	@echo "Installing open_pdks..."
-ifeq ($(CONDA_DIR),"")
-	@cd $(PDK_ROOT)/open_pdks && \
-		./configure --enable-sky130-pdk=$(PDK_ROOT)/skywater-pdk/libraries --with-sky130-local-path=$(PDK_ROOT) && \
-		cd sky130 && \
-		make veryclean && \
-		make && \
-		make SHARED_PDKS_PATH=$(PDK_ROOT) install
-else
-	@source $(TOP_DIR)/miniconda/bin/activate && \
-		cd $(PDK_ROOT)/open_pdks && \
-		./configure --enable-sky130-pdk=$(PDK_ROOT)/skywater-pdk/libraries --with-sky130-local-path=$(PDK_ROOT) && \
-		cd sky130 && \
-		make veryclean && \
-		make && \
-		make SHARED_PDKS_PATH=$(PDK_ROOT) install && \
-		conda deactivate
-endif
+$(GF180_PDKS_DIR): check-pdk-root
+	@echo "Cloning gf PDK..."
+	@[ -d $(PDK_ROOT)/gf180mcu-pdk ] || \
+		git clone https://github.com/google/gf180mcu-pdk.git $(PDK_ROOT)/gf180mcu-pdk
+	@cd $(GF180_PDKS_DIR) && \
+		git checkout main && git pull && \
+		git checkout -qf $(GF180_PDKS_GIT_COMMIT) && \
+		git submodule update --init libraries/gf180mcu_fd_pr/latest libraries/gf180mcu_fd_sc_mcu7t5v0/latest libraries/gf180mcu_fd_sc_mcu9t5v0/latest
 
 $(SRAM_LIB_DIR): check-pdk-root
 	@echo "Cloning SRAM library..."
@@ -100,21 +89,39 @@ $(SRAM_LIB_DIR): check-pdk-root
 	@git -C $(SRAM_LIB_DIR) fetch
 	@git -C $(SRAM_LIB_DIR) checkout $(SRAM_LIB_GIT_COMMIT)
 
-install: $(SRAM_LIB_DIR)
+sky130-install: $(SRAM_LIB_DIR)
 	@[ -d $(PDK_ROOT)/sky130A ] || \
-		(echo "Warning: $(PDK_ROOT)/sky130A not found!! Run make pdk first." &&  false)
+		(echo "Warning: $(PDK_ROOT)/sky130A not found!! Run make sky130-pdk first." &&  false)
 	@[ -d $(PDK_ROOT)/skywater-pdk ] || \
-		(echo "Warning: $(PDK_ROOT)/skywater-pdk not found!! Run make pdk first." && false)
+		(echo "Warning: $(PDK_ROOT)/skywater-pdk not found!! Run make sky130-pdk first." && false)
 	@echo "Installing sky130 SRAM PDK..."
 	@echo "PDK_ROOT='$(PDK_ROOT)'"
 	@echo "SRAM_LIB_DIR='$(SRAM_LIB_DIR)'"
 	@echo "SKY130_PDK='$(SKY130_PDK)'"
 	@make $(INSTALL_DIRS)
-.PHONY: install
+.PHONY: sky130-install
 
-pdk: $(SKY130_PDK)
-	@true
-.PHONY: pdk
+sky130-pdk: $(SKY130_PDKS_DIR)
+	@echo "Installing SKY130 via ciel..."
+ifeq ($(CONDA_DIR),)
+	ciel enable --pdk sky130 $(SKY130_CIEL)
+else
+	source $(TOP_DIR)/miniconda/bin/activate && \
+		ciel enable --pdk sky130 $(SKY130_CIEL) && \
+		conda deactivate
+endif
+.PHONY: sky130-pdk
+
+gf180mcu-pdk:
+	@echo "Installing GF180 via ciel..."
+ifeq ($(CONDA_DIR),)
+	ciel enable --pdk gf180mcu $(GF180_CIEL)
+else
+	source $(TOP_DIR)/miniconda/bin/activate && \
+		ciel enable --pdk gf180mcu $(GF180_CIEL) && \
+		conda deactivate
+endif
+.PHONY: gf180mcu-pdk
 
 $(INSTALL_BASE)/gds_lib: $(GDS_FILES)
 	@echo

README.md

@@ -42,10 +42,6 @@ updating.
 # Further Help
 
 + [Documentation][documentation]
-+ [OpenRAM Slack Workspace][Slack]
-+ [OpenRAM Users Group][user-group] ([subscribe here][user-group-subscribe])
-+ [OpenRAM Developers Group][dev-group] ([subscribe here][dev-group-subscribe])
-
 
 
 # License
@@ -66,18 +62,18 @@ OpenRAM is licensed under the [BSD 3-Clause License](./LICENSE).
 + [H. Nichols, "Statistical Modeling of SRAMs," M.S. Thesis, UCSC, 2022.](https://escholarship.org/content/qt7vx9n089/qt7vx9n089_noSplash_cfc4ba479d8eb1b6ec25d7c92357bc18.pdf?t=ra9wzr)
 
 
- 
+
 # Contributors & Acknowledgment
 
 - [Matthew Guthaus] from [VLSIDA] created the OpenRAM project and is the lead architect.
 - [James Stine] from [VLSIARCH] co-founded the project.
-- Many students: Hunter Nichols, Michael Grimes, Jennifer Sowash, Yusu Wang, Joey Kunzler, Jesse Cirimelli-Low, Samira Ataei, Bin Wu, Brian Chen, Jeff Butera
+- Many students: Hunter Nichols, Michael Grimes, Jennifer Sowash, Yusu Wang, Joey Kunzler, Jesse Cirimelli-Low, Samira Ataei, Bin Wu, Brian Chen, Jeff Butera, Sage Walker
 
 If I forgot to add you, please let me know!
 
 
 
-[Matthew Guthaus]:       https://users.soe.ucsc.edu/~mrg
+[Matthew Guthaus]:       https://vlsida.github.io
 [James Stine]:           https://ece.okstate.edu/content/stine-james-e-jr-phd
 [VLSIDA]:                https://vlsida.soe.ucsc.edu
 [VLSIARCH]:              https://vlsiarch.ecen.okstate.edu/
@@ -88,10 +84,6 @@ If I forgot to add you, please let me know!
 [Github project]:        https://github.com/VLSIDA/OpenRAM
 
 [documentation]:         docs/source/index.md
-[dev-group]:             mailto:openram-dev-group@ucsc.edu
-[user-group]:            mailto:openram-user-group@ucsc.edu
-[dev-group-subscribe]:   mailto:openram-dev-group+subscribe@ucsc.edu
-[user-group-subscribe]:  mailto:openram-user-group+subscribe@ucsc.edu
 
 [Klayout]:               https://www.klayout.de/
 [Magic]:                 http://opencircuitdesign.com/magic/
@@ -105,6 +97,5 @@ If I forgot to add you, please let me know!
 [SCMOS]:                 https://www.mosis.com/files/scmos/scmos.pdf
 [Sky130]:                https://github.com/google/skywater-pdk-libs-sky130_fd_bd_sram.git
 
-[Slack]:                 https://join.slack.com/t/openram/shared_invite/zt-onim74ue-zlttW5XI30xvdBlJGJF6JA
 
 

VERSION

@@ -1 +1 @@
-1.2.41
+1.2.49

__init__.py

@@ -1,11 +1,12 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
 import os
+import sys
 
 
 # Attempt to add the source code to the PYTHONPATH here before running globals.init_openram()

common.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 """

compiler/base/__init__.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .channel_route import *

compiler/base/channel_route.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/contact.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -10,7 +10,7 @@ from openram.tech import drc, layer, preferred_directions
 from openram.tech import layer as tech_layers
 from .hierarchy_design import hierarchy_design
 from .vector import vector
-
+from .utils import ceil
 
 class contact(hierarchy_design):
     """
@@ -41,7 +41,7 @@ class contact(hierarchy_design):
             self.add_comment("implant type: {}\n".format(implant_type))
             self.add_comment("well_type: {}\n".format(well_type))
 
-        self.is_well_contact = implant_type == well_type
+        self.is_well_contact = (implant_type == well_type) and implant_type is not None
 
         # If we have a special tap layer, use it
         self.layer_stack = layer_stack
@@ -125,6 +125,8 @@ class contact(hierarchy_design):
 
         self.first_layer_minwidth = drc("minwidth_{0}".format(self.first_layer_name))
         self.first_layer_enclosure = drc("{0}_enclose_{1}".format(self.first_layer_name, self.via_layer_name))
+        self.first_layer_minarea = drc("minarea_{0}".format(self.first_layer_name))
+
         # If there's a different rule for active
         # FIXME: Make this more elegant
         if self.is_well_contact and self.first_layer_name == "active" and "tap_extend_contact" in drc.keys():
@@ -135,7 +137,7 @@ class contact(hierarchy_design):
         self.second_layer_minwidth = drc("minwidth_{0}".format(self.second_layer_name))
         self.second_layer_enclosure = drc("{0}_enclose_{1}".format(self.second_layer_name, self.via_layer_name))
         self.second_layer_extend = drc("{0}_extend_{1}".format(self.second_layer_name, self.via_layer_name))
-
+        self.second_layer_minarea = drc("minarea_{0}".format(self.second_layer_name))
         # In some technologies, the minimum width may be larger
         # than the overlap requirement around the via, so
         # check this for each dimension.
@@ -143,7 +145,7 @@ class contact(hierarchy_design):
             self.first_layer_horizontal_enclosure = max(self.first_layer_enclosure,
                                                         (self.first_layer_minwidth - self.contact_array_width) / 2)
             self.first_layer_vertical_enclosure = max(self.first_layer_extend,
-                                                      (self.first_layer_minwidth - self.contact_array_height) / 2)
+                                                     (self.first_layer_minwidth - self.contact_array_height) / 2)
         elif self.directions[0] == "H":
             self.first_layer_horizontal_enclosure = max(self.first_layer_extend,
                                                         (self.first_layer_minwidth - self.contact_array_width) / 2)
@@ -166,7 +168,7 @@ class contact(hierarchy_design):
             self.second_layer_vertical_enclosure = max(self.second_layer_enclosure,
                                                        (self.second_layer_minwidth - self.contact_array_width) / 2)
         else:
-            debug.error("Invalid secon layer direction: ".format(self.directions[1]), -1)
+            debug.error("Invalid second layer direction: ".format(self.directions[1]), -1)
 
     def create_contact_array(self):
         """ Create the contact array at the origin"""
@@ -221,6 +223,18 @@ class contact(hierarchy_design):
             first_layer_name = "tap"
         else:
             first_layer_name = self.first_layer_name
+
+        area = self.first_layer_width * self.first_layer_height
+        if area < self.first_layer_minarea and self.is_well_contact:
+            if self.directions[0] == "V":
+                area_extend = (self.first_layer_minarea / self.first_layer_width) - self.first_layer_height
+                self.first_layer_height = ceil(self.first_layer_height + area_extend)
+                self.first_layer_position = self.first_layer_position - vector(0, area_extend / 2)
+            elif self.directions[0] == "H":
+                area_extend = (self.first_layer_minarea / self.first_layer_height) - self.first_layer_width
+                self.first_layer_width = ceil(self.first_layer_height + area_extend)
+                self.first_layer_position = self.first_layer_position - vector(area_extend / 2, 0)
+
         self.add_rect(layer=first_layer_name,
                       offset=self.first_layer_position,
                       width=self.first_layer_width,
@@ -236,6 +250,7 @@ class contact(hierarchy_design):
                                       self.second_layer_minwidth)
         self.second_layer_height = max(self.contact_array_height + 2 * self.second_layer_vertical_enclosure,
                                        self.second_layer_minwidth)
+
         self.add_rect(layer=self.second_layer_name,
                       offset=self.second_layer_position,
                       width=self.second_layer_width,

compiler/base/delay_data.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/design.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/errors.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 

compiler/base/geometry.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/hierarchy_design.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/hierarchy_layout.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -22,7 +22,7 @@ from openram.sram_factory import factory
 from openram import OPTS
 from .vector import vector
 from .pin_layout import pin_layout
-from .utils import round_to_grid
+from .utils import round_to_grid, ceil
 from . import geometry
 
 try:
@@ -187,7 +187,7 @@ class layout():
                 pass
 
             # Skip computing the pitch for non-routing layers
-            if layer_id in ["active", "nwell"]:
+            if layer_id in ["active", "nwell", "pwell"]:
                 continue
 
             # Add the pitch
@@ -259,8 +259,7 @@ class layout():
                 contact_width = contact1.first_layer_width
         layer_space = getattr(layout, layer1 + "_space")
 
-        #print(layer_stack)
-        #print(contact1)
+
         pitch = contact_width + layer_space
 
         return round_to_grid(pitch)
@@ -838,8 +837,7 @@ class layout():
 
         from_id = tech_layer_indices[from_layer]
         to_id   = tech_layer_indices[to_layer]
-
-        layer_list = [x for x in tech_layer_indices.keys() if tech_layer_indices[x] >= from_id and tech_layer_indices[x] < to_id]
+        layer_list = [x for x in tech_layer_indices.keys() if tech_layer_indices[x] > from_id and tech_layer_indices[x] < to_id]
 
         return layer_list
 
@@ -944,14 +942,19 @@ class layout():
 
         return (bot_rect, top_rect)
 
-    def route_horizontal_pins(self, name, insts=None, layer=None, xside="cx", yside="cy", full_width=True):
+    def route_horizontal_pins(self, name, insts=None, layer=None, xside="cx", yside="cy", full_width=True, new_name=None):
         """
         Route together all of the pins of a given name that horizontally align.
         Uses local_insts if insts not specified.
         Uses center of pin by default, or top or botom if specified.
+        New top level pin can be renamed with new_name, otherwise the new pin will keep the same name as old pins
         TODO: Add equally spaced option for IR drop min, right now just 2
         """
 
+        if new_name is not None:
+            pin_name = new_name
+        else:
+            pin_name = name
 
         bins = {}
         if not insts:
@@ -1011,16 +1014,17 @@ class layout():
             left_pos = vector(left_x + 0.5 * via_width, y)
             right_pos = vector(right_x + 0.5 * via_width, y)
 
-#            self.add_layout_pin_rect_ends(name=name,
-#                                          layer=pin_layer,
-#                                          start=left_pos,
-#                                          end=right_pos,
-#                                          width=via_height)
-            self.add_layout_pin_segment_center(text=name,
-                                               layer=pin_layer,
-                                               start=left_pos,
-                                               end=right_pos,
-                                               width=via_height)
+            # self.add_layout_pin_rect_ends(name=name,
+            #                                 layer=pin_layer,
+            #                                 start=left_pos,
+            #                                 end=right_pos,
+            #                                 width=via_height)
+
+            self.add_layout_pin_segment_center(text=pin_name,
+                                            layer=pin_layer,
+                                            start=left_pos,
+                                            end=right_pos,
+                                            width=via_height)
 
     def add_layout_end_pin_segment_center(self, text, layer, start, end):
         """
@@ -1368,12 +1372,11 @@ class layout():
         min_width = drc("minwidth_{}".format(layer))
 
         if preferred_directions[layer] == "V":
-            new_height = max(min_area / width, min_width)
+            new_height = ceil(max(min_area / width, min_width))
             new_width = width
         else:
-            new_width = max(min_area / height, min_width)
+            new_width = ceil(max(min_area / height, min_width))
             new_height = height
-
         debug.check(min_area <= round_to_grid(new_height*new_width), "Min area violated.")
 
         self.add_rect_center(layer=layer,

compiler/base/hierarchy_spice.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/lef.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/logical_effort.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/pin_layout.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/power_data.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/rom_verilog.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -51,7 +51,7 @@ class rom_verilog:
         for port in self.all_ports:
             if port in self.read_ports:
                 self.vf.write("// Port {0}: R\n".format(port))
-                self.vf.write("    clk{0},csb{0},addr{0},dout{0}".format(port))
+                self.vf.write("    clk{0},cs{0},addr{0},dout{0}".format(port))
             # Continue for every port on a new line
             if port != self.all_ports[-1]:
                 self.vf.write(",\n")
@@ -111,7 +111,7 @@ class rom_verilog:
         """
         Create the input regs for the given port.
         """
-        self.vf.write("  reg  csb{0}_reg;\n".format(port))
+        self.vf.write("  reg  cs{0}_reg;\n".format(port))
         self.vf.write("  reg [ADDR_WIDTH-1:0]  addr{0}_reg;\n".format(port))
         if port in self.read_ports:
             self.vf.write("  reg [DATA_WIDTH-1:0]  dout{0};\n".format(port))
@@ -125,14 +125,14 @@ class rom_verilog:
         self.vf.write("  // All inputs are registers\n")
         self.vf.write("  always @(posedge clk{0})\n".format(port))
         self.vf.write("  begin\n")
-        self.vf.write("    csb{0}_reg = csb{0};\n".format(port))
+        self.vf.write("    cs{0}_reg = cs{0};\n".format(port))
         self.vf.write("    addr{0}_reg = addr{0};\n".format(port))
         if port in self.read_ports:
             self.add_write_read_checks(port)
 
         if port in self.read_ports:
             self.vf.write("    #(T_HOLD) dout{0} = {1}'bx;\n".format(port, self.word_size))
-            self.vf.write("    if ( !csb{0}_reg && VERBOSE ) \n".format(port))
+            self.vf.write("    if ( cs{0}_reg && VERBOSE ) \n".format(port))
             self.vf.write("      $display($time,\" Reading %m addr{0}=%b dout{0}=%b\",addr{0}_reg,mem[addr{0}_reg]);\n".format(port))
 
         self.vf.write("  end\n\n")
@@ -142,7 +142,7 @@ class rom_verilog:
         Add the module input and output declaration for a port.
         """
         self.vf.write("  input  clk{0}; // clock\n".format(port))
-        self.vf.write("  input   csb{0}; // active low chip select\n".format(port))
+        self.vf.write("  input   cs{0}; // active high chip select\n".format(port))
 
         self.vf.write("  input [ADDR_WIDTH-1:0]  addr{0};\n".format(port))
         if port in self.read_ports:
@@ -159,10 +159,10 @@ class rom_verilog:
         """
         self.vf.write("\n")
         self.vf.write("  // Memory Read Block Port {0}\n".format(port))
-        self.vf.write("  // Read Operation : When web{0} = 1, csb{0} = 0\n".format(port))
+        self.vf.write("  // Read Operation : When cs{0} = 1\n".format(port))
         self.vf.write("  always @ (negedge clk{0})\n".format(port))
         self.vf.write("  begin : MEM_READ{0}\n".format(port))
-        self.vf.write("    if (!csb{0}_reg)\n".format(port))
+        self.vf.write("    if (cs{0}_reg)\n".format(port))
         self.vf.write("       dout{0} <= #(DELAY) mem[addr{0}_reg];\n".format(port))
         self.vf.write("  end\n")
 

compiler/base/route.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/timing_graph.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 import copy

compiler/base/utils.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/vector.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/vector3d.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/verilog.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/wire.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/wire_path.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/wire_spice_model.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/__init__.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/analytical_util.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/cacti.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/charutils.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/delay.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/elmore.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/fake_sram.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from openram import sram_config

compiler/characterizer/functional.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -45,7 +45,10 @@ class functional(simulation):
             sram.sp_write(self.sp_file, trim=OPTS.trim_netlist)
         # Copy sp file to temp dir
         self.temp_spice = path.join(OPTS.openram_temp, "sram.sp")
-        shutil.copy(self.sp_file, self.temp_spice)
+        try:
+            shutil.copy(self.sp_file, self.temp_spice)
+        except shutil.SameFileError: # skip if the same
+            pass
 
         if not corner:
             corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])

compiler/characterizer/lib.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -254,7 +254,7 @@ class lib:
         self.lib.write("    resistance_unit : \"1kohm\" ;\n")
         self.lib.write("    capacitive_load_unit(1, pF) ;\n")
         self.lib.write("    leakage_power_unit : \"1mW\" ;\n")
-        self.lib.write("    pulling_resistance_unit :\"1kohm\" ;\n")
+        self.lib.write("    pulling_resistance_unit : \"1kohm\" ;\n")
         self.lib.write("    operating_conditions(OC){\n")
         self.lib.write("    process : {} ;\n".format(1.0)) # How to use TT, FF, SS?
         self.lib.write("    voltage : {} ;\n".format(self.voltage))
@@ -536,7 +536,7 @@ class lib:
         min_pulse_width = round_time(self.char_sram_results["min_period"])/2.0
         min_period = round_time(self.char_sram_results["min_period"])
         self.lib.write("        timing(){ \n")
-        self.lib.write("            timing_type :\"min_pulse_width\"; \n")
+        self.lib.write("            timing_type : \"min_pulse_width\"; \n")
         self.lib.write("            related_pin  : clk{0}; \n".format(port))
         self.lib.write("            rise_constraint(scalar) {\n")
         self.lib.write("                values(\"{0}\"); \n".format(min_pulse_width))
@@ -546,7 +546,7 @@ class lib:
         self.lib.write("            }\n")
         self.lib.write("         }\n")
         self.lib.write("        timing(){ \n")
-        self.lib.write("            timing_type :\"minimum_period\"; \n")
+        self.lib.write("            timing_type : \"minimum_period\"; \n")
         self.lib.write("            related_pin  : clk{0}; \n".format(port))
         self.lib.write("            rise_constraint(scalar) {\n")
         self.lib.write("                values(\"{0}\"); \n".format(min_period))

compiler/characterizer/linear_regression.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/measurements.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/model_check.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/neural_network.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/regression_model.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/setup_hold.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/simulation.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/stimuli.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/trim_spice.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/datasheet/__init__.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .datasheet_gen import datasheet_gen

compiler/datasheet/add_db.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/datasheet/datasheet.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/datasheet/datasheet_gen.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/datasheet/table_gen.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/debug.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/drc/__init__.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .custom_cell_properties import *

compiler/drc/custom_cell_properties.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/drc/custom_layer_properties.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/drc/design_rules.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/drc/drc_lut.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/drc/drc_value.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/drc/module_type.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/gen_stimulus.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/globals.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California and The Board
+# Copyright (c) 2016-2024 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/model_configs/shared_config.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 model_name = "cacti"

compiler/model_configs/sram_10b_64w_4wpr_21las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_128b_1024_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_12b_128w_4wpr_38las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_12b_16w_1wpr_1las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_12b_256w_16wpr_186las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_12b_256w_8wpr_17las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_14b_32w_2wpr_23las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_15b_512w_8wpr_85las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_16b_1024w_16wpr_40las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_17b_1024w_16wpr_86las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_17b_256w_16wpr_49las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_18b_128w_2wpr_7las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_18b_32w_1wpr_18las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_21b_1024w_4wpr_54las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_22b_512w_16wpr_249las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_23b_1024w_16wpr_118las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_26b_64w_4wpr_23las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_27b_1024w_4wpr_89las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_27b_256w_8wpr_191las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_27b_512w_4wpr_60las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_32b_1024_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from shared_config import *

compiler/model_configs/sram_32b_2048_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_32b_256_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_32b_32w_1wpr_31las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_32b_512_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_4b_16w_1wpr_4las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_4b_32w_2wpr_5las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_4b_64w_4wpr_14las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_5b_256w_16wpr_75las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_64b_1024_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_64b_512_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_6b_16w_1wpr_1las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_7b_256w_4wpr_25las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_7b_64w_2wpr_10las_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *

compiler/model_configs/sram_8b_1024_1rw.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
 # All rights reserved.
 #
 from .shared_config import *