mirror of https://github.com/VLSIDA/OpenRAM.git
Add LEF output for ROM
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parent
05884cf6a7
commit
8032fa75a4
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@ -11,13 +11,14 @@ from math import ceil, log
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from openram.base import vector
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from openram.base import design
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from openram.base import rom_verilog
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from openram.base import lef
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from openram import OPTS, print_time
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from openram.sram_factory import factory
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from openram.tech import spice
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from openram.tech import drc, layer, parameter
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class rom_bank(design,rom_verilog):
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class rom_bank(design, rom_verilog, lef):
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"""
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Rom data bank with row and column decoder + control logic
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@ -27,6 +28,7 @@ class rom_bank(design,rom_verilog):
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def __init__(self, name, rom_config):
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super().__init__(name=name)
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lef.__init__(self, ["m1", "m2", "m3", "m4"])
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self.rom_config = rom_config
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rom_config.set_local_config(self)
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@ -59,6 +59,9 @@ class rom():
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def sp_write(self, name, lvs=False, trim=False):
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self.r.sp_write(name, lvs, trim)
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def lef_write(self, name):
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self.r.lef_write(name)
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def gds_write(self, name):
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self.r.gds_write(name)
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@ -106,6 +109,13 @@ class rom():
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output_path=OPTS.output_path)
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print_time("GDS", datetime.datetime.now(), start_time)
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# Create a LEF physical model
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start_time = datetime.datetime.now()
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lefname = OPTS.output_path + self.r.name + ".lef"
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debug.print_raw("LEF: Writing to {0}".format(lefname))
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self.lef_write(lefname)
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print_time("LEF", datetime.datetime.now(), start_time)
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# Save the LVS file
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start_time = datetime.datetime.now()
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lvsname = OPTS.output_path + self.r.name + ".lvs.sp"
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@ -51,7 +51,7 @@ openram.print_time("Start", start_time)
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output_extensions = [ "sp", "v"]
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# Only output lef/gds if back-end
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if not OPTS.netlist_only:
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output_extensions.extend(["gds"])
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output_extensions.extend(["lef", "gds"])
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output_files = ["{0}{1}.{2}".format(OPTS.output_path,
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OPTS.output_name, x)
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@ -69,4 +69,4 @@ r.save()
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# Delete temp files etc.
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openram.end_openram()
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openram.print_time("End", datetime.datetime.now(), start_time)
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openram.print_time("End", datetime.datetime.now(), start_time)
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