mirror of https://github.com/VLSIDA/OpenRAM.git
216 lines
6.6 KiB
Python
216 lines
6.6 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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class _bank:
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def __init__(self, stack, pitch):
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# bank
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# column address route: stack, pitch
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# m1_stack, m2_pitch (default)
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# m2_stack, m3_pitch (sky130)
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self.stack = stack
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self.pitch = pitch
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class _hierarchical_decoder:
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def __init__(self,
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bus_layer,
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bus_directions,
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input_layer,
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output_layer,
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vertical_supply):
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# hierarchical_decoder
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# bus_layer, bus_directions, bus_pitch, bus_space, input_layer, output_layer, output_layer_pitch
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# m2, pref, m2_pitch, m2_space, m1, m3, m3_pitch
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# m1, nonpref, m1_pitch, m2_space, m2, li, li_pitch (sky130)
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#
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# vertical vdd/gnd
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# special jogging
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self.bus_layer = bus_layer
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self.bus_directions = bus_directions
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self.input_layer = input_layer
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self.output_layer = output_layer
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self.vertical_supply = vertical_supply
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class _hierarchical_predecode:
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def __init__(self,
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bus_layer,
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bus_directions,
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bus_space_factor,
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input_layer,
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output_layer,
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vertical_supply,
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force_horizontal_input_contact):
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# hierarchical_predecode
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# bus_layer, bus_directions, bus_pitch, bus_space, input_layer, output_layer, output_layer_pitch
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# m2, pref, m2_pitch, m2_space, m1, m1, m1_pitch
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# m1, nonpref, m1_pitch, 1`.5*m1_space, m2, li, li_pitch (sky130)
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#
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# vertical vdd/gnd
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# special jogging
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self.bus_layer = bus_layer
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self.bus_directions = bus_directions
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self.bus_space_factor = bus_space_factor
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self.input_layer = input_layer
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self.output_layer = output_layer
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self.vertical_supply = vertical_supply
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self.force_horizontal_input_contact = force_horizontal_input_contact
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class _column_mux_array:
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def __init__(self,
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select_layer,
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select_pitch,
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bitline_layer):
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# column_mux_array
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# sel_layer, sel_pitch, bitline_layer
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# m1, m2_pitch, m2
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# m3, m3_pitch, m1 (sky130)
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self.select_layer = select_layer
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self.select_pitch= select_pitch
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self.bitline_layer = bitline_layer
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class _port_address:
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def __init__(self,
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supply_offset):
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# port_adress
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# special supply offset
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self.supply_offset = supply_offset
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class _port_data:
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def __init__(self,
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channel_route_bitlines,
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enable_layer):
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# port_data
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# connect bitlines instead of chanel route
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# sense_amp_array
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# en_layer
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# m1
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# m3 (sky130)
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# precharge_array
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# en_bar_layer
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# m1
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# m3 (sky130)
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self.channel_route_bitlines = channel_route_bitlines
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self.enable_layer = enable_layer
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class _replica_column:
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def __init__(self,
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even_rows):
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# replica_column
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# even row check (sky130)
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self.even_rows = even_rows
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class _wordline_driver:
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def __init__(self,
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vertical_supply):
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# wordline_buffer_array
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# vertical vdd/gnd (sky130)
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# wordline_driver_array
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# vertical vdd/gnd (sky130)
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# wordline_driver
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# vertical vdd/gnd (sky130)
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self.vertical_supply = vertical_supply
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class _bitcell_array:
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def __init__(self,
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wordline_layer,
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wordline_pitch_factor=2):
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self.wordline_layer = wordline_layer
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self.wordline_pitch_factor = wordline_pitch_factor
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class layer_properties():
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"""
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This contains meta information about the module routing layers. These
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can be overriden in the tech.py file.
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"""
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def __init__(self):
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self._bank = _bank(stack="m1_stack",
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pitch="m2_pitch")
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self._hierarchical_decoder = _hierarchical_decoder(bus_layer="m2",
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bus_directions="pref",
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input_layer="m1",
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output_layer="m3",
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vertical_supply=False)
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self._hierarchical_predecode = _hierarchical_predecode(bus_layer="m2",
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bus_directions="pref",
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bus_space_factor=1,
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input_layer="m1",
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output_layer="m1",
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vertical_supply=False,
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force_horizontal_input_contact=False)
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self._column_mux_array = _column_mux_array(select_layer="m1",
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select_pitch="m2_pitch",
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bitline_layer="m2")
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self._port_address = _port_address(supply_offset=False)
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self._port_data = _port_data(channel_route_bitlines=True,
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enable_layer="m1")
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self._replica_column = _replica_column(even_rows=False)
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self._wordline_driver = _wordline_driver(vertical_supply=False)
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self._local_bitcell_array = _bitcell_array(wordline_layer="m2")
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self._global_bitcell_array = _bitcell_array(wordline_layer="m3")
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@property
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def bank(self):
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return self._bank
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@property
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def column_mux_array(self):
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return self._column_mux_array
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@property
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def hierarchical_decoder(self):
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return self._hierarchical_decoder
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@property
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def hierarchical_predecode(self):
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return self._hierarchical_predecode
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@property
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def port_address(self):
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return self._port_address
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@property
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def port_data(self):
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return self._port_data
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@property
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def replica_column(self):
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return self._replica_column
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@property
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def wordline_driver(self):
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return self._wordline_driver
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@property
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def global_bitcell_array(self):
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return self._global_bitcell_array
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@property
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def local_bitcell_array(self):
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return self._local_bitcell_array
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