mirror of https://github.com/VLSIDA/OpenRAM.git
129 lines
5.1 KiB
Python
129 lines
5.1 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram import debug
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from openram.tech import GDS, layer
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from openram.tech import preferred_directions
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from openram.tech import cell_properties as props
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from openram import OPTS
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from . import utils
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from .hierarchy_design import hierarchy_design
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class design(hierarchy_design):
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"""
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This is the same as the hierarchy_design class except it contains
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some DRC/layer constants and analytical models for other modules to reuse.
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"""
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def __init__(self, name, cell_name=None, prop=None):
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# This allows us to use different GDS/spice circuits for hard cells instead of the default ones
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# Except bitcell names are generated automatically by the globals.py setup_bitcells routines
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# depending on the number of ports.
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if name in props.names:
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if type(props.names[name]) is list:
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num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports - 1
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cell_name = props.names[name][num_ports]
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else:
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cell_name = props.names[name]
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elif not cell_name:
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cell_name = name
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super().__init__(name, cell_name)
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# This means it is a custom cell.
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# It could have properties and not be a hard cell too (e.g. dff_buf)
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if prop and prop.hard_cell:
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# The pins get added from the spice file, so just check
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# that they matched here
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debug.check(prop.port_names == list(self.pins),
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"Custom cell pin names do not match spice file:\n{0} vs {1}".format(prop.port_names, list(self.pins)))
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self.add_pin_indices(prop.port_indices)
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self.add_pin_names(prop.port_map)
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self.update_pin_types(prop.port_types)
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(width, height) = utils.get_libcell_size(self.cell_name,
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GDS["unit"],
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layer[prop.boundary_layer])
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self.pin_map = utils.get_libcell_pins(list(self.pins),
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self.cell_name,
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GDS["unit"])
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# Convert names back to the original names
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# so that copying will use the new names
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for pin_name in self.pin_map:
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for index1, pin in enumerate(self.pin_map[pin_name]):
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self.pin_map[pin_name][index1].name = self.get_original_pin_name(pin.name)
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self.width = width
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self.height = height
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self.setup_multiport_constants()
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try:
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from openram.tech import power_grid
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self.supply_stack = power_grid
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except ImportError:
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# if no power_grid is specified by tech we use sensible defaults
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# Route a M3/M4 grid
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self.supply_stack = self.m3_stack
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def check_pins(self):
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for pin_name in self.pins:
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pins = self.get_pins(pin_name)
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for pin in pins:
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debug.info(0, "{0} {1}".format(pin_name, pin))
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def setup_multiport_constants(self):
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"""
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These are contants and lists that aid multiport design.
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Ports are always in the order RW, W, R.
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Port indices start from 0 and increment.
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A first RW port will have clk0, csb0, web0, addr0, data0
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A first W port (with no RW ports) will be: clk0, csb0, addr0, data0
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"""
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total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
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# These are the read/write port indices.
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self.readwrite_ports = []
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# These are the read/write and write-only port indices
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self.write_ports = []
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# These are the write-only port indices.
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self.writeonly_ports = []
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# These are the read/write and read-only port indices
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self.read_ports = []
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# These are the read-only port indices.
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self.readonly_ports = []
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# These are all the ports
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self.all_ports = list(range(total_ports))
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# The order is always fixed as RW, W, R
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port_number = 0
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for port in range(OPTS.num_rw_ports):
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self.readwrite_ports.append(port_number)
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self.write_ports.append(port_number)
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self.read_ports.append(port_number)
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port_number += 1
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for port in range(OPTS.num_w_ports):
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self.write_ports.append(port_number)
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self.writeonly_ports.append(port_number)
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port_number += 1
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for port in range(OPTS.num_r_ports):
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self.read_ports.append(port_number)
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self.readonly_ports.append(port_number)
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port_number += 1
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def analytical_power(self, corner, load):
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""" Get total power of a module """
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total_module_power = self.return_power()
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for inst in self.insts:
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total_module_power += inst.mod.analytical_power(corner, load)
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return total_module_power
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