 mrg
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e774314add
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Separate write driver pins by M3 pitch
|
2020-06-28 14:14:48 -07:00 |
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|
mrg
|
0c9f52e22f
|
Realign col decoder and control by 1/4 so metal can pass over
|
2020-06-28 07:15:06 -07:00 |
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|
mrg
|
66ea559209
|
Use channel for dffs all at once
|
2020-06-27 08:23:12 -07:00 |
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|
mrg
|
c10a6a29c0
|
Simplify precharge pin layer
|
2020-06-27 08:22:16 -07:00 |
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|
mrg
|
609aa98c8b
|
Move write mask pin to left of cell to avoid sense amp
|
2020-06-27 08:21:53 -07:00 |
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|
mrg
|
2bd498c39c
|
Change precharge layer to m3
|
2020-06-27 08:21:30 -07:00 |
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mrg
|
a7ee17eb2d
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Move output of sense amp to side like other techs
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2020-06-26 15:29:27 -07:00 |
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|
mrg
|
c07e20cbe4
|
Move mux select from li to m2 in sky130
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2020-06-26 14:27:16 -07:00 |
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mrg
|
94d7000717
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Reduce output clutter from gds write
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2020-06-26 12:16:54 -07:00 |
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|
mrg
|
f57eeb88eb
|
PEP8 cleanup, multiple vdd/gnd support
|
2020-06-26 11:47:55 -07:00 |
|
|
mrg
|
e23d41c1d4
|
PEP8 cleanup
|
2020-06-26 11:47:35 -07:00 |
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|
mrg
|
567675ab31
|
PEP8 cleanup
|
2020-06-26 11:47:12 -07:00 |
|
|
mrg
|
af4ed3dd6e
|
Skip riscv func test for time sake
|
2020-06-26 06:50:45 -07:00 |
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|
mrg
|
d53abba479
|
Always route the channel route since it is it's own design.
|
2020-06-25 17:43:44 -07:00 |
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|
mrg
|
76e5389c33
|
Change riscv func test name
|
2020-06-25 17:43:17 -07:00 |
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|
mrg
|
9eb1b500ea
|
Skip phys riscv test
|
2020-06-25 17:31:23 -07:00 |
|
|
mrg
|
f11afaa63d
|
Refactor channel route to be a design.
|
2020-06-25 17:30:03 -07:00 |
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|
mrg
|
7220b23402
|
Add riscv unit tests
|
2020-06-25 15:34:18 -07:00 |
|
|
mrg
|
66df659ad4
|
Col decoders are anything not bitcell pitch.
|
2020-06-25 14:25:48 -07:00 |
|
|
mrg
|
f84ee04fa9
|
Single bank passing.
Parameterized gate column mux of dff height.
End-cap only supply option instead of no vdd in bitcell.
|
2020-06-25 14:03:59 -07:00 |
|
|
mrg
|
ee0a003298
|
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
|
2020-06-25 08:57:37 -07:00 |
|
 jcirimel
|
5941e01b51
|
add missing parens
|
2020-06-25 08:02:08 -07:00 |
|
|
jcirimel
|
59562f2b92
|
move accuracy_requirement from techfile to config
|
2020-06-25 06:44:07 -07:00 |
|
|
jcirimel
|
812cf11e95
|
Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev
|
2020-06-25 06:32:29 -07:00 |
|
|
jcirimel
|
57b6d49edb
|
fix pinv size bining
|
2020-06-25 06:32:07 -07:00 |
|
|
mrg
|
da900b89ba
|
Only expand implants in sky130
|
2020-06-24 13:48:30 -07:00 |
|
|
mrg
|
ba92467fec
|
Add no well enclosure for techs without wells
|
2020-06-24 12:07:47 -07:00 |
|
|
mrg
|
6c523a7556
|
use add_enclosure for npc contacts
|
2020-06-24 11:55:44 -07:00 |
|
|
mrg
|
e694622f28
|
use add_enclosure to extend implants
|
2020-06-24 11:54:59 -07:00 |
|
|
mrg
|
4bc3df8931
|
Add get_tx_insts and expand add_enclosure
|
2020-06-24 11:54:36 -07:00 |
|
|
mrg
|
93d65e84e1
|
Fix power pin layer problems in delay line
|
2020-06-24 10:26:49 -07:00 |
|
|
mrg
|
98ec9442c6
|
Add npc enclosure for pnand2, pnand3, pnor2
|
2020-06-24 10:00:00 -07:00 |
|
|
mrg
|
1340908330
|
Remove fudge factor for pin spacing
|
2020-06-24 09:24:26 -07:00 |
|
|
mrg
|
cddb16dabc
|
Separate active and poly contact to gate rule
|
2020-06-24 09:17:39 -07:00 |
|
|
mrg
|
a32b5b13e8
|
Rename nwell yoffset for consistency
|
2020-06-24 08:26:15 -07:00 |
|
|
mrg
|
b3d1161957
|
Add u+x permissions to new tests
|
2020-06-24 08:19:25 -07:00 |
|
 Joey Kunzler
|
22ed725a35
|
made 1rw_1r tests for write driver and wmask, fixed typo in portdata_wmask_1rw_1r_test
|
2020-06-23 18:16:14 -07:00 |
|
|
Joey Kunzler
|
4e83e8c648
|
added contact to locali for wmask
|
2020-06-23 18:13:17 -07:00 |
|
|
mrg
|
22c821f5d8
|
Change port_address test to 256 for riscv
|
2020-06-23 15:40:00 -07:00 |
|
|
mrg
|
cfa234a4d0
|
Extra space between decoders for well spacing
|
2020-06-23 15:39:42 -07:00 |
|
|
mrg
|
83001e1ab5
|
PEP8 formatting
|
2020-06-23 15:39:26 -07:00 |
|
|
mrg
|
e849a9b973
|
Use different LVS libs based on tech and sky130
|
2020-06-23 14:53:24 -07:00 |
|
|
mrg
|
031862c749
|
Add metal enclosure to base case of center via stack.
|
2020-06-23 11:56:50 -07:00 |
|
|
mrg
|
1a528f9739
|
Skip and4_dec test
|
2020-06-23 10:08:28 -07:00 |
|
|
mrg
|
7ea3366ef1
|
Disable magic filter in sky130
|
2020-06-22 16:58:01 -07:00 |
|
|
mrg
|
92fc30005c
|
Use factory in and_dec tests
|
2020-06-22 16:55:49 -07:00 |
|
|
mrg
|
40edbfa51f
|
Error out on single port in sky130
|
2020-06-22 15:41:59 -07:00 |
|
|
mrg
|
cd23b31ab4
|
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
|
2020-06-22 12:55:45 -07:00 |
|
|
mrg
|
0926eab9f5
|
PEP8 formatting
|
2020-06-22 12:55:18 -07:00 |
|
|
mrg
|
54120f8405
|
Add option for removing subckt/instances of cells for row/col caps
|
2020-06-22 12:35:37 -07:00 |
|