 mrg
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e1967dc548
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Draft local and global arrays. Ensure rows before cols in usage.
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2020-07-23 14:43:14 -07:00 |
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mrg
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58846a4a25
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Limit wordline driver size. Place row addr dff near predecoders.
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2020-07-20 17:57:38 -07:00 |
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mrg
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bed2e36550
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Simplify write mask supply via logic
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2020-07-01 14:44:48 -07:00 |
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mrg
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8cd1cba818
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Fix missing via in wmask driver
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2020-07-01 14:44:18 -07:00 |
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mrg
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bb18d05f75
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Move control output via inside module instead of perimeter
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2020-07-01 11:33:25 -07:00 |
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mrg
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3d0f29ff3a
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Fix missing via LVS issues. LVS passing for some 20 tests.
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2020-07-01 09:22:59 -07:00 |
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mrg
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b07f30cb9e
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Missing output via in control logic
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2020-06-30 16:23:07 -07:00 |
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mrg
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011ac2fc05
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Don't route to clk to perimeter on m2
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2020-06-30 13:57:45 -07:00 |
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mrg
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a48ea52253
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Add missing contact to vdd pins.
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2020-06-30 13:26:38 -07:00 |
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mrg
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eb11ac22f3
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Widen pitch of control bus in bank.
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2020-06-30 10:58:09 -07:00 |
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mrg
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372a8a728e
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Off by one error in channel spacing
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2020-06-29 16:47:34 -07:00 |
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mrg
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459e3789b8
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Change control layers in sky130.
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2020-06-29 16:23:25 -07:00 |
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mrg
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bec948dcc3
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Fix error in when to add vias for array power
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2020-06-29 15:28:55 -07:00 |
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mrg
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07d0f3af8e
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Only copy end-cap pins to the bank level
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2020-06-29 11:46:59 -07:00 |
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mrg
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1bc0775810
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Only add pins to periphery
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2020-06-29 10:03:24 -07:00 |
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mrg
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5285468380
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All bitcells need a vdd/gnd pin
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2020-06-28 15:09:47 -07:00 |
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mrg
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051c8d8697
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Only add bitcells to dummy and replica rows and columns (the perimeter)
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2020-06-28 14:47:54 -07:00 |
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mrg
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225fc69420
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Use preferred routing direction
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2020-06-28 14:29:12 -07:00 |
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mrg
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0c9f52e22f
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Realign col decoder and control by 1/4 so metal can pass over
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2020-06-28 07:15:06 -07:00 |
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mrg
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66ea559209
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Use channel for dffs all at once
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2020-06-27 08:23:12 -07:00 |
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mrg
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609aa98c8b
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Move write mask pin to left of cell to avoid sense amp
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2020-06-27 08:21:53 -07:00 |
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mrg
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2bd498c39c
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Change precharge layer to m3
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2020-06-27 08:21:30 -07:00 |
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mrg
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c07e20cbe4
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Move mux select from li to m2 in sky130
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2020-06-26 14:27:16 -07:00 |
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mrg
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f57eeb88eb
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PEP8 cleanup, multiple vdd/gnd support
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2020-06-26 11:47:55 -07:00 |
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mrg
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e23d41c1d4
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PEP8 cleanup
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2020-06-26 11:47:35 -07:00 |
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mrg
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66df659ad4
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Col decoders are anything not bitcell pitch.
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2020-06-25 14:25:48 -07:00 |
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mrg
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f84ee04fa9
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Single bank passing.
Parameterized gate column mux of dff height.
End-cap only supply option instead of no vdd in bitcell.
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2020-06-25 14:03:59 -07:00 |
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mrg
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93d65e84e1
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Fix power pin layer problems in delay line
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2020-06-24 10:26:49 -07:00 |
|
 Joey Kunzler
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4e83e8c648
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added contact to locali for wmask
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2020-06-23 18:13:17 -07:00 |
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mrg
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cfa234a4d0
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Extra space between decoders for well spacing
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2020-06-23 15:39:42 -07:00 |
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mrg
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cd23b31ab4
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-06-22 12:55:45 -07:00 |
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mrg
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0926eab9f5
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PEP8 formatting
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2020-06-22 12:55:18 -07:00 |
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Joey Kunzler
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208c652653
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added error for sky130 with invalid x mirroring (for lvs)
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2020-06-19 13:59:33 -07:00 |
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mrg
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abb5ff7bae
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Separate route conditions for s8
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2020-06-15 10:30:27 -07:00 |
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mrg
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e331d6fae8
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Permute bus order to avoid conflict in control_logic
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2020-06-15 10:25:53 -07:00 |
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mrg
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79b3b9a8b0
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Switch input/output layers for predecodes
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2020-06-15 10:06:04 -07:00 |
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mrg
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02352c35d7
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Fix hard coded layer in wmask
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2020-06-14 17:10:32 -07:00 |
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mrg
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78be9f367a
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Add brain-dead router pins to perimeter
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2020-06-14 15:52:09 -07:00 |
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mrg
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33a32101c9
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DRC and LVS fixes for pinv_dec
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2020-06-12 15:23:51 -07:00 |
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mrg
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443b8fbe23
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Change s8 to sky130
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2020-06-12 14:23:26 -07:00 |
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mrg
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e9780ea599
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Add non-preferred directions for channel routes
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2020-06-11 15:03:36 -07:00 |
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mrg
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dff28a9997
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Merge branch 'tech_migration' into dev
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2020-06-10 17:09:05 -07:00 |
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mrg
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bfd1abc79f
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Replica column pins start at 0 height.
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2020-06-10 14:58:55 -07:00 |
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mrg
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157926960b
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Flip freepdk45 flop, dff_buf route layer change
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2020-06-09 13:48:16 -07:00 |
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mrg
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77fb7017c4
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Merge branch 'tech_migration' into dev
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2020-06-08 12:54:41 -07:00 |
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mrg
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9cc36c6d3a
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Bus code converted to pins. Fix layers on control signal routes in bank.
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2020-06-08 11:01:14 -07:00 |
|
 Aditi Sinha
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300522a1a8
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Change spare enable pins offset to lower right
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2020-06-08 14:31:46 +00:00 |
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Aditi Sinha
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d5041afebc
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Merge branch 'dev' into bisr
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2020-06-07 16:27:25 +00:00 |
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mrg
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0837432d45
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Wordline route layers and (optional) via.
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2020-06-05 16:47:22 -07:00 |
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mrg
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5514996708
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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