mrg e9780ea599 Add non-preferred directions for channel routes

2020-06-11 15:03:36 -07:00

..

bank_select.py

Changes to simplify metal preferred directions and pitches.

2020-05-10 11:32:45 -07:00

bank.py

Add non-preferred directions for channel routes

2020-06-11 15:03:36 -07:00

bitcell_array.py

Configured bitline directions into prot_data

2020-04-20 14:23:40 -07:00

bitcell_base_array.py

update for end caps

2020-05-27 20:03:11 -07:00

col_cap_array.py

Auto-generate port dependent cell names.

2020-06-05 15:09:22 -07:00

control_logic.py

Merge branch 'tech_migration' into dev

2020-06-08 12:54:41 -07:00

delay_chain.py

Changes to allow decoder height to be a 2x multiple of bitcell height.

2020-05-10 06:56:22 -07:00

dff_array.py

add custom module file, make dff clk pin dynamic

2020-02-04 23:35:06 -08:00

dff_buf_array.py

Add supply rails to dff array. PEP8 cleanup.

2020-04-21 15:21:29 -07:00

dff_buf.py

Flip freepdk45 flop, dff_buf route layer change

2020-06-09 13:48:16 -07:00

dff_inv_array.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

dff_inv.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

dummy_array.py

Auto-generate port dependent cell names.

2020-06-05 15:09:22 -07:00

hierarchical_decoder.py

Bus code converted to pins. Fix layers on control signal routes in bank.

2020-06-08 11:01:14 -07:00

hierarchical_predecode2x4.py

Thin-cell decoder changes.

2020-05-29 10:36:07 -07:00

hierarchical_predecode3x8.py

Thin-cell decoder changes.

2020-05-29 10:36:07 -07:00

hierarchical_predecode4x16.py

Thin-cell decoder changes.

2020-05-29 10:36:07 -07:00

hierarchical_predecode.py

Bus code converted to pins. Fix layers on control signal routes in bank.

2020-06-08 11:01:14 -07:00

module_type.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

multibank.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

port_address.py

Merge branch 'dev' into bisr

2020-06-07 16:27:25 +00:00

port_data.py

Merge branch 'dev' into bisr

2020-06-07 16:27:25 +00:00

precharge_array.py

Bus code converted to pins. Fix layers on control signal routes in bank.

2020-06-08 11:01:14 -07:00

replica_bitcell_array.py

PEP8 format replica_bitcell_array

2020-06-05 13:49:32 -07:00

replica_column.py

Replica column pins start at 0 height.

2020-06-10 14:58:55 -07:00

row_cap_array.py

Auto-generate port dependent cell names.

2020-06-05 15:09:22 -07:00

sense_amp_array.py

Merge branch 'dev' into bisr

2020-06-07 16:27:25 +00:00

sense_amp.py

sense_amp: Allow custom pin names

2020-02-17 15:20:12 +01:00

single_level_column_mux_array.py

Update mirroring in port_data for bitcell mirrored arrays

2020-06-05 11:29:31 -07:00

tri_gate_array.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

wordline_driver_array.py

Thin-cell decoder changes.

2020-05-29 10:36:07 -07:00

write_driver_array.py

Change spare enable pins offset to lower right

2020-06-08 14:31:46 +00:00

write_mask_and_array.py

Fix syntax error

2020-06-05 12:13:41 -07:00