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OpenRAM
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1997 Commits

Author SHA1 Message Date
mrg d916322b74 PEP8 updates 2020-03-31 10:15:46 -07:00
Joey Kunzler b0d2946c80 update to sense amp and write driver modules 2020-03-30 20:00:32 -07:00
mrg 9907daaffa Min area only for multiple layers 2020-03-26 13:05:02 -07:00
mrg d2c97d75a7 Add well contact and min area to power pin of precharge 2020-03-26 11:49:32 -07:00
mrg 1e3734cb26 Hack to fix pnand3 in freepdk45 2020-03-26 11:08:53 -07:00
mrg 2f353187ba Skywater extraction mode for si unit scales 2020-03-24 12:41:15 -07:00
mrg 1e2163c3a6 Hack for pnand3 pin spacing 2020-03-24 12:40:41 -07:00
mrg e9d0db44fd Add li_stack contact to ptx and pgate if it exists. 2020-03-23 16:55:38 -07:00
mrg f491876a5a Move up B input in pnor2 2020-03-23 13:49:08 -07:00
mrg c15b4167b6 Merge branch 'dev' into tech_migration 2020-03-23 11:57:03 -07:00
mrg f598a359d5 Remove unused contact in pnor2 2020-03-23 11:55:17 -07:00
mrg 717cbb0fe5 Remove unused contact in pnand3 2020-03-23 11:52:19 -07:00
mrg 0ee6963198 Remove unused contact in pnand2 2020-03-23 11:46:21 -07:00
mrg f21791a904 Add source drain contact options to ptx. 2020-03-23 11:36:45 -07:00
mrg 9df99beb28 Merge branch 'tech_migration' into dev 2020-03-06 15:03:46 -08:00
mrg fd7af7fc25 Matt sucks skip test 2020-03-06 15:03:31 -08:00
mrg c5a1be703c Rotate via and PEP8 formatting 2020-03-06 13:39:46 -08:00
mrg 23501c7b35 Convert pnand+pinv to pand in decoders. 2020-03-06 13:26:40 -08:00
mrg 1a2efd77ad Move rbl route away from bitcell array 2020-03-06 09:48:20 -08:00
mrg ee18f61cbf Route RBL to edge of bank. 2020-03-06 09:03:52 -08:00
mrg 05f9e809b4 PEP8 Formatting 2020-03-05 16:27:35 -08:00
mrg 6506622dfb PEP8 Formatting 2020-03-05 16:20:21 -08:00
mrg 5b23653369 PEP8 Formatting 2020-03-05 16:13:49 -08:00
mrg ad98137cd4 Merge branch 'dev' into tech_migration 2020-03-05 14:18:06 -08:00
mrg 5312629702 Remove jog in precharge. Jog is in port data 2020-03-05 12:10:13 -08:00
mrg 9c1f0657dd PEP8 Formatting 2020-03-05 11:58:36 -08:00
mrg 7adeef6c9e PEP8 Formatting 2020-03-05 10:21:18 -08:00
mrg 287a31f598 Precharge updates. 
Enable different layers for bitlines.
Jog bitlines to fit precharge transistors for close proximity bitlines.
PEP8 cleanup.
 2020-03-04 17:39:11 -08:00
Joey Kunzler d7529ce526 Vdd/gnd via stacks now use perferred directions, added cell property to override 2020-03-04 17:05:19 -08:00
mrg 7ba9e09e12 Incomplete precharge layer decoupling 2020-03-04 22:23:05 +00:00
mrg bb2305d56a PEP8 format fixes 2020-02-28 18:24:39 +00:00
mrg e1b97f58e1 Add instance center location 2020-02-28 18:24:09 +00:00
mrg 0b73979388 Space inputs by M1 pitch 2020-02-28 18:23:49 +00:00
mrg 073bd47b31 Add source/drain/gate to structure 2020-02-28 18:23:36 +00:00
Matt Guthaus 1617840ed3 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-02-27 08:50:19 -08:00
mrg 266d68c395 Generalize pgate width based on nwell/pwell contacts 2020-02-25 17:09:07 +00:00
Matt Guthaus 0db0c5a3a9 Update version to 1.1.4 2020-02-25 08:09:08 -08:00
mrg e80677caf7 Merge remote-tracking branch 'origin/dev' into tech_migration 2020-02-25 00:36:43 +00:00
mrg 254e584e35 Cleanup and simplify ptx for multiple technologies 2020-02-25 00:36:22 +00:00
mrg 585a708e0c Generalize y offsets in pnand3 2020-02-25 00:36:02 +00:00
mrg d565c9ac72 Generalize input y offsets 2020-02-25 00:35:32 +00:00
mrg 6bcffb8efb Change default cell height and fix contact width error 2020-02-25 00:34:59 +00:00
mrg 35110a4453 Improve debug of non-manhattan error 2020-02-25 00:34:28 +00:00
Joey Kunzler 4c9b3c5864 Merge branch 's8_update' into dev 
Add lpp to addText(), remove reference to specific technology in gdsMill
 2020-02-24 14:02:18 -08:00
Bastian Koppelmann 0e641bf905 Remove write_driver_array.py.orig 
this was the remainder of applying a diff using "patch". To avoid this
mistake, add the filetypes created by "patch" to the .gitignore.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-21 13:29:43 +01:00
Joey Kunzler c9cb387912 fixed variable typo 2020-02-20 18:35:54 -08:00
Matt Guthaus da4c69ab98 Merge branch 'pin-pull3' into dev 2020-02-20 09:07:58 -08:00
Hunter Nichols c1cb6bf512 Changed layout input names of s_en AND gate to match the schematic 2020-02-19 23:32:11 -08:00
Joey Kunzler d6987ac584 added purposes to addText(), removed reference to specific tech from gdsMill 2020-02-19 16:26:52 -08:00
Hunter Nichols df2f981a34 Adds checks to prevent characterization of redundant corners. 2020-02-19 15:59:26 -08:00