OpenRAM/compiler
mrg d916322b74 PEP8 updates 2020-03-31 10:15:46 -07:00
..
base Min area only for multiple layers 2020-03-26 13:05:02 -07:00
bitcells bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
characterizer Adds checks to prevent characterization of redundant corners. 2020-02-19 15:59:26 -08:00
datasheet Convert capital names to lower case for consistency 2019-08-21 13:45:34 -07:00
drc Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
example_configs revert example scn4m to non netlist only 2020-02-09 23:52:11 -08:00
gdsMill added purposes to addText(), removed reference to specific tech from gdsMill 2020-02-19 16:26:52 -08:00
modules PEP8 updates 2020-03-31 10:15:46 -07:00
pgates Add well contact and min area to power pin of precharge 2020-03-26 11:49:32 -07:00
router tech: Make power_grid configurable 2020-01-28 12:06:34 +01:00
sram Route RBL to edge of bank. 2020-03-06 09:03:52 -08:00
tests update to sense amp and write driver modules 2020-03-30 20:00:32 -07:00
verify Skywater extraction mode for si unit scales 2020-03-24 12:41:15 -07:00
Makefile Clean up Makefile for unit tests 2018-12-05 12:58:10 -08:00
debug.py Add layer-purpose GDS support. Various PEP8 fixes. 2019-11-14 18:17:20 +00:00
gen_stimulus.py Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00
globals.py Update version to 1.1.4 2020-02-25 08:09:08 -08:00
openram.py Only setup bitcell when running top-level OpenRAM 2019-11-26 13:54:37 -08:00
options.py Blackbox option for DRC waivers 2019-11-29 15:50:32 -08:00
run_profile.sh Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
sram_factory.py sram_factory: Add check for duplicate module name 2019-12-19 16:31:52 +01:00
view_profile.py Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00