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OpenRAM
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356 Commits

Author SHA1 Message Date
Matt Guthaus 33b04bbca5 Add area/perimeter of source/drain to transistor netlist. Gets rid of some spice warnings, gives better non-annotated measurements. 2018-02-05 16:02:57 -08:00
Matt Guthaus 941094ce31 Return slews to 10-90 and 90-10 so I don't have to re-hardcode the results in unit tests. 2018-02-05 15:21:53 -08:00
Matt Guthaus 4505c0f74e Improve error to setup model dir path. Use it to override FreePDK45 too. 2018-02-05 15:12:12 -08:00
Matt Guthaus 85f4438280 Exit with error if model files are not found. 2018-02-05 15:09:21 -08:00
mguthaus e01d5b7c61 Disable virtual connects at top level LVS with Calibre. 2018-02-05 14:52:51 -08:00
Matt Guthaus e2e5f45cec Correct vague comments about char cycles. End simulation after last period even though a transition would mean a failed simulation. 2018-02-05 14:07:12 -08:00
Matt Guthaus a8e1abdce8 Use method=gear for ngspice to improve convergence. Split TD for trig and targ in measure statements. Start waiting for clk neg edge trigger at clk pos edge. 2018-02-05 11:36:46 -08:00
Matt Guthaus 92095e52f7 Update new LEF files for unit tests. 2018-02-05 10:27:56 -08:00
Matt Guthaus f21ff38cae Simplify via offsets in replica bitline. Route clk_bar in control over supply rail until we get channel router working. 2018-02-05 10:22:38 -08:00
Matt Guthaus 84b42b0170 Fix bug in trim netlist. Add info comments to spice netlist and trimmed netlist. Increase verbosity for simulations. 2018-02-02 19:33:07 -08:00
Matt Guthaus 7127895270 Update LEF files for unit tests 2018-02-02 15:51:29 -08:00
Matt Guthaus d6d96907ef Route to the right in the bank decode for DRC. 2018-02-02 15:50:45 -08:00
Matt Guthaus 1415d139a3 Specify file format for sp spice extension. 2018-02-02 15:33:35 -08:00
Matt Guthaus 3873f72a58 Ensure wells are spaced in the bank select and column decoder 2018-02-02 15:26:15 -08:00
Matt Guthaus ffcf58100e Clean up column mux by moving pins to own function. Adjust spacing between column mux and bitcell to prevent DRCs. Fix up find lowest/highest functions when no objects or instances in a module. 2018-02-02 15:17:21 -08:00
Matt Guthaus 9d043b904e Remove unnecessary design reset 2018-02-02 14:26:53 -08:00
Matt Guthaus 27dbb95c19 Fix name of column mux. 2018-02-02 14:26:39 -08:00
Matt Guthaus 9d7dc4c552 Reset even if not purging temp files. 2018-02-02 14:26:09 -08:00
Matt Guthaus 2a8199c3ca Force re-extract of cells in DRC/LVS. 2018-02-02 14:21:31 -08:00
Matt Guthaus fb90b8f5fe Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder. 2018-02-02 14:08:56 -08:00
Matt Guthaus 3be59fb762 Change DRC output for magic to drc.summary just like calibre output. 2018-02-02 14:07:15 -08:00
Matt Guthaus 63392c8d71 Fix gnd connection in control logic. 2018-02-02 13:04:38 -08:00
Matt Guthaus 072c8e3174 Change LVS report file to same name as Calibre 2018-02-02 12:47:42 -08:00
Hunter Nichols db4913dd9c Added skeleton code for analytical power in functions with analytical delay. 2018-02-02 12:31:34 -08:00
Matt Guthaus 74064fc854 Replace LEF files with new changes. 2018-02-02 12:31:34 -08:00
Matt Guthaus e8d001a3f9 Change wen to en in spice lib files. Check lvs report insted of stdout with netgen. 2018-02-02 12:31:33 -08:00
Matt Guthaus e4295ea61b Fix pin names to lower case. Fix write driver DRC errors and LVS error. 2018-02-02 12:31:33 -08:00
Matt Guthaus 3e2d4d631d Do not require hspice during tests. Check if a valid simulator is found, however. 2018-02-02 12:31:33 -08:00
Matt Guthaus 7c9c16e29c Fix assertion error syntax problem. Do not require hspice for functional test. Improve delay fail error message. 2018-02-02 12:31:33 -08:00
Matt Guthaus cc987daeb9 Add well around column muxes. 2018-02-02 12:31:33 -08:00
mguthaus 2ad52205c5 Clean up messages. 2018-02-02 12:31:33 -08:00
mguthaus d0c9382d97 Modify unit tests to distinguish between FAIL and ERROR. Move comparison utilities into our derived unit test class. 2018-02-02 12:31:33 -08:00
Hunter Nichols 56f7caf59f Added first test power model to sram 2018-02-02 12:31:33 -08:00
Matt Guthaus 5527e73db0 Add descriptive exceptions along with cleanup in unit test checking. 2018-02-02 12:31:33 -08:00
Matt Guthaus be1c59f10c Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array. 2018-02-02 12:31:33 -08:00
Matt Guthaus ea5eda91fc Connect all gnd rails of RBL. 2018-02-02 12:27:24 -08:00
Matt Guthaus d552d88f45 Add -d option to not delete temp directory on successful runs. 2018-02-01 11:53:02 -08:00
Matt Guthaus 8ef1e0af2c Replace LEF files with new changes. 2018-02-01 05:43:37 -08:00
Matt Guthaus 64546ad3dd Change wen to en in spice lib files. Check lvs report insted of stdout with netgen. 2018-02-01 05:38:48 -08:00
Matt Guthaus 512448f9e8 Fix pin names to lower case. Fix write driver DRC errors and LVS error. 2018-01-31 17:37:16 -08:00
Matt Guthaus 9fea4a1a2d Do not require hspice during tests. Check if a valid simulator is found, however. 2018-01-31 16:21:43 -08:00
Matt Guthaus 590f6e01d1 Fix assertion error syntax problem. Do not require hspice for functional test. Improve delay fail error message. 2018-01-31 15:38:02 -08:00
Matt Guthaus acf3fe8376 Add well around column muxes. 2018-01-31 14:31:50 -08:00
mguthaus 4273a3717d Clean up messages. 2018-01-31 11:54:20 -08:00
mguthaus 4aee700331 Modify unit tests to distinguish between FAIL and ERROR. Move comparison utilities into our derived unit test class. 2018-01-31 11:48:41 -08:00
Matt Guthaus 1175f515c8 Add descriptive exceptions along with cleanup in unit test checking. 2018-01-31 10:35:51 -08:00
Matt Guthaus 58da8af619 Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array. 2018-01-31 10:04:28 -08:00
Matt Guthaus 012c3923be Create empty setup.tcl file as workaround for resetting netgen LVS options until Tim fix's bug. 2018-01-31 08:28:53 -08:00
Matt Guthaus 264d55b16c Remove temp files 2018-01-30 08:05:50 -08:00
Matt Guthaus 8fcb551953 Only perform DRC not LVS on transistors 2018-01-30 08:03:54 -08:00
Matt Guthaus 1d9274621a Only remove files when cleaning temp dir 2018-01-30 07:58:31 -08:00
Matt Guthaus 0b6eddef43 Force write the specific cell during DRC. 2018-01-29 17:00:20 -08:00
Matt Guthaus 56770f558f Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
Matt Guthaus 313e06d2af Fix pwell contact in column mux to have layers for Magic. 2018-01-29 15:53:22 -08:00
Matt Guthaus 6080b59058 Fix nand input ordering to correct netgen LVS error of wordline driver. 2018-01-29 15:36:37 -08:00
Matt Guthaus a56fa0e787 Fix wrong pin order on pnand2 LVS problem. 2018-01-29 15:31:14 -08:00
Matt Guthaus 79715ae1a2 Fix input discrepencies in pre3x8 2018-01-29 15:25:41 -08:00
Matt Guthaus 3c5ecb963d Remove level of indirection to ptx devices to allow LVS symmetries. 2018-01-29 15:25:15 -08:00
Matt Guthaus 586d80623e Remove level of indirection to ptx devices to allow LVS symmetries. 2018-01-29 15:25:00 -08:00
Matt Guthaus 31c192c2e9 Fix precharge nwell contact spacing DRC violatin. 2018-01-26 13:53:45 -08:00
Matt Guthaus e46a4fb115 Use any spice for the functional tests. 2018-01-26 13:53:11 -08:00
Matt Guthaus 028146f3c2 Add output explaining error for not finding simulator in unit tests. 2018-01-26 13:23:11 -08:00
Matt Guthaus 369aa85cd2 Fail simulation tests if correct spice is not found. Correctly load spice characterizer. 2018-01-26 13:00:25 -08:00
Matt Guthaus 50107636a0 Fail test early if spice simulator is not found. 2018-01-26 12:47:32 -08:00
Matt Guthaus 1dc7752429 Fix 6T and replica cell contact spacing issues with Magic DRC. 
DRC/LVS passing for all parameterized gates.
Magic and GDS match for SCMOS rules again.
 2018-01-26 12:39:00 -08:00
Matt Guthaus ac8eada0d8 Fix devices sizes in SCMOS sense amp. Elaborate magic/netgen scripts in comments. 2018-01-24 13:02:55 -08:00
Matt Guthaus 1b2df3a5a1 Properly ignore ad as, pd, ps property errors 2018-01-22 17:50:53 -08:00
Matt Guthaus 2468f224d9 SCMOS library cells passing LVS (with property errors though). Permute must be enabled before compare, duh. 2018-01-22 17:14:39 -08:00
Matt Guthaus fb2ed1d46c Add wells to fix DRC errors in SCMOS library cells. 2018-01-22 16:28:20 -08:00
Matt Guthaus f572b83671 Add Makefile for parallel test execution. 2018-01-22 13:39:07 -08:00
Matt Guthaus 10ced33127 Fixed command line arguments to take priority over config file. Any option can be specified in config file now. 2018-01-21 11:21:09 -08:00
Matt Guthaus 84ec7a5be0 Convert unit tests to use new options as well. 2018-01-19 17:23:38 -08:00
Matt Guthaus 95fab1ca71 Remove personalized temp dir. 2018-01-19 16:39:14 -08:00
Matt Guthaus 490a70dee9 Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file. 2018-01-19 16:38:19 -08:00
Matt Guthaus 72b0617e81 Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-01-19 16:19:12 -08:00
Matt Guthaus efa465757c Remove dead code ptx_port. 2018-01-19 16:19:05 -08:00
Matt Guthaus fcc533ec11 Initial LVS using netgen. pinv nad pnand2 pass. No property checks in LVS yet. 2018-01-17 16:48:35 -08:00
Matt Guthaus ba489f0291 Only check if using magic with freepdk when LVSDRC is enabled. 2018-01-17 07:38:29 -08:00
Matt Guthaus 7c50708158 Check that we are not using Magic for FreePDK45. 2018-01-12 14:50:35 -08:00
Matt Guthaus 243097cb33 Remove print statement in magic.py 2018-01-12 14:45:11 -08:00
Matt Guthaus 1b30eb4b64 Initial DRC with Magic is done. 2018-01-12 14:39:42 -08:00
Matt Guthaus 7a172873a3 Update unit tests to load verify after config file. Start magic DRC. 2018-01-12 10:24:49 -08:00
Matt Guthaus e0a6b59773 Fix LEF test mismatch in regression. 2018-01-12 08:54:31 -08:00
Matt Guthaus 1701eac1a9 Added workaround to import layouts into Magic. Select and well layers in active contacts. Fixed missing implant enclose active DRC rule in parameterized cells. 2018-01-11 10:24:44 -08:00
Matt Guthaus f028436156 Add implant/select enclosure rule to ptx. 2018-01-08 12:27:50 -08:00
Matt Guthaus e95988c639 Document tech files. Remove unused/redundant rules. Made rule names consistent/simple. 2018-01-08 11:57:51 -08:00
Matt Guthaus fd748b4fe4 Move info messages about modes to better locations. 2018-01-05 08:32:23 -08:00
Matt Guthaus 4885616bec Remove metal3 in LEF library cells. 2017-12-19 13:12:39 -08:00
Matt Guthaus 97a2d620fe Fix dev tests. Split pruned test to separate golden result. 2017-12-19 11:42:11 -08:00
Matt Guthaus ee7bf7c5f2 Remove metal3 blanket blockage on library cells. 2017-12-19 09:55:59 -08:00
Matt Guthaus 40465d6518 Merge tolerance change from master. 2017-12-19 09:17:43 -08:00
Matt Guthaus 9059a15ceb Remove tab in lef file. 2017-12-19 09:14:59 -08:00
Matt Guthaus 9a4b2b4341 Revised LEF and Verilog generation. Does not read GDS for speed improvements. 2017-12-19 09:01:24 -08:00
mguthaus 13902538ff Increase lib file tolerance to 25 percent. 2017-12-19 07:41:08 -08:00
Matt Guthaus a4a9205a56 Change thresholds to 50 percent. 2017-12-15 08:02:48 -08:00
Matt Guthaus 7e091fc622 Increase threshold to 30% for SCMOS 2017-12-14 16:52:49 -08:00
Matt Guthaus 819e249526 Remove nor_2 reference 2017-12-12 19:25:35 -08:00
Matt Guthaus e3a6c1ac6b Rewrite CONTRIBUTING.md to add changes relative to dev. Add small changes from orbe7947. 2017-12-12 15:50:45 -08:00
Matt Guthaus abee235963 Rewrite the parameterized transistor and gate classes. 
Changes propagate through all designs.
All modules use instance and layout pins.
 2017-12-12 15:04:01 -08:00
Matt Guthaus 1085497476 Fail when using Magic/netgen for DRC/LVS. Remove arguments in running precharge test. 2017-12-12 13:06:01 -08:00