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OpenRAM
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724 Commits 4 Branches 63 Tags 78 MiB
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584 Commits

Author SHA1 Message Date
Matt Guthaus b50f57ea3a Remove control logic supply rails and replace with M3 supply pins 2018-07-24 10:12:54 -07:00
Matt Guthaus 45a53ed089 Rotate via in center for freepdk 2018-07-19 14:01:48 -07:00
Matt Guthaus 4c3bd0e42b Move WL gnd contacts outside the cell for simplicity 2018-07-19 13:38:45 -07:00
Matt Guthaus beee8229d1 Revert change. Add gnd pin to right on bitline load. 2018-07-19 13:26:12 -07:00
Matt Guthaus ea53066966 Align RBL inverter with first load inverter in delay chain to aid supply connections 2018-07-19 11:02:13 -07:00
Matt Guthaus 311ab97bfc Fix s_en stages to be even per Kevin's bug report. Assert minimum fanout to ensure vdd/gnd connections. 2018-07-19 10:51:20 -07:00
Matt Guthaus 128dfd5830 Add internal vdd/gnd connections for delay chain 2018-07-19 10:37:47 -07:00
Matt Guthaus 51958814a0 Fixing power via problems in freepdk45 2018-07-19 10:23:08 -07:00
Matt Guthaus 9983408fa3 Add verilog_write to sram wrapper for verilog unit test 2018-07-19 10:05:30 -07:00
Matt Guthaus 3f57853969 Use lower case names except for leaf cells and top level 2018-07-18 15:10:57 -07:00
Matt Guthaus 4a139b682d Add temporary options to LVS to allow name merging 2018-07-18 15:10:29 -07:00
Matt Guthaus a9c0ec5549 Add LVS correspondence points to each bank type 2018-07-18 14:29:04 -07:00
Matt Guthaus a878ce5500 Standardize DRC and LVS message levels 2018-07-18 14:28:43 -07:00
Matt Guthaus 58896a6f8e Fix control signal names on control_logic input 2018-07-18 13:41:44 -07:00
Matt Guthaus b88947ef5c Pass the sram design to lib instead of the sram wrapper 2018-07-18 11:51:42 -07:00
Matt Guthaus f43d4cc98f Fix routing clk connections of dff arrays 2018-07-18 11:38:58 -07:00
Matt Guthaus 0701fceb0b Use sram rather than new meta-sram class in the characterizer for delay 2018-07-18 10:39:29 -07:00
Matt Guthaus 1130062343 Fix syntax error in delay test to use new sram wrapper module 2018-07-18 10:33:18 -07:00
Matt Guthaus b8a3bc9b1a Space hier decoder input connections along rails to avoid conflicts 2018-07-18 10:21:58 -07:00
Matt Guthaus b8e3629923 Fix syntax error in unit test 2018-07-17 15:14:22 -07:00
Matt Guthaus 01655b1d54 Clean up tests. Enable 8-way tests. Some tests still have channel route conflicts. 2018-07-17 15:13:00 -07:00
Matt Guthaus ef60b02a81 Add vdd/gnd pins to dff_array 2018-07-17 15:01:31 -07:00
Matt Guthaus 6133d54684 Fix spacing between adjacent decoders 2018-07-17 15:01:16 -07:00
Matt Guthaus ffc866ef78 Single bank working except for channel routing error in 4-way case. 2018-07-17 14:40:04 -07:00
Matt Guthaus 7a69fc1bca Add col addr routing and data routing 2018-07-17 14:24:44 -07:00
Matt Guthaus 0665d51249 Must connect clock at top level for now 2018-07-17 14:24:07 -07:00
Matt Guthaus e82f97cce1 Add create_bus and connect_bus api 2018-07-17 14:23:29 -07:00
Matt Guthaus 0175c88a16 Convert predecodes to use create_bus api 2018-07-17 14:23:06 -07:00
Matt Guthaus ac22b1145f Convert bank to use create_bus routines. 
Modify control logic to have correct offset in SRAM.
 2018-07-16 14:13:41 -07:00
Matt Guthaus 77e786ae5e Fix bug in recomputing boundary with a new offset 2018-07-16 13:46:12 -07:00
Matt Guthaus afcc3563ae Add new supplies to RBL and control logic 2018-07-16 12:58:15 -07:00
Matt Guthaus 93e830e800 Add new supplies to replica bitline 2018-07-16 10:49:43 -07:00
Matt Guthaus 3bbb604504 Add new power supplies to delay chain 2018-07-16 10:19:52 -07:00
Matt Guthaus f3ae29fe0b Getting single bank to work reliably. Removed tri_gate from bank 
for now. Will add it in multibank arrays only. Not needed for
separate DIN and DOUT ports.
 2018-07-13 14:45:46 -07:00
Matt Guthaus 834fbac8de Remove extra print statements. 
Add wrappers for file generation in sram wrapper class.
 2018-07-13 09:38:43 -07:00
Matt Guthaus 0c23efe49b Reference local sram instance in sram.py. 2018-07-13 09:30:14 -07:00
Matt Guthaus a4c29ea527 Improve openram output. Fix save output function name. 2018-07-12 10:35:38 -07:00
Matt Guthaus e6b1fcb44c Refactor banks to use inheritance with a top-level SRAM wrapper class. 2018-07-12 10:30:45 -07:00
Matt Guthaus c71ea51e2e Merge branch 'multiport_cleanup' of github.com:VLSIDA/PrivateRAM into multiport_cleanup 2018-07-11 14:27:41 -07:00
Matt Guthaus 22d40364ec Merge branch 'multiport_cleanup' of https://github.com/VLSIDA/PrivateRAM into multiport_cleanup 2018-07-11 14:27:06 -07:00
Matt Guthaus a2d8d16c7a Split DATA into DIN and DOUT in characterizer 2018-07-11 14:19:09 -07:00
Matt Guthaus 33bb98894f Disable LEF test until supplies fixed. 2018-07-11 14:18:53 -07:00
Matt Guthaus 8be88d14a7 Disable banner output during gitlab runner 2018-07-11 14:18:36 -07:00
Matt Guthaus 7d8352a04d Fix order of checkpointing so that it is done after characterizer and verify have found their executables. 2018-07-11 12:12:03 -07:00
Matt Guthaus 8a530da2cc Remove extra conversion to list 2018-07-11 12:07:37 -07:00
Matt Guthaus 265b5d977a Fix option reload problems and checkpointing so that it works properly. 2018-07-11 12:00:15 -07:00
Matt Guthaus 58646ab8e6 Add DRC/LVS/PEX statistics in verbose=1 mode 2018-07-11 11:59:24 -07:00
Matt Guthaus f894ef47af Fix missing list conversion to run drc library tests. 2018-07-11 11:58:22 -07:00
Matt Guthaus b3732f4fcf Output debug warnings and errors to stderr. Clean up regress script a bit. 2018-07-11 09:51:28 -07:00
Matt Guthaus f82591dd6f Remove outdated README 2018-07-11 09:12:20 -07:00