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OpenRAM
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222 Commits

Author SHA1 Message Date
mrg 971f2ac114 v1.1.8 2020-12-08 10:50:35 -08:00
mrg ebe19abf60 Merge remote-tracking branch 'private/dev' into dev 2020-12-08 10:50:02 -08:00
Arya Reais-Parsi 9eb2f3c0e6 add error message when configuration files are not valid python module names 2020-12-08 10:43:29 -08:00
mrg edf3d9557d Purge temp at the start of every run if it exists. 2020-12-02 11:09:40 -08:00
mrg 0250d9add7 v1.1.7 2020-12-01 17:15:03 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
mrg 0ba2feee53 Fix errors in new run_sim calls and corners 2020-11-09 13:59:46 -08:00
mrg 493c9125f1 Read different modules overrides for different num ports 2020-11-06 11:09:50 -08:00
mrg 18d2987805 Cleanup 2020-11-05 16:30:15 -08:00
mrg 2c76a2680f Adjust openram options. 
Remove option -d (dontpurge) and replace with keeptemp
Add option -d (debug) to drop into pdb.
Add option -k (--keeptemp) to keep temp files
 2020-11-05 13:12:26 -08:00
mrg 3315fe32ba Improve nominal corner message 2020-11-03 16:49:49 -08:00
mrg 45cdecdea9 Improve error message about missing DRC/LVS tools. 2020-11-03 15:47:04 -08:00
mrg 29ac541b28 Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
mrg 87419bd640 Fix bitcell and pbitcell with different cell names 2020-11-03 11:30:40 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg f9787eb878 Use bitcell_base for all bitcells. Fix missing setup_bitcell call 2020-11-02 17:00:15 -08:00
mrg fa89b73ef8 PR from mithro + other changable GDS file names 2020-11-02 16:00:16 -08:00
mrg 1caecf5a69 Undo version and traceback 2020-11-02 10:44:49 -08:00
Tim 'mithro' Ansell 232f754c73 Adding traceback printing to tech file import. 2020-11-02 09:52:00 -08:00
mrg 5268ec547b Merge remote-tracking branch 'private/dev' into dev 2020-10-16 16:51:50 -07:00
mrg 3295a813d6 Don't use single slew for nominal corner 2020-10-16 16:51:28 -07:00
mrg db1bcd0774 Merge remote-tracking branch 'private/dev' into dev 2020-10-16 13:54:43 -07:00
mrg 35c91168f7 Add load/slew scale option to config files 2020-10-16 13:52:36 -07:00
mrg a5e8818014 OpenRAM v1.1.7 
Global and local wordlines.
Many updates all around.
 2020-10-12 09:02:38 -07:00
mrg cb35c0aff4 Add command line -j option for number of threads. 2020-10-05 15:49:00 -07:00
mrg ed9d32c7bc OpenRAM 1.1.6 2020-07-13 16:26:25 -07:00
mrg 443b8fbe23 Change s8 to sky130 2020-06-12 14:23:26 -07:00
Aditi Sinha d5041afebc Merge branch 'dev' into bisr 2020-06-07 16:27:25 +00:00
mrg 5514996708 Auto-generate port dependent cell names. 2020-06-05 15:09:22 -07:00
Aditi Sinha 2498ff07ea Merge branch 'dev' into bisr 2020-05-02 07:48:35 +00:00
mrg 4d6d6af0a1 Merge remote-tracking branch 'public/dev' into dev 2020-04-22 09:28:25 -07:00
mrg 7888e54fc4 Remove dynamic bitcell multiple detection. 
Check for decoder bitcell multiple in tech file or assume 1.
PEP8 fixes.
 2020-04-09 11:38:18 -07:00
Matt Guthaus 75bd2b46a5 OpenRAM v1.1.5 2020-04-09 10:02:15 -07:00
Aditi Sinha b75eeb7688 Merge branch 'dev' into bisr 2020-03-22 21:58:04 +00:00
Aditi Sinha a5afbfe0aa Fixed errors in extra rows characterization 2020-03-22 20:54:49 +00:00
Matt Guthaus 0db0c5a3a9 Update version to 1.1.4 2020-02-25 08:09:08 -08:00
Aditi Sinha 34939ebd70 Merge branch 'dev' into bisr 2020-02-20 17:09:09 +00:00
Aditi Sinha 88bc1f09cb Characterization for extra rows 2020-02-20 17:01:52 +00:00
Bastian Koppelmann 1df16eceb6 sram_factory: Give proper priority to overrides 
modules overridden by the user are the highest priority, then modules
overridden by the technology. If nothing is overriden, use the defaults
from OPTS (if they exist) or use the requested module_type.

This fixes that custom tech_modules could not be used, if they had a default in
OPTS even if the latter was not overridden by the user.

We don't need extra defaults in the tech_modules, as we now only use them,
if they have been overridden by the tech_module.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-19 15:58:00 +01:00
Bastian Koppelmann 306c0b92c3 globals: Add tech module path to Pythonpath if it exists 
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-16 16:56:16 +01:00
Matt Guthaus 46c2cbd2d9 Check nominal_corner_only in new corner creation routine 2019-11-29 14:47:02 -08:00
Matt Guthaus d511f648c6 Move DRC/LVS/PEX tools to tech file. 2019-11-29 12:01:33 -08:00
Matt Guthaus abd8b0a23a Only setup bitcell when running top-level OpenRAM 2019-11-26 13:54:37 -08:00
Matt Guthaus 67a0928303 Merge branch 'dev' into tech_migration 2019-11-21 11:02:33 -08:00
Matt Guthaus 982e12be5e Increment minor version 2019-11-21 11:00:22 -08:00
Matt Guthaus 807923cbf1 Ignore pycache dirs. Fix output error message. 2019-11-21 10:11:19 -08:00
Matthew Guthaus aca99b87bc Fix config for tests 30 2019-11-16 22:22:30 +00:00
Matthew Guthaus c4cf8134fe Undo changes for config expansion. Change unit tests to use OPENRAM_HOME. 2019-11-15 18:47:59 +00:00
Matthew Guthaus 7e9d08206c Fix config import to be location independent 2019-11-14 20:18:18 +00:00
Matt Guthaus 38213d998f Add separate layer and purpose pairs to tech layers. 2019-10-25 10:03:25 -07:00
Matt Guthaus ccc6a67021 Update version to 1.1.2 2019-10-07 12:28:02 -07:00
Matt Guthaus 69c5608b53 Allow gds to be written with supplies off. Fix extraction bug with new options. 2019-09-03 11:23:35 -07:00
Matt Guthaus ee2456f433 Merge branch 'add_wmask' into dev 2019-08-22 15:01:41 -07:00
Matt Guthaus 5f3ffdb8ba Output name and version in help 2019-08-21 14:00:55 -07:00
jsowash d5e331d4f3 Connected en together in write_mask_and_array. 2019-08-09 14:27:53 -07:00
Matt Guthaus 0c5cd2ced9 Merge branch 'dev' into rbl_revamp 2019-07-26 18:01:43 -07:00
jsowash ddf5148fa5 Removed code where if there was no write mask, word_size=write_size. Now it stays None. 2019-07-22 14:58:43 -07:00
mrg a189b325ed Merge remote-tracking branch 'origin/dev' into rbl_revamp 2019-07-12 11:10:07 -07:00
mrg b9d993c88b Add dummy bitcell module. 
Modify bitcell logic to guess if bitcell is not "bitcell"
No longer need to specify replica (and dummy) bitcell explicitly
Add support for 1 or 2 port replica array.
 2019-07-05 12:58:52 -07:00
jsowash 1f76afd294 Begin wmask functionality. Added wmask to verilog file and config parameters. 2019-06-28 15:43:09 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 59d2e45744 Move characterization on/off feedback to report_status. 2019-04-24 11:30:38 -07:00
Matt Guthaus 74f904a509 Cleanup options for front-end. Improve info output. 2019-04-01 10:35:17 -07:00
Matt Guthaus c4c844a8a2 Remove duplicate module name checking since we use the factory 2019-03-06 14:14:46 -08:00
Matt Guthaus cfc14f327e Factor default corner out of import_tech 2019-03-06 07:46:30 -08:00
Matt Guthaus d178801882 Simplify tech organization and import 2019-03-06 07:41:38 -08:00
Matt Guthaus 22deab959c Fix setup_bitcell to allow user to force override the bitcell. 2019-03-03 11:58:41 -08:00
Matt Guthaus abcb1cfa2c Correct elsif to elif 2019-02-28 09:17:24 -08:00
Matt Guthaus da6aa161de Don't autodetect the bitcell if the user overrides it 2019-02-28 09:12:32 -08:00
Matt Guthaus de977732db Only warn if not unit tests 2019-02-25 16:13:54 -08:00
Matt Guthaus 1f1426b97c Add auto-detect of custom bitcells 2019-02-25 16:10:34 -08:00
Matt Guthaus a4b5368302 Add total size in warning for output size. 2019-02-25 14:57:18 -08:00
Matt Guthaus a18071a4ff Add warning for large memory sizes 2019-02-25 10:07:05 -08:00
Matt Guthaus f5f27073be Merge remote-tracking branch 'origin/dev' into factory 2019-01-18 09:52:18 -08:00
Matt Guthaus a418431a42 First draft of sram_factory code 2019-01-16 16:15:38 -08:00
Jesse Cirimelli-Low 87380a4801 complete log file generation 2019-01-13 14:34:46 -08:00
Matt Guthaus cdef5f0ecb Change kbits to bits in output 2019-01-09 16:57:12 -08:00
Jesse Cirimelli-Low e58515b89b tables stable and flask removed, headers are bugged 2019-01-08 19:50:47 -08:00
Matt Guthaus 3f468b1c18 Only print_time when not a unit test or debug_level set 2018-12-07 15:14:28 -08:00
Matt Guthaus 5248482fab Merge branch 'dev' into supply_routing 2018-12-07 14:28:49 -08:00
Matt Guthaus 6f171ad147 Added router timing code. Commented combine adjacent pins due to run-time complexity 2018-12-07 13:54:18 -08:00
Jesse Cirimelli-Low 3d9203a7ea Merge branch 'dev' into datasheet_gen 2018-12-07 04:29:07 -08:00
Matt Guthaus 3f1fbc3d90 Merge remote-tracking branch 'origin' into supply_routing 2018-12-06 13:53:51 -08:00
Matt Guthaus b7bbc9b994 Add output on number of ports. 2018-12-06 11:58:34 -08:00
Matt Guthaus 2cd1322071 Clean up Makefile for unit tests 2018-12-05 12:58:10 -08:00
Jesse Cirimelli-Low 2c12ef2161 added warning to test 30 coverage is not installed 2018-12-03 13:24:22 -08:00
Jesse Cirimelli-Low 59c0421804 merge dev into datasheet_gen; fixed merge conflict in hierarchy_design.py 2018-11-15 10:45:33 -08:00
Matt Guthaus 2f6300c7a0 Fix date/time formatting to remove fraction seconds. 2018-11-14 10:31:33 -08:00
Matt Guthaus ce74827f24 Add new option to enable inline checks at each level of hierarchy. Default is off. 2018-11-13 16:51:19 -08:00
Jesse Cirimelli-Low ce5001e0af added config file to datasheet and output files 2018-10-31 12:29:13 -07:00
Hunter Nichols 62439bdac6 Fixed merge conflicts with sram.py 2018-10-22 17:29:14 -07:00
Matt Guthaus 7591f25a2e Merge branch 'dev' into supply_routing 2018-10-20 14:29:19 -07:00
Jesse Cirimelli-Low 1b4383b945 moved flask_table warning from sram.py to datasheet_gen.py 2018-10-18 09:58:19 -07:00
Jesse Cirimelli-Low b9990609bf provides warning on missing flask packages, does not generate html on missing packages 2018-10-18 07:21:03 -07:00
Matt Guthaus 4932d83afc Add design rules classes for complex design rules 2018-10-12 09:44:36 -07:00
Jesse Cirimelli-Low cfb5921d98 reorganized code structure 2018-10-11 15:59:06 -07:00
Hunter Nichols fd806077d2 Added class and test for testing the delay of several bitcells. 2018-10-08 15:50:52 -07:00