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OpenRAM
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3,953 Commits 4 Branches 63 Tags 78 MiB
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578 Commits

Author SHA1 Message Date
Bugra Onal a7db6d182e Template section clone method 2022-07-08 13:51:07 -07:00
Bugra Onal 5bbb8eae4c TEmplate rework 2022-07-08 13:51:07 -07:00
Bugra Onal 41d04f88f4 Base-verilog 2022-07-08 13:51:07 -07:00
Bugra Onal 4afa391a87 Base template additions 2022-07-08 13:51:07 -07:00
Bugra Onal e6ca67e945 Verilog Template additions 2022-07-08 13:51:07 -07:00
Bugra Onal 31bf5364ee Base verilog template init 2022-07-08 13:51:07 -07:00
mrg 8217a84165 Uniquify overlap points during segment overlap computation. 2022-05-17 13:31:23 -07:00
mrg 9b592ab432 Fix missing hash recompute in vector class. 2022-05-17 13:30:41 -07:00
mrg 4be075e586 Overlap length can include a rectangle overlap. 2022-05-16 14:57:32 -07:00
mrg 74c2c5ae0e Don't double prefix a name 2022-05-13 14:32:52 -07:00
mrg fbb2ea5fb6 Intersection now returns a pin_layout fixed during LEF computation. 2022-05-13 13:56:16 -07:00
mrg 8f2d787d53 Add min area metal in preferred direction 2022-05-11 10:50:32 -07:00
mrg b6c3580e24 Fix width of replica routes. Don't enclose pins if they overlap sufficiently. 2022-05-09 11:44:46 -07:00
mrg 50045e54e8 Fix a couple supply routing issues. 2022-05-03 11:45:51 -07:00
mrg b1bb9151c4 Reimplement off grid pins. 
Long pins aren't accessed on end pins anymore.
Fix problem with multiple non-enclosed space causing blockages.
Add partial pin offgrid enclosure algorithm.
 2022-05-02 15:43:14 -07:00
mrg 64f2f90664 Rework replica_bitcell_array supplies 
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
 2022-04-19 08:50:11 -07:00
mrg 5e546ee974 New power strapping mostly working. 
Each module uses M3/M4 power straps with pins on the ends.
Works in all technologies for a single no mux, dual port SRAM.
 2022-04-05 13:51:55 -07:00
mrg 01a73b31e1 Fix power ring routing boundary bug. 2022-03-18 10:32:25 -07:00
mrg 7e7670581c Add some vertical/horizontal pins for sky130 only 2022-03-16 07:58:29 -07:00
mrg 229a3b5b3d By default uniquify instances based on macro name. 2022-03-11 18:01:45 -08:00
mrg b841e18abd Remove breakpoint 2022-03-07 16:59:55 -08:00
mrg 2796800898 Fix bug with incorrect pitch while adding channel route trunks. 2022-03-07 16:12:20 -08:00
mrg d69e55c2e3 Power routing changes. 
Make the power rails an "experimental_power" option and conditional.
Rename route_vdd_gnd to route_supplies everywhere for consistency.
 2022-03-06 09:56:00 -08:00
mrg 8b3c10ae79 Improvements to power routing. 
Improved the route horizontal and vertical pin functions to
create a single pin at the end.
Swapped A and B on wordline driver input for cleaner routing
in most technologies.
Fixed vertical supply routing in port_address.
 2022-03-04 15:44:07 -08:00
mrg febf7031b1 Fix wrong power layer for min area constraint 2022-03-02 17:04:54 -08:00
mrg 7654cd7295 Allow supply pins on m4 too 2022-03-02 16:47:17 -08:00
mrg 51ba88d896 Port address with vertical power stripes 2022-03-02 16:29:43 -08:00
mrg 0908aa9e25 Add route vertical pins 2022-03-01 14:37:09 -08:00
mrg 54bd022efc Rework precharge route supply horizontally 2022-02-28 11:36:10 -08:00
mrg 7b77378927 Add layer to horizontal pin help and use in precharge 2022-02-25 10:45:25 -08:00
mrg d4c14d7d19 Add horizontal pin helper function 2022-02-23 14:06:19 -08:00
mrg abac5a11ab Move power supply stack to design 2022-02-18 15:02:45 -08:00
mrg e460eff014 Add per tool lvs directories 2021-12-17 10:21:34 -08:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
mrg e6a009312e Move mem reg before usage for compatibility 2021-10-13 09:46:02 -07:00
Hunter Nichols 39ae1270d7 Merge branch 'dev' into cacti_model 2021-09-20 17:01:50 -07:00
mrg 8d9a4cc27b PEP8 cleanup 2021-09-07 16:49:44 -07:00
Hunter Nichols 1236a0773a Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage. 2021-09-07 15:56:27 -07:00
Hunter Nichols 6b8d143073 Changed cacti RC delay function to better match cacti code in bitcell. Sense amp also has similar changed but is missing transconductance parameter. 2021-09-01 14:27:13 -07:00
erendo e9b370bf21 Fix write masks in Verilog 2021-08-29 00:31:32 +03:00
Hunter Nichols 680d7b5d93 Added special RC delay functions for the bitline and sense amp to match CACTI. Contains temporary parameters which need to be defined. 2021-08-25 16:12:05 -07:00
Hunter Nichols 12c03ddd9f Fixed issues with load capcitance units. Changed freepdk45 r and c wire values to be more in line with cacti. 2021-08-16 22:58:26 -07:00
Hunter Nichols b3500982ca Fixed issue with wire resistance in total resistance equations for cacti. Fixed issue with sense amp resistance values. 2021-08-04 16:10:27 -07:00
Hunter Nichols b44f840814 Changed delay calculation to include wire resistance and wire capacitance. Added bitline r and c values. 2021-08-01 19:25:54 -07:00
Hunter Nichols 1b89533d7b Added unit r and c values with m2 minwidth incorporated to match CACTI params 2021-08-01 00:23:59 -07:00
biarmic 85955ce298 Fix addr flop in Verilog 2021-07-30 12:22:55 +03:00
Hunter Nichols 54cbef1aff Replaced cacti tech params with already existing params. Added an existence check in design_rules. 2021-07-27 14:31:22 -07:00
Hunter Nichols 1e08005639 Merge branch 'dev' into cacti_model 2021-07-26 14:35:47 -07:00
Hunter Nichols 3e0a49e58d Added options for the model type in timing graph (cacti or elmore) 2021-07-25 22:28:23 -07:00
Hunter Nichols 5ad86538d4 Renamed graph_util to timing_graph to match the module name 2021-07-25 20:21:54 -07:00