mirror of https://github.com/VLSIDA/OpenRAM.git
Add per tool lvs directories
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mrg
parent
4fa084f272
commit
e460eff014
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@ -17,6 +17,7 @@ from wire_spice_model import wire_spice_model
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from power_data import power_data
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import logical_effort
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class spice():
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"""
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This provides a set of useful generic types for hierarchy
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@ -36,14 +37,15 @@ class spice():
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# If we have a separate lvs directory, then all the lvs files
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# should be in there (all or nothing!)
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try:
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lvs_subdir = tech.lvs_lib
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except AttributeError:
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lvs_subdir = "lvs_lib"
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lvs_dir = OPTS.openram_tech + lvs_subdir + "/"
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from tech import lvs_name
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lvs_dir = OPTS.openram_tech + lvs_name + "_lvs_lib/"
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except ImportError:
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lvs_dir = OPTS.openram_tech + "lvs_lib/"
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if not os.path.exists(lvs_dir):
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lvs_dir = OPTS.openram_tech + "lvs_lib/"
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if os.path.exists(lvs_dir):
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self.lvs_file = lvs_dir + cell_name + ".sp"
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else:
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self.lvs_file = lvs_dir + cell_name + ".sp"
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if not os.path.exists(self.lvs_file):
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self.lvs_file = self.sp_file
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self.valid_signal_types = ["INOUT", "INPUT", "OUTPUT", "BIAS", "POWER", "GROUND"]
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@ -277,7 +279,10 @@ class spice():
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# parses line into ports and remove subckt
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lvs_pins = subckt_line.split(" ")[2:]
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debug.check(lvs_pins == self.pins,
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"Spice netlists for LVS and simulation have port mismatches: {0} (LVS) vs {1} (sim)".format(lvs_pins, self.pins))
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"Spice netlists for LVS and simulation have port mismatches:\n{0} (LVS {1})\nvs\n{2} (sim {3})".format(lvs_pins,
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self.lvs_file,
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self.pins,
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self.sp_file))
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def check_net_in_spice(self, net_name):
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"""Checks if a net name exists in the current. Intended to be check nets in hand-made cells."""
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@ -419,7 +424,7 @@ class spice():
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self.cacti_params = cacti_params
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# Get the r_on the the tx
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rd = self.get_on_resistance()
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# Calculate the intrinsic capacitance
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# Calculate the intrinsic capacitance
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c_intrinsic = self.get_intrinsic_capacitance()
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# Get wire values
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c_wire = self.module_wire_c()
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@ -453,13 +458,13 @@ class spice():
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def module_wire_c(self):
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"""All devices assumed to have ideal capacitance (0).
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Non-ideal cases should have this function re-defined.
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Non-ideal cases should have this function re-defined.
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"""
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return 0
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def module_wire_r(self):
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"""All devices assumed to have ideal resistance (0).
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Non-ideal cases should have this function re-defined.
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Non-ideal cases should have this function re-defined.
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"""
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return 0
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@ -517,19 +522,19 @@ class spice():
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self.cell_name))
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return 0
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def cacti_rc_delay(self,
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def cacti_rc_delay(self,
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inputramptime, # input rise time
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tf, # time constant of gate
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vs1, # threshold voltage
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vs2, # threshold voltage
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rise, # whether input rises or fall
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extra_param_dict=None):
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extra_param_dict=None):
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"""By default, CACTI delay uses horowitz for gate delay.
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Can be overriden in cases like bitline if equation is different.
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"""
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return self.horowitz(inputramptime, tf, vs1, vs2, rise)
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def horowitz(self,
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def horowitz(self,
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inputramptime, # input rise time
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tf, # time constant of gate
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vs1, # threshold voltage
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@ -549,17 +554,17 @@ class spice():
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td = tf * math.sqrt(math.log(1.0 - vs1)*math.log(1.0 - vs1) + 2*a*b*(vs1)) + tf*(math.log(1.0 - vs1) - math.log(1.0 - vs2))
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return td
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def tr_r_on(self, width, is_nchannel, stack, _is_cell):
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def tr_r_on(self, width, is_nchannel, stack, _is_cell):
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restrans = self.cacti_params["r_nch_on"] if is_nchannel else self.cacti_params["r_pch_on"]
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return stack * restrans / width
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def gate_c(self, width):
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return (tech.spice["c_g_ideal"] + tech.spice["c_overlap"] + 3*tech.spice["c_fringe"])*width +\
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tech.drc["minlength_channel"]*tech.spice["cpolywire"]
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def drain_c_(self,
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width,
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stack,
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@ -570,10 +575,10 @@ class spice():
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c_fringe = 2*tech.spice["c_overlap"]
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c_overlap = 2*tech.spice["c_fringe"]
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drain_C_metal_connecting_folded_tr = 0
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w_folded_tr = width/folds
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num_folded_tr = folds
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# Re-created some logic contact to get minwidth as importing the contact
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# module causes a failure
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if "minwidth_contact" in tech.drc:
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@ -595,10 +600,10 @@ class spice():
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if num_folded_tr%2 == 0:
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drain_h_for_sidewall = 0
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total_drain_height_for_cap_wrt_gate *= num_folded_tr
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drain_C_metal_connecting_folded_tr = tech.spice["wire_c_per_um"] * total_drain_w
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drain_C_area = c_junc_area * total_drain_w * w_folded_tr
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drain_C_sidewall = c_junc_sidewall * (drain_h_for_sidewall + 2 * total_drain_w)
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