mirror of https://github.com/VLSIDA/OpenRAM.git
Add min area metal in preferred direction
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b6c3580e24
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@ -597,8 +597,14 @@ class layout():
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start=top_pos,
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end=bot_pos)
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def get_metal_layers(self, from_layer, to_layer):
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from_id = layer_indices[from_layer]
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to_id = layer_indices[to_layer]
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layer_list = [x for x in layer_indices.keys() if layer_indices[x] >= from_id and layer_indices[x] < to_id]
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return layer_list
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def route_vertical_pins(self, name, insts=None, layer=None, xside="cx", yside="cy", full_width=True):
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@ -647,8 +653,7 @@ class layout():
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last_via = self.add_via_stack_center(from_layer=pin.layer,
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to_layer=pin_layer,
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offset=vector(x, y),
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min_area=True)
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offset=vector(x, y))
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if last_via:
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via_width=last_via.mod.second_layer_width
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@ -1076,6 +1081,8 @@ class layout():
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offset=offset)
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return None
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intermediate_layers = self.get_metal_layers(from_layer, to_layer)
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via = None
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cur_layer = from_layer
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while cur_layer != to_layer:
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@ -1098,7 +1105,9 @@ class layout():
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implant_type=implant_type,
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well_type=well_type)
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if cur_layer != from_layer or min_area:
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# Only add the enclosure if we are in an intermediate layer
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# or we are forced to
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if min_area or cur_layer in intermediate_layers:
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self.add_min_area_rect_center(cur_layer,
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offset,
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via.mod.first_layer_width,
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@ -1124,14 +1133,18 @@ class layout():
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min_width = drc("minwidth_{}".format(layer))
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if preferred_directions[layer] == "V":
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height = max(min_area / width, min_width)
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new_height = max(min_area / width, min_width)
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new_width = width
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else:
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width = max(min_area / height, min_width)
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new_width = max(min_area / height, min_width)
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new_height = height
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debug.check(min_area <= round_to_grid(new_height*new_width), "Min area violated.")
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self.add_rect_center(layer=layer,
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offset=offset,
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width=width,
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height=height)
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width=new_width,
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height=new_height)
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def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"):
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"""Adds a ptx module to the design."""
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