 mrg
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8d71a98ce9
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Make purposes argument to gdsMill. Create prefixGDS.py script.
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2021-06-22 14:40:43 -07:00 |
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 Hunter Nichols
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a0921b4afc
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Merge branch 'dev' into automated_analytical_model
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2021-06-22 01:39:38 -07:00 |
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mrg
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6e22771794
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2021-06-21 17:37:41 -07:00 |
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mrg
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58f8c66020
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Fix disconnected spare_wen_0_0
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2021-06-21 17:36:20 -07:00 |
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Hunter Nichols
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294ccf602e
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Merged with dev, addressed conflict in port data
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2021-06-21 17:23:32 -07:00 |
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Hunter Nichols
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470317eaa4
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Changed bitcell exclusion to instead exclude array instances to prevent issues of module exclusion affecting other modules.
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2021-06-21 17:20:25 -07:00 |
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Hunter Nichols
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b408a871f9
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Added direction information functions to 2-port bitcell modules
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2021-06-21 17:19:15 -07:00 |
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 Jesse Cirimelli-Low
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3502bec231
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Merge remote-tracking branch 'origin/dev' into dev
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2021-06-21 15:27:32 -07:00 |
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mrg
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bb1ac1a38e
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Fix incorrect bus indexing of spare_wen. Convert internal signals to not use braces.
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2021-06-21 15:23:08 -07:00 |
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Jesse Cirimelli-Low
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2760beae34
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swap sky130 replica bitcell array power bias routing
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2021-06-21 15:22:31 -07:00 |
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mrg
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f3f19aeeeb
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Remove print statement
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2021-06-21 15:16:36 -07:00 |
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mrg
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1ce5823df8
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2021-06-21 13:14:23 -07:00 |
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mrg
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d53bc98ff5
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Exit with error when spice models not found. Use ngspice if no simulator defined.
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2021-06-21 13:14:08 -07:00 |
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mrg
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af31027504
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Fix error in 1 spare column Verilog
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2021-06-21 13:13:53 -07:00 |
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Jesse Cirimelli-Low
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56dc83de47
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fix typo
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2021-06-18 18:10:12 -07:00 |
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Jesse Cirimelli-Low
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2dbe928c09
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fix typo
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2021-06-18 18:08:57 -07:00 |
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Jesse Cirimelli-Low
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4688988434
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only check dimensions on single port
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2021-06-18 17:46:39 -07:00 |
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Jesse Cirimelli-Low
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0008df0204
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catch where strap size is zero
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2021-06-18 15:24:24 -07:00 |
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Jesse Cirimelli-Low
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2eb98083d0
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Merge branch 'dev' into laptop_checkpoint
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2021-06-18 14:21:39 -07:00 |
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Jesse Cirimelli-Low
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8ceece2af6
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check for valid dimensions instead of recalcuating
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2021-06-18 14:21:02 -07:00 |
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mrg
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693a81fa8d
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Fix spare_wen IO pin names
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2021-06-18 10:44:35 -07:00 |
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mrg
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1299989332
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Fix single spare_wen naming
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2021-06-18 08:43:21 -07:00 |
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mrg
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67877175b2
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Fix error in no spare column verilog
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2021-06-18 08:41:26 -07:00 |
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mrg
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81d20ec2aa
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Add spare cols to behavioral Verilog model
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2021-06-18 07:23:41 -07:00 |
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Jesse Cirimelli-Low
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7b7c72706a
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merge in dev
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2021-06-17 09:49:32 -07:00 |
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Jesse Cirimelli-Low
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d9afe89770
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remove print statement
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2021-06-17 03:23:46 -07:00 |
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Jesse Cirimelli-Low
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1ce6b4d41a
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fix freepdk45
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2021-06-17 03:21:01 -07:00 |
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Hunter Nichols
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131ff8bcef
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Changed the regression test to only run models for the output being tested.
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2021-06-16 23:50:20 -07:00 |
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mrg
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afe0902547
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Enable small short func tests
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2021-06-16 19:13:50 -07:00 |
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mrg
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b7f1c8e8fc
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Fix name for detecting single port
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2021-06-16 19:07:56 -07:00 |
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mrg
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c7c319c11f
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Use extra bitcell version tag only for single port in sky130
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2021-06-16 19:06:12 -07:00 |
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mrg
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d119a0e7ff
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Use sky130 bitcell in simulation for BLs
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2021-06-16 18:45:53 -07:00 |
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mrg
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1e486cd344
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Use local spacing rule
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2021-06-16 18:41:39 -07:00 |
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Hunter Nichols
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16e658726e
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When determining bitline names, added a technology check for sky130.
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2021-06-16 17:04:02 -07:00 |
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Jesse Cirimelli-Low
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e775f7a355
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fixed indent
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2021-06-16 12:36:00 -07:00 |
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Jesse Cirimelli-Low
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2b9df2ff1f
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uncomment function sim and datasheet generation
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2021-06-16 11:23:27 -07:00 |
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mrg
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6ac082ce23
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Only replace simulator if it is defined.
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2021-06-16 10:44:13 -07:00 |
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mrg
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1adada9e27
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Merge branch 'dev' into xyce
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2021-06-16 09:52:17 -07:00 |
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Jesse Cirimelli-Low
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25bc178132
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extend input rail
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2021-06-14 15:13:17 -07:00 |
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Hunter Nichols
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4132decd32
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Merge branch 'dev' into automated_analytical_model
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2021-06-14 14:45:48 -07:00 |
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Hunter Nichols
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74b55ea83b
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Added a graph exclusion clear for the mux to prevent previous graph creations causing bugs.
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2021-06-14 14:39:54 -07:00 |
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Hunter Nichols
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7df36a916b
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Added an exclusion for unused column mux paths to prevent multiple outputs paths in graph.
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2021-06-14 13:51:52 -07:00 |
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Hunter Nichols
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4d22201055
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Changed name of regression test since we currently only test the delay.
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2021-06-14 10:57:20 -07:00 |
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mrg
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159d0ed603
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Fix s_en spacing problem.
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2021-06-13 15:08:05 -07:00 |
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mrg
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53107a8322
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Add ring test
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2021-06-13 15:03:41 -07:00 |
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mrg
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d6a72aed37
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Add 2x1 perimter pins to satisfy minimum area rule.
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2021-06-13 15:00:46 -07:00 |
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mrg
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2e23fffadd
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Fix comment
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2021-06-13 14:18:55 -07:00 |
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Jesse Cirimelli-Low
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73cc6b3891
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uncomment 4x16 decoder
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2021-06-11 18:20:36 -07:00 |
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Jesse Cirimelli-Low
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bee9b07516
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fix decoder routing
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2021-06-11 18:19:07 -07:00 |
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Jesse Cirimelli-Low
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2e72da0e53
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rotate input to rail contacts for drc
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2021-06-10 14:01:28 -07:00 |
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