mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 17:39:02 +02:00
fixed indent
This commit is contained in:
@@ -142,7 +142,7 @@ class sram():
|
||||
start_time = datetime.datetime.now()
|
||||
from characterizer import lib
|
||||
debug.print_raw("LIB: Characterizing... ")
|
||||
lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
|
||||
lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
|
||||
print_time("Characterization", datetime.datetime.now(), start_time)
|
||||
|
||||
# Write the config file
|
||||
@@ -157,7 +157,7 @@ class sram():
|
||||
from datasheet_gen import datasheet_gen
|
||||
dname = OPTS.output_path + self.s.name + ".html"
|
||||
debug.print_raw("Datasheet: Writing to {0}".format(dname))
|
||||
datasheet_gen.datasheet_write(dname)
|
||||
datasheet_gen.datasheet_write(dname)
|
||||
print_time("Datasheet", datetime.datetime.now(), start_time)
|
||||
|
||||
# Write a verilog model
|
||||
|
||||
Reference in New Issue
Block a user